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Mon, 16 Dec 2024 23:44:11 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , "Mohan Kumar D" Subject: [PATCH v2 RESEND 1/2] dt-bindings: dma: Support channel page to nvidia,tegra210-adma Date: Tue, 17 Dec 2024 13:13:57 +0530 Message-ID: <20241217074358.340180-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241217074358.340180-1-mkumard@nvidia.com> References: <20241217074358.340180-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C9:EE_|MN0PR12MB6002:EE_ X-MS-Office365-Filtering-Correlation-Id: 745f9210-6303-48f5-ff94-08dd1e6e9e52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: MDYo3zgcJwKAAM4m8uhshhsy71TwKrAmMQl1JW2lALIBV3XqNbYPe/mCaToSPzJL683qAstAmTUcaO7xKLIw7X/+jQWoUOEpYmWCWbMhlDHYlF7qr/S2m08vYvsaJXw1KfAtIL8f4HevmuF5SJGzke5xVQIW0r731qyLncdPeYiwQ8TbTKaKt0xPJIeRH7PuslYmEikqe8TrPmhcs4NT7X8E0B3DGj3sV0Spx4REmrcFmfZykpgomZNEPL3lqKbwg1+yrCCShzGuStqfQCM1iO/jP8231mcm47bis3fCM7WoBNqGjtQTgCenOwzqqLmGaLzrkD63wV0HHCeVSgkkbgM3wEOVBkFrGYkfM7g58TVWBq3832GLTjChXGIYTRNIlyluZ0eOKyHE3ZCtHUHCKb622wW4JLmkpkCgL4aEX/bFQuOGU6rHYyB69pc9Fy5HOZlze/cgbqKnL87YydRQSLBgfQs7Rii1+en0VelCWR2dThsOR8QGWkv9q5TwF6OZ7t6L0tahmL38YMT4KsXkq3OXwac7Trpd3Ctmt6ZyJnz2bXIUDVF5d2pj1u6SviaTkr87JMO4QSNKAcrpevDj9jFzLCJH8PYHPnchuqirfTsbFwDTIwA/RQNbOEwfuXZvMT6Hi9ORGaZ8+G023q2rqjxvbpMd5yI5MWzOQIUWffhJWOeDiI5ZPwbSkEcqiMgxHA2zHhOSpRE3dNawKvRfpZbtJi/i2r7ff183XDbZBQFSB5m6iG7bE8D/DwPIgbDzyBXnTltx+EIWFXXooWWKygSCR5J5GKw6HnWtSoUIbHP8OJxV+TbdSW2ttsiFrRCsDRkTaU6yzc5o0e6kXuxI19bagDMZRQWB0QLiU1tNQkffWXy9+E5s6RZZ1Yt18d9a7JH1ry/zS4CX3xH9srvn6E5QobQAVfS03bpSY1Mo0huR1UmR3U/+o9QsEtEYeUkXA3HdqQw+1e8HpS8o5h0Ru6t8ySS6VSpTf2mdZI8hTcMUd99ISZbjtQzQ6T2GhHSQQ5fGNbz72jeS55mAhmBQ6fMOPqt9OcEdkc+l5Bnb6Ybv0KexUdH0Xl9vHAvqYJ6/ibLhaD5Z4uExKVnCydw5Ol7LAxne0cRE3St8A9r0jk5B6Ie8M6pF7vj5ixfzw52EMB4mdzKxA1BZU3+wQRxpwqcIpZcG8GzqK8TB1BRG8mM3l87qA44x6+bbkp4o3M4qr9izxAWIWYpqogEw7Wh3MIsDwWhWXNOX5qO9EJwleHppPv79LXT6eQJUX+ICm2yOpnO1kGYG7qxyTGCPAd5oz12+Y21FIINWCoorreBYkRDCMO0zFE0bWHlEyuT3yWhdrns2E/OZbrYLEQrdAM3q5iMSxiRZp1phrxbpeb2K8EupIi0sBQL25dt9kpLu/9eG4DWTnOWTNSFCD9LDQVSJORrJ9BrK3XWeAtvf/KILEfkTPBPR+K6G/LGrOwam7RlqkeXSBLYiv8jNAVpcN3dtZF2gPSSGEjg/iZxXuNZQ/UE= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 07:44:20.7797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 745f9210-6303-48f5-ff94-08dd1e6e9e52 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6002 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D Acked-by: Conor Dooley --- .../bindings/dma/nvidia,tegra210-adma.yaml | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..d3f8c269916c 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -13,9 +13,6 @@ description: | maintainers: - Jon Hunter -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: @@ -29,7 +26,19 @@ properties: - const: nvidia,tegra186-adma reg: - maxItems: 1 + description: + The 'page' region describes the address space of the page + used for accessing the DMA channel registers. The 'global' + region describes the address space of the global DMA registers. + In the absence of the 'reg-names' property, there must be a + single entry that covers the address space of the global DMA + registers and the DMA channel registers. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 interrupts: description: | @@ -63,6 +72,49 @@ required: - clocks - clock-names +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-adma + then: + properties: + reg: + items: + - description: Full address space range of DMA registers. + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + anyOf: + - properties: + reg: + items: + - description: Full address space range of DMA registers. + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + reg-names: + items: + - const: page + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + - description: Global Page address space range of DMA registers. + reg-names: + items: + - const: page + - const: global + additionalProperties: false examples: From patchwork Tue Dec 17 07:43:58 2024 Content-Type: text/plain; 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Mon, 16 Dec 2024 23:44:15 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , "Mohan Kumar D" Subject: [PATCH v2 RESEND 2/2] dmaengine: tegra210-adma: Support channel page Date: Tue, 17 Dec 2024 13:13:58 +0530 Message-ID: <20241217074358.340180-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241217074358.340180-1-mkumard@nvidia.com> References: <20241217074358.340180-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C9:EE_|PH8PR12MB6940:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b7c9183-358b-440a-98e7-08dd1e6ea0cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: HizunEHJdLO3pqGQjsrKNsmkkpIyYdk0KSfUYSkSBmGz6SUuCQROByQFcrzd4sUn3wk8fewdCfZRfTniBYAMYCWNb3wYrlV99Fmc9W9ZDRIW0Icnc5ZtSFgitLMvzZ4aqgaph5zqEp/3sRW5Q5isi2rtSzBthHAcqi3/0IUOSDhKsHKKNbf1MYWy/uiYcenaXEMIRkPVp7c+i53sKAeIcFjdFr1tmZsc9E9+ewxCC62Kx47mwHxh5+h41zInMcRQEuPhf7SpFafJtUijzUxtNp2IfUzs7sd6/7WqvMKNoPIc5thXIw+Bcv4OK4fYqn+L1JQ4kVOBbT8Wjk1QSfwunYMDOhjkn9gWCC6GAS9QmVXwxPfQXr/sxgD6qYz59w6ATfPd0G1MEX996JASKp3QKgMhYyHYvGMagElWOxbX1O/okx7XEk7Q6ffJgmHHFMfFyPLHR42IsWxcjwIhRuc3SoPmxy8GofPQDvia0zaadAIUs5J7t8Y5+R0MoP6a/1Ll4TWO8K3Fe3it83AHduuFf0D68uCnTOrHEpLX4KivIeZUWczuVps6nFsy5KSMUWOtNUQzrYsgUYfA/hjZ15Iz8kMBFsn3mNSHY/CGMR8AYDc3iOI2GwObqjcXGznEvFH1Mc/ikFXwX7Mfq3XvnUAK6RNFVUWJgljrg4nLhrIo1XAW07NdkjXfUyk3tO4uxXYrJTkK/ayMgmOOZckLFaBTH37U8ojNSfZVCAHvhbVccOqzNsQDCUBvLFBo7dYN1t10mDKzKn/gfzJREo17tcsca7Y5Eewqpe4/04o8B+06idv0iO7gnAbikWGRcPlbTCTKKoruxGoVhkqnRlIkfYtC40OQHN4iUzlga8WpAZVHUukStYFJfNslhU4CT4EgNb+LVAElAZOtYHMH590D4HhLiTKFlY1qYhjQXHD4k12PvMuxtK+hHqUV55tyaPI08EXpQ5IwPg0jKPF6EWBA/EMbeLAfOkRc/yILKEgjIQyw6Ygc5rJlRuPeDh5GMSjlD0A6WKsk34i9rhfEUvWE6H1MDM27eshdpr6kJbAy7EhVdviPtd+aqtxI/V+j+uAJxADwMM26h4OPTyxlYV0CTyvr6v5Zr1vcRu0wGz3A+Tanugc6SpiQb6cxJkd6JjBSR1UDdJGe5aSkbjT98X1zV30yT1RME2jWoft52u+RYViQrXr6SQJRENwuFg8SwhSaeHgFSw5mrAAVtwwaSgcISXGUyjWZUtxHuucbV9YDfJxGlm34FjLUZ90wGNKs1x9no5jorNS9maaBJiiO7/HWnHvrvqxPREHY92cm62QkIu9M4fNdUtKLt9ilUDn1sVY2kgmP3LxZjcEwb0/1xX9oEDiAFW8T99D6LRk01tIVwjZwRN/F6+Xbn5FU9qThzVAujH6+ZzVC6zxdh7Wp8mv8n+IiY+n4Z1eQ3DDLRgqzXIVoRbn6JhLYcbqT32qnuHpcnMtCloNjXNH5EEu+lLLjDi7Wrz48BtlSOXqN27Od+HIg6vc= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 07:44:24.9360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b7c9183-358b-440a-98e7-08dd1e6ea0cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6940 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. - Add support in the tegra adma driver to handle selective channel page usage - Make global register programming optional Signed-off-by: Mohan Kumar D --- drivers/dma/tegra210-adma.c | 86 ++++++++++++++++++++++++++++++++----- 1 file changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 2953008d42ef..6896da8ac7ef 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -43,6 +43,10 @@ #define ADMA_CH_CONFIG_MAX_BUFS 8 #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4) +#define TEGRA186_ADMA_GLOBAL_PAGE_CHGRP 0x30 +#define TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ 0x70 +#define TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ 0x84 + #define ADMA_CH_FIFO_CTRL 0x2c #define ADMA_CH_TX_FIFO_SIZE_SHIFT 8 #define ADMA_CH_RX_FIFO_SIZE_SHIFT 0 @@ -96,6 +100,7 @@ struct tegra_adma_chip_data { unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; bool has_outstanding_reqs; + void (*set_global_pg_config)(struct tegra_adma *tdma); }; /* @@ -151,6 +156,7 @@ struct tegra_adma { struct dma_device dma_dev; struct device *dev; void __iomem *base_addr; + void __iomem *ch_base_addr; struct clk *ahub_clk; unsigned int nr_channels; unsigned long *dma_chan_mask; @@ -159,6 +165,7 @@ struct tegra_adma { /* Used to store global command register state when suspending */ unsigned int global_cmd; + unsigned int ch_page_no; const struct tegra_adma_chip_data *cdata; @@ -176,6 +183,11 @@ static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg) return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); } +static inline void tdma_ch_global_write(struct tegra_adma *tdma, u32 reg, u32 val) +{ + writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg); +} + static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) { writel(val, tdc->chan_addr + reg); @@ -217,13 +229,30 @@ static int tegra_adma_slave_config(struct dma_chan *dc, return 0; } +static void tegra186_adma_global_page_config(struct tegra_adma *tdma) +{ + /* + * Clear the default page1 channel group configs and program + * the global registers based on the actual page usage + */ + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP + (tdma->ch_page_no * 0x4), 0xff); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ + (tdma->ch_page_no * 0x4), 0x1ffffff); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0x4), 0xffffff); +} + static int tegra_adma_init(struct tegra_adma *tdma) { u32 status; int ret; - /* Clear any interrupts */ - tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); + /* Clear any channels group global interrupts */ + tdma_ch_global_write(tdma, tdma->cdata->global_int_clear, 0x1); + + if (!tdma->base_addr) + return 0; /* Assert soft reset */ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); @@ -237,6 +266,9 @@ static int tegra_adma_init(struct tegra_adma *tdma) if (ret) return ret; + if (tdma->cdata->set_global_pg_config) + tdma->cdata->set_global_pg_config(tdma); + /* Enable global ADMA registers */ tdma_write(tdma, ADMA_GLOBAL_CMD, 1); @@ -736,7 +768,9 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) struct tegra_adma_chan *tdc; int i; - tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (tdma->base_addr) + tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->global_cmd) goto clk_disable; @@ -777,7 +811,11 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) dev_err(dev, "ahub clk_enable failed: %d\n", ret); return ret; } - tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + if (tdma->base_addr) { + tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + if (tdma->cdata->set_global_pg_config) + tdma->cdata->set_global_pg_config(tdma); + } if (!tdma->global_cmd) return 0; @@ -817,6 +855,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { .ch_fifo_size_mask = 0xf, .sreq_index_offset = 2, .has_outstanding_reqs = false, + .set_global_pg_config = NULL, }; static const struct tegra_adma_chip_data tegra186_chip_data = { @@ -833,6 +872,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { .ch_fifo_size_mask = 0x1f, .sreq_index_offset = 4, .has_outstanding_reqs = true, + .set_global_pg_config = tegra186_adma_global_page_config, }; static const struct of_device_id tegra_adma_of_match[] = { @@ -846,7 +886,8 @@ static int tegra_adma_probe(struct platform_device *pdev) { const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; - int ret, i; + struct resource *res_page, *res_base; + int ret, i, page_no; cdata = of_device_get_match_data(&pdev->dev); if (!cdata) { @@ -865,9 +906,35 @@ static int tegra_adma_probe(struct platform_device *pdev) tdma->nr_channels = cdata->nr_channels; platform_set_drvdata(pdev, tdma); - tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(tdma->base_addr)) - return PTR_ERR(tdma->base_addr); + res_page = platform_get_resource_byname(pdev, IORESOURCE_MEM, "page"); + if (res_page) { + tdma->ch_base_addr = devm_ioremap_resource(&pdev->dev, res_page); + if (IS_ERR(tdma->ch_base_addr)) + return PTR_ERR(tdma->ch_base_addr); + + res_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global"); + if (res_base) { + page_no = (res_page->start - res_base->start) / cdata->ch_base_offset; + if (page_no <= 0) + return -EINVAL; + tdma->ch_page_no = page_no - 1; + tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + } + } else { + /* If no 'page' property found, then reg DT binding would be legacy */ + res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_base) { + tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + } else { + return -ENODEV; + } + + tdma->ch_base_addr = tdma->base_addr + cdata->ch_base_offset; + } tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); if (IS_ERR(tdma->ahub_clk)) { @@ -900,8 +967,7 @@ static int tegra_adma_probe(struct platform_device *pdev) if (!test_bit(i, tdma->dma_chan_mask)) continue; - tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset - + (cdata->ch_reg_size * i); + tdc->chan_addr = tdma->ch_base_addr + (cdata->ch_reg_size * i); tdc->irq = of_irq_get(pdev->dev.of_node, i); if (tdc->irq <= 0) {