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Wed, 18 Dec 2024 06:20:50 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/5] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling Date: Wed, 18 Dec 2024 14:20:41 +0000 Message-ID: <20241218142045.77269-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Avoid triggering a `refcount_t: addition on 0; use-after-free.` warning when registering a module clock with the same MSTOP configuration. The issue arises when a module clock is registered but not enabled, resulting in a `ref_cnt` of 0. Subsequent calls to `refcount_inc()` on such clocks cause the kernel to warn about use-after-free. [    0.113529] ------------[ cut here ]------------ [    0.113537] refcount_t: addition on 0; use-after-free. [    0.113576] WARNING: CPU: 2 PID: 1 at lib/refcount.c:25 refcount_warn_saturate+0x120/0x144 [    0.113602] Modules linked in: [    0.113616] CPU: 2 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.13.0-rc3+ #446 [    0.113629] Hardware name: Renesas RZ/V2H EVK Board based on r9a09g057h44 (DT) [    0.113641] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [    0.113652] pc : refcount_warn_saturate+0x120/0x144 [    0.113664] lr : refcount_warn_saturate+0x120/0x144 [    0.113675] sp : ffff8000818aba90 [    0.113682] x29: ffff8000818aba90 x28: ffff0000c0d96450 x27: ffff0000c0d96440 [    0.113699] x26: 0000000000000014 x25: 0000000000051000 x24: ffff0000c0ad6480 [    0.113714] x23: ffff0000c0d96200 x22: ffff800080fae558 x21: 00000000000001e0 [    0.113730] x20: ffff0000c0b11c10 x19: ffff8000815ae6f0 x18: 0000000000000006 [    0.113745] x17: ffff800081765368 x16: 0000000000000000 x15: 0765076507720766 [    0.113760] x14: ffff8000816a3ea0 x13: 0765076507720766 x12: 072d077207650774 [    0.113776] x11: ffff8000816a3ea0 x10: 00000000000000ce x9 : ffff8000816fbea0 [    0.113791] x8 : 0000000000017fe8 x7 : 00000000fffff000 x6 : ffff8000816fbea0 [    0.113806] x5 : 80000000fffff000 x4 : 0000000000000000 x3 : 0000000000000000 [    0.113821] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000c0158000 [    0.113837] Call trace: [    0.113845]  refcount_warn_saturate+0x120/0x144 (P) [    0.113859]  rzv2h_cpg_probe+0x7f8/0xa38 [    0.113874]  platform_probe+0x68/0xdc [    0.113890]  really_probe+0xbc/0x2c0 [    0.113901]  __driver_probe_device+0x78/0x120 [    0.113912]  driver_probe_device+0x3c/0x154 [    0.113923]  __driver_attach+0x90/0x1a0 [    0.113933]  bus_for_each_dev+0x7c/0xe0 [    0.113944]  driver_attach+0x24/0x30 [    0.113954]  bus_add_driver+0xe4/0x208 [    0.113965]  driver_register+0x68/0x124 [    0.113975]  __platform_driver_probe+0x54/0xd4 [    0.113987]  rzv2h_cpg_init+0x24/0x30 [    0.113998]  do_one_initcall+0x60/0x1d4 [    0.114013]  kernel_init_freeable+0x214/0x278 [    0.114028]  kernel_init+0x20/0x140 [    0.114041]  ret_from_fork+0x10/0x20 [    0.114052] ---[ end trace 0000000000000000 ]--- Resolve this by checking the `ref_cnt` value before calling `refcount_inc()`. If `ref_cnt` is 0, reset it to 1 using `refcount_set()`. Fixes: 7bd4cb3d6b7c ("clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver") Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 668a2880b2d3..23c89b0de38a 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -565,8 +565,12 @@ static struct rzv2h_mstop continue; if (BUS_MSTOP(clk->mstop->idx, clk->mstop->mask) == mstop_data) { - if (rzv2h_mod_clock_is_enabled(&clock->hw)) - refcount_inc(&clk->mstop->ref_cnt); + if (rzv2h_mod_clock_is_enabled(&clock->hw)) { + if (refcount_read(&clk->mstop->ref_cnt)) + refcount_inc(&clk->mstop->ref_cnt); + else + refcount_set(&clk->mstop->ref_cnt, 1); + } return clk->mstop; } } From patchwork Wed Dec 18 14:20:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13913760 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 749F01B0417; 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Wed, 18 Dec 2024 06:20:53 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:9516:68be:c7cd:69f2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c801ac68sm14107033f8f.51.2024.12.18.06.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 06:20:52 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/5] clk: renesas: rzv2h: Relocate MSTOP-related macros to the family driver Date: Wed, 18 Dec 2024 14:20:42 +0000 Message-ID: <20241218142045.77269-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The `CPG_BUS_1_MSTOP` and `CPG_BUS_MSTOP` macros are exclusively used by the RZ/V2H(P) CPG family driver and are not required in the SoC-specific clock driver. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 3 +++ drivers/clk/renesas/rzv2h-cpg.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 23c89b0de38a..38edddfc42d9 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -41,6 +41,9 @@ #define GET_RST_OFFSET(x) (0x900 + ((x) * 4)) #define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4)) +#define CPG_BUS_1_MSTOP (0xd00) +#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4) + #define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val))) #define MDIV(val) FIELD_GET(GENMASK(15, 6), (val)) #define PDIV(val) FIELD_GET(GENMASK(5, 0), (val)) diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 9be5a312fa96..810275eba473 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -35,7 +35,6 @@ struct ddiv { #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) -#define CPG_BUS_1_MSTOP (0xd00) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) @@ -47,8 +46,6 @@ struct ddiv { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) -#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4) - #define BUS_MSTOP(idx, mask) (((idx) & 0xffff) << 16 | (mask)) #define BUS_MSTOP_NONE GENMASK(31, 0) From patchwork Wed Dec 18 14:20:43 2024 Content-Type: text/plain; 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Wed, 18 Dec 2024 06:20:53 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/5] clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction Date: Wed, 18 Dec 2024 14:20:43 +0000 Message-ID: <20241218142045.77269-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Replace manual bit manipulation in `BUS_MSTOP` with `FIELD_PREP_CONST` and `FIELD_GET` macros for better clarity and maintainability. Introduce explicit masks (`BUS_MSTOP_IDX_MASK`, `BUS_MSTOP_BITS_MASK`) to improve readability. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 4 ++-- drivers/clk/renesas/rzv2h-cpg.h | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 38edddfc42d9..29b1ce003370 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -582,8 +582,8 @@ static struct rzv2h_mstop if (!mstop) return NULL; - mstop->idx = (mstop_data >> 16) & 0xffff; - mstop->mask = mstop_data & 0xffff; + mstop->idx = FIELD_GET(BUS_MSTOP_IDX_MASK, (mstop_data)); + mstop->mask = FIELD_GET(BUS_MSTOP_BITS_MASK, (mstop_data)); if (rzv2h_mod_clock_is_enabled(&clock->hw)) refcount_set(&mstop->ref_cnt, 1); else diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 810275eba473..f918620c4650 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -46,7 +46,10 @@ struct ddiv { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) -#define BUS_MSTOP(idx, mask) (((idx) & 0xffff) << 16 | (mask)) +#define BUS_MSTOP_IDX_MASK GENMASK(31, 16) +#define BUS_MSTOP_BITS_MASK GENMASK(15, 0) +#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ + FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask))) #define BUS_MSTOP_NONE GENMASK(31, 0) /** From patchwork Wed Dec 18 14:20:44 2024 Content-Type: text/plain; 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Wed, 18 Dec 2024 06:20:55 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/5] clk: renesas: r9a09g057: Add reset entry for SYS Date: Wed, 18 Dec 2024 14:20:44 +0000 Message-ID: <20241218142045.77269-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add the missing reset entry for the `SYS` module in the clock driver. The corresponding core clock entry for `SYS` is already present. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/r9a09g057-cpg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 59dadedb2217..856a02ac7ac5 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -220,6 +220,7 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { }; static const struct rzv2h_reset r9a09g057_resets[] __initconst = { + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ From patchwork Wed Dec 18 14:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13913763 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8534E1C5CDA; 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Wed, 18 Dec 2024 06:20:57 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:9516:68be:c7cd:69f2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c801ac68sm14107033f8f.51.2024.12.18.06.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 06:20:56 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 5/5] clk: renesas: r9a09g057: Add clock and reset entries for GIC Date: Wed, 18 Dec 2024 14:20:45 +0000 Message-ID: <20241218142045.77269-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241218142045.77269-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add clock and reset entries for GIC. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/r9a09g057-cpg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 856a02ac7ac5..947efb1a5914 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -117,6 +117,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, BUS_MSTOP_NONE), + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, + BUS_MSTOP(3, BIT(5))), DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, BUS_MSTOP(5, BIT(10))), DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, @@ -222,6 +224,8 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */