From patchwork Wed Dec 18 15:27:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 13913873 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB55A1BEF88 for ; Wed, 18 Dec 2024 15:36:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734536211; cv=none; b=CQIgP9rTgWGhoSzHzYbiggXMalFqU2mzGGYfrMEKj3vF5Fff+TL96PB0MX59xK6ZKAqXgRTOwvtd9EOMgfULOLj7+keEhzcrliZTRf7L2q7RBKSvhdPrb6GPRwsy3Gvn41fERed3Ddvkt5SL2/QFf8KL4uvI1TWvl1LoJ+SfRfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734536211; c=relaxed/simple; bh=tGc9xVwfmgpgk71ZWecJKg+KkXdqZ2zUCeIsc1Nr4a8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tAlX7xrrq348TXycxM7n/XwLvww55L+jGuRlt+cPrzswOCl1fKnQQmUQzgOQ5bFXo2tVJyHI8eSyGJY4LoX7BDpbUxiwC+ZNpTARGT2XyUUsFY3xzcqO4KWO1RkWcHRD3sFDRXDoA96uHaxq7PtoV6hwaw54MfPkvyjo+YSNdnc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=pass smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=zTTNS0Ek; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="zTTNS0Ek" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D80F0BFB70; Wed, 18 Dec 2024 16:29:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1734535786; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=A+MEtWqv+jtuMkcOt3EU3LJknR9R8KvXbro2h2nqPjw=; b=zTTNS0Ekiu3XFX9gHx6F0jaivYzGs4wdcpgnCHwLtjWnAeINTdfGHJccOgQiDD1PGJem0R fzpbonJQFl94z6tF6/owTw/85uW3gRHHPN+VBNYM0+M0B2s3IqvrZHLJ8+ISIwbOMh00mv k1KTIKGV+e/xC0sp2q2EUIemqAWmej2woXCVxC3e3Kmp6S/8YJwgBjDiMNbQzpjlPzE0pz aQD8o5Pe0a5Z7jjbB/1EGSV6uZCzb2fNqfr15CuMLet8N8gAQWoNBl8vrxqraM2jl9Lo88 /NGmGne1M+DSYtZx91mUnc+5W4Q8CNXzdPCWozo1r1gyiRlI8pcJqQt5LoCAiw== From: Frieder Schrempf To: linux-arm-kernel@lists.infradead.org, Marek Vasut , Conor Dooley , Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [PATCH v3 2/9] arm64: dts: imx8mp-skov-reva: Use hardware signal for SD card VSELECT Date: Wed, 18 Dec 2024 16:27:25 +0100 Message-ID: <20241218152842.97483-3-frieder@fris.de> In-Reply-To: <20241218152842.97483-1-frieder@fris.de> References: <20241218152842.97483-1-frieder@fris.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf The USDHC controller is able to control the IO voltage of the SD card. There is no reason to use a GPIO to control it. Signed-off-by: Frieder Schrempf --- Changes for v3: * Rebase to next-20241218 Changes for v2: * new patch --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index 59813ef8e2bb3..33031e946329d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -232,7 +232,6 @@ pmic@25 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; regulators { reg_vdd_soc: BUCK1 { @@ -555,7 +554,6 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 >; }; @@ -623,6 +621,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -634,6 +633,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -645,6 +645,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; From patchwork Wed Dec 18 15:27:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 13913865 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A71DE1F37D8 for ; Wed, 18 Dec 2024 15:30:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="0rUi7MJc" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 95AC3BFB88; Wed, 18 Dec 2024 16:29:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1734535799; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=wfB/TCZTripQjH6hLxg9WpKQmWcxnwexAWuVAFpfJ2o=; b=0rUi7MJcJDi1Eu2sqR834LN6dsxJ0Y+1qRM4wHJlZz+SOkl5n8riq56UcMNjrKHx6XaACh XR/vM0M0ENp0QCj3azfIG0VkHOsYNwY+O53c/Bi+xo1R3/1vegiJ08wDQxJXhmCJAbDE1V 5vPZxtv/dTX7hahx2f7XAkP37ECRtM2/uOqoewhA/xIz1IfvJ6yfH+APshydh18CHIp6IX YUksesdWmF9KI9CEZQixAMPHmkBy8hvwqCx5S5+WpXf1n20pBtISLXbQR9CIXtmpm51ie/ mbVyheV8rleluz0KuayaeZ5e19rWAKX3/s7t2SSsBBQfWwRaMOe2rcSlN/SMfA== From: Frieder Schrempf To: linux-arm-kernel@lists.infradead.org, Marek Vasut , Conor Dooley , Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [PATCH v3 7/9] arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal Date: Wed, 18 Dec 2024 16:27:30 +0100 Message-ID: <20241218152842.97483-8-frieder@fris.de> In-Reply-To: <20241218152842.97483-1-frieder@fris.de> References: <20241218152842.97483-1-frieder@fris.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf This fixes the LDO5 regulator handling of the pca9450 driver by taking the status of the SD_VSEL into account to determine which configuration register is used for the voltage setting. Even without this change there is no functional issue, as the code for switching the voltage in sdhci.c currently switches both, the VSELECT/SD_VSEL signal and the regulator voltage at the same time and doesn't run into an invalid corner case. We should still make sure, that we always use the correct register when controlling the regulator. At least in U-Boot this fixes an actual bug where the wrong IO voltage is used and it makes sure that the correct voltage can be read from sysfs. Signed-off-by: Frieder Schrempf --- Changes for v3: * Rebase to next-20241218 Changes for v2: * rebase to current master --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 10 +++++++--- .../arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 7 ++++--- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index a8ef4fba16a9e..d16490d876874 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -254,6 +254,10 @@ &pwm2 { status = "okay"; }; +®_nvcc_sd { + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -454,7 +458,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -467,7 +471,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -480,7 +484,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 663ae52b48526..d455429652305 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -342,6 +342,7 @@ reg_nvcc_sd: LDO5 { regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -794,7 +795,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -807,7 +808,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -820,7 +821,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; From patchwork Wed Dec 18 15:27:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 13913866 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F751C2304 for ; Wed, 18 Dec 2024 15:30:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734535808; cv=none; b=KW6RmT87xugzC71XC2/fO6ytsPaQ95n6ak4G7tF97kmuu0Dq5m1q40ieYt9dRLcipDzGq1t40Nt7enWOcp9G/IgSKV4HR6s7Q6ZKO0D0F7Ug/eeEBeOJl4wXGFdc3T5b2fwduQzk6ol1HydpCiVJvzrzRIUmgPitlOQXcTGLV2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734535808; c=relaxed/simple; bh=Dko0j7BjXx0wHz7qAsWEDtK9wLzepysGeLzxwxNOhSA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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bh=MglykLElRkkNwHFoO+5brxcsZetAnMpPwRMk/KFCtsI=; b=nXNhE4Jme2kQOwKw3mZQU4UntRyuOOlV9OxAdxKtLX2yhxLnR8hljlcfsjv1u3j3uykP04 VBQNfHl0seNBssUinoK4a809T/2/b6E4VO5VeoXmaFSUB2pNt2Bnegbv4TQwDR03sDAVcV BQgZXvQdTeBvLyxBoCOw7nHqHIUz0gjEjqkJkGnuvSTeUNCIi8/DJMSV2UuvuYVcitLbXH w+uNYJCE+wckImIbYTqfxMzMrpVhzl8L1lGwQd4aBr3GKVZylonzpBMFzCZmM82yTUxcVQ ZgyxTUNVat3bvJXx/GxJDLHb0ASchufv7GeGFYVXgYWRgpDj5UAmW0HwtUDqwQ== From: Frieder Schrempf To: linux-arm-kernel@lists.infradead.org, Marek Vasut , Conor Dooley , Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [PATCH v3 8/9] arm64: dts: imx93-kontron: Fix SD card IO voltage control Date: Wed, 18 Dec 2024 16:27:31 +0100 Message-ID: <20241218152842.97483-9-frieder@fris.de> In-Reply-To: <20241218152842.97483-1-frieder@fris.de> References: <20241218152842.97483-1-frieder@fris.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf The OSM-S i.MX93 SoM doesn't have the VSELECT signal of the USDHC controller connected to the PMICs SD_VSEL input. Instead SD_VSEL is hardwired to low level. Let the driver know this in order to use the proper register for reading and writing the voltage level. This fixes SD card access with the latest hardware revision of the Kontron OSM-S i.MX93 SoM. Signed-off-by: Frieder Schrempf --- Changes for v3: * Rebase to next-20241218 Changes for v2: * new patch --- arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index 47c1363a2f99a..119a162070596 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -189,6 +189,7 @@ reg_nvcc_sd: LDO5 { regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + nxp,sd-vsel-fixed-low; }; }; }; @@ -282,6 +283,7 @@ &usdhc2 { /* OSM-S SDIO_A */ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; }; @@ -553,7 +555,6 @@ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 /* SDIO_A_D0 */ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -565,7 +566,6 @@ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e /* SDIO_A_D0 */ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -577,7 +577,6 @@ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe /* SDIO_A_D0 */ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; From patchwork Wed Dec 18 15:27:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 13913867 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F431E9B37 for ; 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arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="L20Isi2D" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 412FBBFB05; Wed, 18 Dec 2024 16:30:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1734535810; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=JgASWdXNS3RqXVlA/ImzhuUR23AWDdoHokCYtEmwqDo=; b=L20Isi2DAUo2qXpjkQIriyp7PxpAWdBObbWKlkfL2ZxkAYpaonmHa/wS1oVceOXLNgijSj eunGPCDTQlNVAzlgfuQbUXxJNYH3jIpj5bNaMjogZ8FvUTWSrTaHcMbN+71Qa8LuBOk21j ITYm+eh8UPy81F0ZtjcUW5ZyKLOwKSj9lzjzqCkIBDReC1iAfzWY9C0uUFdhucx7gdh13r g0qXlQgI2OmwmL2kWGj3xYax6Po1ZgxvpAAp2GHOvFwe8Swgq7nTZ2VdcQrm2ycCkYiUk4 r+XLne08y0F4+uveZQO6XVjNWZ7yyVVC2iBTIVqkFH4h6KjmCeWUZg3iJBNJfg== From: Frieder Schrempf To: linux-arm-kernel@lists.infradead.org, Marek Vasut , Conor Dooley , Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [PATCH v3 9/9] arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal Date: Wed, 18 Dec 2024 16:27:32 +0100 Message-ID: <20241218152842.97483-10-frieder@fris.de> In-Reply-To: <20241218152842.97483-1-frieder@fris.de> References: <20241218152842.97483-1-frieder@fris.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf This fixes the LDO5 regulator handling of the pca9450 driver by taking the status of the SD_VSEL into account to determine which configuration register is used for the voltage setting. Even without this change there is no functional issue, as the code for switching the voltage in sdhci.c currently switches both, the VSELECT/SD_VSEL signal and the regulator voltage at the same time and doesn't run into an invalid corner case. We should still make sure, that we always use the correct register when controlling the regulator. At least in U-Boot this fixes an actual bug where the wrong IO voltage is used and it makes sure that the correct voltage can be read from sysfs. Signed-off-by: Frieder Schrempf --- Changes for v3: * Rebase to next-20241218 Changes for v2: * new patch --- arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi index e0e9f6f7616d9..b97bfeb1c30f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi @@ -311,6 +311,7 @@ reg_nvcc_sd: LDO5 { regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -808,7 +809,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -820,7 +821,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -832,7 +833,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; };