From patchwork Thu Dec 19 11:01:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2B5CE7718A for ; Thu, 19 Dec 2024 11:18:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVj-0004Y2-KT; Thu, 19 Dec 2024 06:16:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVb-0004Vz-Ud for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:00 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVY-0005HS-P7 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:15:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606957; x=1766142957; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DxXDnN+O/WwzGOcacl7nzyyO6E4y6vh1Z1+71dP+W94=; b=cJ6jG4M+HxGdgcQGCXzKebyHizokYHvXr19ThhQOf2bBbasCfkOdVRSa VBR5XC92MtmjN4y/1QGsOzXAiwfHhh4r/6TzI+XCBY1EktVXAF4fuHgP1 +8sUpqO+RFDYX/sejefN9AcsgjfFbWgPNnymyX85QRxycU4l9X1y8PpKr KroMB8drthlggd0urBc1ocUj+cWpJxPTi6yN62/TNdsRDM7CtTXIkgLhr 3QHQddrnJtan7A5B32FTNbq6qA49DH17xszZ1JOiUPsNBFuoACODMmQXt 4SXIJKwmZC0WZBR03qG/KQ8PmUkYe0OSCe2eZVg3cx6QY4Bbe5M2sCvOr w==; X-CSE-ConnectionGUID: HH80fenOSdmlrChVBDKMiQ== X-CSE-MsgGUID: amVDAtymSDudAZQ0mdHkoA== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994924" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994924" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:15:54 -0800 X-CSE-ConnectionGUID: 3ZhCPKwkQLubGHKE5dqV7g== X-CSE-MsgGUID: GBEQRhl2RGWufLAoiN2N7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956108" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:15:50 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 01/10] i386/cpu: Extract a common fucntion to setup value of MSR_CORE_THREAD_COUNT Date: Thu, 19 Dec 2024 06:01:16 -0500 Message-Id: <20241219110125.1266461-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There are duplicated code to setup the value of MSR_CORE_THREAD_COUNT. Extract a common function for it. Signed-off-by: Xiaoyao Li --- Changes in v2: - move the implementation of cpu_x86_get_msr_core_thread_count() to target/i386/cpu-sysemu.c; --- target/i386/cpu-sysemu.c | 11 +++++++++++ target/i386/cpu.h | 2 ++ target/i386/hvf/x86_emu.c | 3 +-- target/i386/kvm/kvm.c | 5 +---- target/i386/tcg/sysemu/misc_helper.c | 3 +-- 5 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 227ac021f62f..4e9df0bc0156 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -309,3 +309,14 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, errp); qapi_free_GuestPanicInformation(panic_info); } + +uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu) +{ + CPUState *cs = CPU(cpu); + uint64_t val; + + val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + + return val; +} diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4c239a6970fd..5e1beca94a62 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2390,6 +2390,8 @@ static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, cs->halted = 0; } +uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu); + int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, target_ulong *base, unsigned int *limit, unsigned int *flags); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 015f760acb39..69c61c9c0737 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -765,8 +765,7 @@ void simulate_rdmsr(CPUX86State *env) val = env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + val = cpu_x86_get_msr_core_thread_count(cpu); break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8e17942c3ba1..18a1bd1297a4 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2602,10 +2602,7 @@ static bool kvm_rdmsr_core_thread_count(X86CPU *cpu, uint32_t msr, uint64_t *val) { - CPUState *cs = CPU(cpu); - - *val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - *val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + *val = cpu_x86_get_msr_core_thread_count(cpu); return true; } diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 094aa56a20d1..ff7b201b44d8 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -468,8 +468,7 @@ void helper_rdmsr(CPUX86State *env) val = x86_cpu->ucode_rev; break; case MSR_CORE_THREAD_COUNT: { - CPUState *cs = CPU(x86_cpu); - val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); + val = cpu_x86_get_msr_core_thread_count(x86_cpu); break; } case MSR_APIC_START ... MSR_APIC_END: { From patchwork Thu Dec 19 11:01:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB206E77184 for ; Thu, 19 Dec 2024 11:18:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVo-0004a1-8c; Thu, 19 Dec 2024 06:16:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVb-0004Vy-UV for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:00 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVZ-0005Hq-O1 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:15:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606958; x=1766142958; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hGrOY+aNrIOBOmNFWeGMrcHfpcpocdtMH4I0QQYaVbU=; b=gv1BFoMFLXIO0vp2k9mtC5B/8EKzi2Rm1pzaWmL+ZW17P6FVZOhHDXuw yk/s7WcayS34/L0AWLwSX2Fsx7Ln5BVPyOlHN6E0Nc4Kim4u+aa5frBz1 Rjnocf4XObyY77UvnesdkqIjZnV9LiUkdMEBAgVmceFQbmQYeuVPHu4IN ETpP6JfuYm8Ix8MvW7creQhYv2z17Azodvp/HXrKT7HVq740JBpepBVM4 vhiUkGp0qW0fiAyz19qDqiBpbgezDwB2nktgRA8rx3H/2IGd86FkRWcI1 UwjcAufHU9JPJb/BJsRZ3GBM3Cf4VTUKNK5PmvF1xeJNsFt3NyVAJiPls g==; X-CSE-ConnectionGUID: j1Z6gqtaQKO1A4uBRcD5uQ== X-CSE-MsgGUID: brA0zVM6Q5iyt/kXFRtkEA== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994936" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994936" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:15:57 -0800 X-CSE-ConnectionGUID: 5rMX38JKSW25WC+VA1ccpg== X-CSE-MsgGUID: 8lFa2maCSp+EKjOnCa9BEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956125" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:15:53 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 02/10] i386/cpu: Drop the variable smp_cores and smp_threads in x86_cpu_pre_plug() Date: Thu, 19 Dec 2024 06:01:17 -0500 Message-Id: <20241219110125.1266461-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org No need to define smp_cores and smp_threads, just using ms->smp.cores and ms->smp.threads is straightforward. It's also consistent with other checks of socket/die/module. Signed-off-by: Xiaoyao Li --- hw/i386/x86-common.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 3f7818269234..32a8d7a9db87 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -248,8 +248,6 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, CPUX86State *env = &cpu->env; MachineState *ms = MACHINE(hotplug_dev); X86MachineState *x86ms = X86_MACHINE(hotplug_dev); - unsigned int smp_cores = ms->smp.cores; - unsigned int smp_threads = ms->smp.threads; X86CPUTopoInfo topo_info; if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { @@ -329,17 +327,17 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); return; - } else if (cpu->core_id > (smp_cores - 1)) { + } else if (cpu->core_id > (ms->smp.cores - 1)) { error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", - cpu->core_id, smp_cores - 1); + cpu->core_id, ms->smp.cores - 1); return; } if (cpu->thread_id < 0) { error_setg(errp, "CPU thread-id is not set"); return; - } else if (cpu->thread_id > (smp_threads - 1)) { + } else if (cpu->thread_id > (ms->smp.threads - 1)) { error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", - cpu->thread_id, smp_threads - 1); + cpu->thread_id, ms->smp.threads - 1); return; } From patchwork Thu Dec 19 11:01:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55A43E77184 for ; Thu, 19 Dec 2024 11:18:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVl-0004YN-QH; Thu, 19 Dec 2024 06:16:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVd-0004WT-KS for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:02 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVb-0005H9-SA for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606960; x=1766142960; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6HpxBDbI/9GKhzbGJA3ef0PtUFQ2lSE7HfhNWpqrw2g=; b=UrxFuh/CYrEv/i9CZh1r9ygLdZUXnLcJgeL5M4oFhIU7h9X/jy/GEs5t l+o+2SbNSpyO2PDViFMMpLggp+4Xgg34eXI4WIIPXO7D65Jq+JncyjibV uu/0/Pcf+RbAALGua7pAV8eACkW0F8YaiZBfz1fOFBnu25Y0izmb6ZAU6 ENa1AVa+vd6uNAR3dOWzTwFWuIAjcR11rV+af+1XELE5/6ns7i/WrmGb7 1bEFa+/C0qzQq6eHYWomULH7NYESBgUA87eICatW6mAGMs7s5s7K7p9jO R94OhLJCKuvMB1Z7UARZp4FOT4a4J+c+9cjCqUA794SCztzrWH+9rAQ2i A==; X-CSE-ConnectionGUID: W7yG2nrPS6aqpr1QI+xGWw== X-CSE-MsgGUID: cFUZWSXzQVKPaMO8Y0zghg== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994942" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994942" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:00 -0800 X-CSE-ConnectionGUID: klXGd20tTbe5rItSGbY+Jw== X-CSE-MsgGUID: limWjYT1SPGUx1IbFuSEQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956148" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:15:56 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 03/10] i386/cpu: Drop cores_per_pkg in cpu_x86_cpuid() Date: Thu, 19 Dec 2024 06:01:18 -0500 Message-Id: <20241219110125.1266461-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Local variable cores_per_pkg is only used to calculate threads_per_pkg. No need for it. Drop it and open-code it instead. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 525339945920..ad6889abdf5e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6498,7 +6498,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; - uint32_t cores_per_pkg; uint32_t threads_per_pkg; topo_info.dies_per_pkg = env->nr_dies; @@ -6506,9 +6505,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; topo_info.threads_per_core = cs->nr_threads; - cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * - topo_info.dies_per_pkg; - threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; + threads_per_pkg = topo_info.threads_per_core * topo_info.cores_per_module * + topo_info.modules_per_die * topo_info.dies_per_pkg; /* Calculate & apply limits for different index ranges */ if (index >= 0xC0000000) { From patchwork Thu Dec 19 11:01:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1AE9AE7718B for ; Thu, 19 Dec 2024 11:16:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVl-0004YP-Qo; Thu, 19 Dec 2024 06:16:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVg-0004Wl-9G for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:05 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVe-0005H9-Kv for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606963; x=1766142963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=svD0Sz+s3Tirwo4k9cnsmvSDpD6Ex6DEuucB26NUaZ0=; b=arjpRb5Jx7ayt7p9uWKIHXOXyeJ8tfS+N64t/YhCDFVIUu1Fv+lYGrIE /7a5g/NOmwbPpxQ3604Wlj/7LD9IGW6wihTe7bdw3e44AiM+A07/LIVxd AR6HqcB9fVjGtGI1M1GBUE0MNGsgc636e5h7Hu8+M2Jr5BxQLzzbBCZAL iB59JmBQuAKNokxpTFncNjJa2fg2JGj4A4yDWSz1DJqj82yL9+6ekmgO5 JcFurlyCZnuqk24JcMGkLLrsfcnDZkaeJTiTmD0H/lLiI4nwRM71an7ll xWiC62mWjL8Q1CWNdDmmZ9BL5TKuWfk5NslT1/N+PF6omcFU5yFbb8iSz w==; X-CSE-ConnectionGUID: FHT1RwKOReSmGVsqqLY11g== X-CSE-MsgGUID: iYvxkXv7TJGhH7ACG6sUFA== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994951" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994951" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:03 -0800 X-CSE-ConnectionGUID: kIeCHDmXTQi5ge7VRhTtmQ== X-CSE-MsgGUID: 0Rk3RJytTbu9GxgqpAfPnw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956156" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:15:59 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 04/10] i386/topology: Update the comment of x86_apicid_from_topo_ids() Date: Thu, 19 Dec 2024 06:01:19 -0500 Message-Id: <20241219110125.1266461-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Update the comment of x86_apicid_from_topo_ids() to match the current implementation, Signed-off-by: Xiaoyao Li Reviewed-by: Zhao Liu --- include/hw/i386/topology.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index b2c8bf2de158..21b65219a5ca 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -121,9 +121,10 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) } /* - * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID + * Make APIC ID for the CPU based on topology and IDs of each topology level. * - * The caller must make sure core_id < nr_cores and smt_id < nr_threads. + * The caller must make sure the ID of each level doesn't exceed the width of + * the level. */ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) From patchwork Thu Dec 19 11:01:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 027CFE7718B for ; Thu, 19 Dec 2024 11:18:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVo-0004aC-RS; Thu, 19 Dec 2024 06:16:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVk-0004YO-Cf for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:08 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVh-0005H9-Gg for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606966; x=1766142966; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yyWt+MVGY6xtOd7DTZ9vugv8QqO6/xf7WS/1tfjrRyc=; b=TYwRVA1JKNK6mSMXoJVpz5mTI8qHNGlD3Mew76xTfRIev4QbEcfpo84Q EtxrqL7J66mzAO9q1oiMiPIAulAH3YLFwfhbxxyXrDhwINSFMQzSQ97A3 cn7zNR04VAasWT0Atay+fMk2ozrmP9m4nhuqt4eHWmFaiDWgcmw9Gec8U arTTYmjQbeoFPNsB97b+ga8XgNxOhxTMZmW8xZODdb1thDoDwTxFopGpb dVtlnpFJZ3/iHSyXrA9LE/Rxk/lVKeQs3tFvjPfbT8y3GmCHJQvI74W3P 12ehdh0vnnJV95HzwKkZ3drT1nd0zuIax90qdlZrgRVAzihA8i3uw55Iv A==; X-CSE-ConnectionGUID: a6GbkZT4RAiioLTft7pBig== X-CSE-MsgGUID: OHGwgQMoQjKkYfebTsZ4pw== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994959" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994959" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:05 -0800 X-CSE-ConnectionGUID: DmifpDBQRhqirTrWD1H3cA== X-CSE-MsgGUID: fg6EgXzbSjacaI+dUdo4HA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956164" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:16:02 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 05/10] i386/topology: Introduce helpers for various topology info of different level Date: Thu, 19 Dec 2024 06:01:20 -0500 Message-Id: <20241219110125.1266461-6-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce various helpers for getting the topology info of different semantics. Using the helper is more self-explanatory. Besides, the semantic of the helper will stay unchanged even when new topology is added in the future. At that time, updating the implementation of the helper without affecting the callers. Signed-off-by: Xiaoyao Li --- include/hw/i386/topology.h | 25 +++++++++++++++++++++++++ target/i386/cpu.c | 11 ++++------- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 21b65219a5ca..f6380f1ed756 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -203,4 +203,29 @@ static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap); } +static inline unsigned x86_module_per_pkg(X86CPUTopoInfo *topo_info) +{ + return topo_info->modules_per_die * topo_info->dies_per_pkg; +} + +static inline unsigned x86_cores_per_pkg(X86CPUTopoInfo *topo_info) +{ + return topo_info->cores_per_module * x86_module_per_pkg(topo_info); +} + +static inline unsigned x86_threads_per_pkg(X86CPUTopoInfo *topo_info) +{ + return topo_info->threads_per_core * x86_cores_per_pkg(topo_info); +} + +static inline unsigned x86_threads_per_module(X86CPUTopoInfo *topo_info) +{ + return topo_info->threads_per_core * topo_info->cores_per_module; +} + +static inline unsigned x86_threads_per_die(X86CPUTopoInfo *topo_info) +{ + return x86_threads_per_module(topo_info) * topo_info->modules_per_die; +} + #endif /* HW_I386_TOPOLOGY_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ad6889abdf5e..f11b5d401a77 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -311,13 +311,11 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, case CPU_TOPOLOGY_LEVEL_CORE: return topo_info->threads_per_core; case CPU_TOPOLOGY_LEVEL_MODULE: - return topo_info->threads_per_core * topo_info->cores_per_module; + return x86_threads_per_module(topo_info); case CPU_TOPOLOGY_LEVEL_DIE: - return topo_info->threads_per_core * topo_info->cores_per_module * - topo_info->modules_per_die; + return x86_threads_per_die(topo_info); case CPU_TOPOLOGY_LEVEL_SOCKET: - return topo_info->threads_per_core * topo_info->cores_per_module * - topo_info->modules_per_die * topo_info->dies_per_pkg; + return x86_threads_per_pkg(topo_info); default: g_assert_not_reached(); } @@ -6505,8 +6503,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; topo_info.threads_per_core = cs->nr_threads; - threads_per_pkg = topo_info.threads_per_core * topo_info.cores_per_module * - topo_info.modules_per_die * topo_info.dies_per_pkg; + threads_per_pkg = x86_threads_per_pkg(&topo_info); /* Calculate & apply limits for different index ranges */ if (index >= 0xC0000000) { From patchwork Thu Dec 19 11:01:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07F78E7718B for ; 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X-CSE-ConnectionGUID: MACcXBliQvCP+rtfrRCPPg== X-CSE-MsgGUID: EQXJykWSQwmUIGRRzLE5JA== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994965" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994965" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:09 -0800 X-CSE-ConnectionGUID: f7EkjQ3NSrSqlly8mCt2yw== X-CSE-MsgGUID: HgPUkl7/QqOp3t6AFBLTNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956171" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:16:05 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 06/10] i386/cpu: Track a X86CPUTopoInfo directly in CPUX86State Date: Thu, 19 Dec 2024 06:01:21 -0500 Message-Id: <20241219110125.1266461-7-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The name of nr_modules/nr_dies are ambiguous and they mislead people. The purpose of them is to record and form the topology information. So just maintain a X86CPUTopoInfo member in CPUX86State instead. Then nr_modules and nr_dies can be dropped. As the benefit, x86 can switch to use information in CPUX86State::topo_info and get rid of the nr_cores and nr_threads in CPUState. This helps remove the dependency on qemu_init_vcpu() so that x86 can get and use topology info earlier in x86_cpu_realizefn(). Signed-off-by: Xiaoyao Li --- hw/i386/x86-common.c | 12 ++++------ target/i386/cpu-sysemu.c | 6 ++--- target/i386/cpu.c | 51 ++++++++++++++++------------------------ target/i386/cpu.h | 6 +---- 4 files changed, 29 insertions(+), 46 deletions(-) diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 32a8d7a9db87..26c3e3169cd4 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -248,7 +248,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, CPUX86State *env = &cpu->env; MachineState *ms = MACHINE(hotplug_dev); X86MachineState *x86ms = X86_MACHINE(hotplug_dev); - X86CPUTopoInfo topo_info; + X86CPUTopoInfo *topo_info = &env->topo_info; if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", @@ -267,15 +267,13 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, } } - init_topo_info(&topo_info, x86ms); + init_topo_info(topo_info, x86ms); if (ms->smp.modules > 1) { - env->nr_modules = ms->smp.modules; set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo); } if (ms->smp.dies > 1) { - env->nr_dies = ms->smp.dies; set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo); } @@ -346,12 +344,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.module_id = cpu->module_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id = x86_apicid_from_topo_ids(topo_info, &topo_ids); } cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); if (!cpu_slot) { - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, module: %u, core: %u, thread: %u]" @@ -374,7 +372,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 4e9df0bc0156..31b37c63252c 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -312,11 +312,11 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu) { - CPUState *cs = CPU(cpu); + CPUX86State *env = &cpu->env; uint64_t val; - val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + val = x86_threads_per_pkg(&env->topo_info); /* thread count, bits 15..0 */ + val |= x86_cores_per_pkg(&env->topo_info) << 16; /* core count, bits 31..16 */ return val; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f11b5d401a77..d41768648ab9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6495,15 +6495,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, CPUState *cs = env_cpu(env); uint32_t limit; uint32_t signature[3]; - X86CPUTopoInfo topo_info; + X86CPUTopoInfo *topo_info = &env->topo_info; uint32_t threads_per_pkg; - topo_info.dies_per_pkg = env->nr_dies; - topo_info.modules_per_die = env->nr_modules; - topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; - topo_info.threads_per_core = cs->nr_threads; - - threads_per_pkg = x86_threads_per_pkg(&topo_info); + threads_per_pkg = x86_threads_per_pkg(topo_info); /* Calculate & apply limits for different index ranges */ if (index >= 0xC0000000) { @@ -6580,12 +6575,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); *eax &= ~0xFC000000; - *eax |= max_core_ids_in_package(&topo_info) << 26; + *eax |= max_core_ids_in_package(topo_info) << 26; if (host_vcpus_per_cache > threads_per_pkg) { *eax &= ~0x3FFC000; /* Share the cache at package level. */ - *eax |= max_thread_ids_for_cache(&topo_info, + *eax |= max_thread_ids_for_cache(topo_info, CPU_TOPOLOGY_LEVEL_SOCKET) << 14; } } @@ -6597,7 +6592,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - &topo_info, + topo_info, eax, ebx, ecx, edx); if (!cpu->l1_cache_per_core) { *eax &= ~MAKE_64BIT_MASK(14, 12); @@ -6605,7 +6600,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 1: /* L1 icache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - &topo_info, + topo_info, eax, ebx, ecx, edx); if (!cpu->l1_cache_per_core) { *eax &= ~MAKE_64BIT_MASK(14, 12); @@ -6613,13 +6608,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 2: /* L2 cache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - &topo_info, + topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - &topo_info, + topo_info, eax, ebx, ecx, edx); break; } @@ -6702,12 +6697,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: - *eax = apicid_core_offset(&topo_info); - *ebx = topo_info.threads_per_core; + *eax = apicid_core_offset(topo_info); + *ebx = topo_info->threads_per_core; *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; break; case 1: - *eax = apicid_pkg_offset(&topo_info); + *eax = apicid_pkg_offset(topo_info); *ebx = threads_per_pkg; *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; break; @@ -6733,7 +6728,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; } - encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); + encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); break; case 0xD: { /* Processor Extended State */ @@ -7036,7 +7031,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, * thread ID within a package". * Bits 7:0 is "The number of threads in the package is NC+1" */ - *ecx = (apicid_pkg_offset(&topo_info) << 12) | + *ecx = (apicid_pkg_offset(topo_info) << 12) | (threads_per_pkg - 1); } else { *ecx = 0; @@ -7065,19 +7060,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, - &topo_info, eax, ebx, ecx, edx); + topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, - &topo_info, eax, ebx, ecx, edx); + topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, - &topo_info, eax, ebx, ecx, edx); + topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, - &topo_info, eax, ebx, ecx, edx); + topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ *eax = *ebx = *ecx = *edx = 0; @@ -7089,7 +7084,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001E: if (cpu->core_id <= 255) { - encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); + encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); } else { *eax = 0; *ebx = 0; @@ -7994,17 +7989,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX * based on inputs (sockets,cores,threads), it is still better to give * users a warning. - * - * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise - * cs->nr_threads hasn't be populated yet and the checking is incorrect. */ if (IS_AMD_CPU(env) && !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && - cs->nr_threads > 1) { + env->topo_info.threads_per_core > 1) { warn_report_once("This family of AMD CPU doesn't support " "hyperthreading(%d). Please configure -smp " "options properly or try enabling topoext " - "feature.", cs->nr_threads); + "feature.", env->topo_info.threads_per_core); } #ifndef CONFIG_USER_ONLY @@ -8165,9 +8157,6 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) { CPUX86State *env = &cpu->env; - env->nr_modules = 1; - env->nr_dies = 1; - /* thread, core and socket levels are set by default. */ set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5e1beca94a62..bcdebdf48f7c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2045,11 +2045,7 @@ typedef struct CPUArchState { TPRAccess tpr_access_type; - /* Number of dies within this CPU package. */ - unsigned nr_dies; - - /* Number of modules within one die. */ - unsigned nr_modules; + X86CPUTopoInfo topo_info; /* Bitmap of available CPU topology levels for this CPU. */ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX); From patchwork Thu Dec 19 11:01:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2ECB5E7718A for ; Thu, 19 Dec 2024 11:18:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVq-0004bV-GL; Thu, 19 Dec 2024 06:16:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVo-0004aG-V1 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:13 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVn-0005Jo-Ca for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606972; x=1766142972; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iXysrcQtxF3+DT6qASzZRMSb17Gh/uEz3CgCSTb5hj8=; b=YHRvakkyno+pr3dQ73ko6le6FYephJAV0Kw1Hqh11pbT36zDT1NTkJLM IPFxuO1fw/RHhbH53gpc8SdNO/AveWBDYeQTwXU5EH/+2X1oZurE5RX58 RXJQdGxF7ppAPXmGea7aHGEcuDkQn2AJSnLiJbJ2FXQqBa7ProfaQcqh8 ByiVVo8aM3ZG426ZW4TYalsfQaqAzO10up7dkHOz9osg8Wzqj0VNMhcVd ppx1nv7u3IIcTR5ZQHrwP0m75XfrAaiJ3uof2+1UouwcrZ6cVEwav3NTc 3RgVNu74OmldRYex5MOVAF4Aob2Sw2ikwdwb2ifQ3qelcv+THZ8f2UlS/ A==; X-CSE-ConnectionGUID: MyaX/2gQS/2yBXrl2rjewg== X-CSE-MsgGUID: bHfqIfKZQbGV/hMyLAnUcQ== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994971" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994971" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:11 -0800 X-CSE-ConnectionGUID: e5mPFWv7TCOYVV25bSbAjA== X-CSE-MsgGUID: mRrOHL98S2+G6UNLTtQTuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956174" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:16:08 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 07/10] i386/cpu: Hoist check of CPUID_EXT3_TOPOEXT against threads_per_core Date: Thu, 19 Dec 2024 06:01:22 -0500 Message-Id: <20241219110125.1266461-8-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now it changes to use env->topo_info.threads_per_core and doesn't depend on qemu_init_vcpu() anymore. Drop the comment of the order dependency on qemu_init_vcpu() and hoist code to put it together with other feature checking. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d41768648ab9..fd59da5d445d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7880,6 +7880,21 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) */ cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; + /* + * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU + * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX + * based on inputs (sockets,cores,threads), it is still better to give + * users a warning. + */ + if (IS_AMD_CPU(env) && + !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && + env->nr_threads > 1) { + warn_report_once("This family of AMD CPU doesn't support " + "hyperthreading(%d). Please configure -smp " + "options properly or try enabling topoext " + "feature.", env->nr_threads); + } + /* For 64bit systems think about the number of physical bits to present. * ideally this should be the same as the host; anything other than matching * the host can cause incorrect guest behaviour. @@ -7984,21 +7999,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) x86_cpu_gdb_init(cs); qemu_init_vcpu(cs); - /* - * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU - * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX - * based on inputs (sockets,cores,threads), it is still better to give - * users a warning. - */ - if (IS_AMD_CPU(env) && - !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && - env->topo_info.threads_per_core > 1) { - warn_report_once("This family of AMD CPU doesn't support " - "hyperthreading(%d). Please configure -smp " - "options properly or try enabling topoext " - "feature.", env->topo_info.threads_per_core); - } - #ifndef CONFIG_USER_ONLY x86_cpu_apic_realize(cpu, &local_err); if (local_err != NULL) { From patchwork Thu Dec 19 11:01:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50A55E77184 for ; Thu, 19 Dec 2024 11:17:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVt-0004cA-Pr; Thu, 19 Dec 2024 06:16:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVs-0004bt-3I for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:16 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVq-0005Kx-G0 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606975; x=1766142975; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bkOTh7sm1DEDqwgD7+5B/BRslnhPu8TCuJZZUpkjQy8=; b=lXQ+dP6NZrx1pYg6b138glPblELdwwChd1V1mJkLGMaFMdHkE2Fk4LLg C4wBKdMIuo8gse3tOYJd8kB0kz6fPETk1cCx0RBlzvp6RPOTeR7Y5tV6f NoFb1uCUXFqXwK1wGhvBoakmJv/js2LrxuMlWaaLcpbD5G5+uPrMDWmD2 gMIp8zbCdE6spEfs8vB3xTu68fGZ8We/TDery4Y4Nvp/UL1Nj9a6xFqW/ RMOkGJlaHIG/oQCkXAK1FzEMweZHA2Gsv0mdGIGhPhcLU46eSEdfANnbq GbOLmE6kIo3uHkE89SCE+piBVLT7InhJZbBycteS1n/DVOwcxWHlIn6hG w==; X-CSE-ConnectionGUID: qw0ivHvpRg6SjUSSSKhG8Q== X-CSE-MsgGUID: gdsjSQgSRumsz293etq9hQ== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994976" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994976" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:14 -0800 X-CSE-ConnectionGUID: mb9ALuozQ8eJr43EZAH5Jw== X-CSE-MsgGUID: 4o1dBuVZSgKccpVCfL7pDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956179" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:16:10 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 08/10] cpu: Remove nr_cores from struct CPUState Date: Thu, 19 Dec 2024 06:01:23 -0500 Message-Id: <20241219110125.1266461-9-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is no user of it now, remove it. Signed-off-by: Xiaoyao Li Reviewed-by: Zhao Liu --- hw/core/cpu-common.c | 1 - include/hw/core/cpu.h | 2 -- system/cpus.c | 1 - 3 files changed, 4 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 09c79035949b..77089d4ed304 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -243,7 +243,6 @@ static void cpu_common_initfn(Object *obj) cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ - cpu->nr_cores = 1; cpu->nr_threads = 1; cpu->cflags_next_tb = -1; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c3ca0babcb3f..fb397cdfc53d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -407,7 +407,6 @@ struct qemu_work_item; * Under TCG this value is propagated to @tcg_cflags. * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. - * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU core. * @thread: Host thread details, only live once @created is #true * @sem: WIN32 only semaphore used only for qtest @@ -466,7 +465,6 @@ struct CPUState { CPUClass *cc; /*< public >*/ - int nr_cores; int nr_threads; struct QemuThread *thread; diff --git a/system/cpus.c b/system/cpus.c index ba633c7688b2..3db4a7d0ab4a 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -681,7 +681,6 @@ void qemu_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); - cpu->nr_cores = machine_topo_get_cores_per_socket(ms); cpu->nr_threads = ms->smp.threads; cpu->stopped = true; cpu->random_seed = qemu_guest_random_seed_thread_part1(); From patchwork Thu Dec 19 11:01:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32980E77184 for ; Thu, 19 Dec 2024 11:16:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEVy-0004lC-6b; Thu, 19 Dec 2024 06:16:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVu-0004cD-4I for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:19 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVs-0005Kx-Di for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606977; x=1766142977; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MHgdNVgv8JU4EXomJN5hU+EHD1vfrDJJzg4gGCEl33Y=; b=CB5/rBGKLwHDOn+b9CWfz4Y8Y/EeCiWOb+bHbN+XsEIx15n4r4QjJV/E VWoBTS76/G5AW7G+EPEK2+eT6YFAhcQ9PywyWbs+5ki3h1a6rQS7wiql6 K51DwDT7ciSX3VGUjep9YD3vVT9uK41TJFcVir7Y42PoIRSUwBeQ/lv9d 816l2XwUbCvGtQ7HmHjiorAa9yWPj9mJixqTFXkrXYwmOspEdzAyIq12b uOiDMqXRYDmVtu+L1xnQOAyhnH/8jPpS1mSTEEFrLXaVLY3MbW6kB8KJw qDUOrUtfGssBTPSygRMfVdsQ/3jx7WD5l+gryzkArrJc6dP+NF4lId2Fu A==; X-CSE-ConnectionGUID: WWiYbFKKTGGYWoJu9vYWUA== X-CSE-MsgGUID: 1MW9reJDRV265Krrk8NEdw== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34994988" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34994988" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:16 -0800 X-CSE-ConnectionGUID: +MY+tXIkTxakM5AkCiefYg== X-CSE-MsgGUID: KvXn05KtSXe/drhSwlIZ9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956195" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:16:13 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 09/10] i386/cpu: Set up CPUID_HT in x86_cpu_expand_features() instead of cpu_x86_cpuid() Date: Thu, 19 Dec 2024 06:01:24 -0500 Message-Id: <20241219110125.1266461-10-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently CPUID_HT is evaluated in cpu_x86_cpuid() each time. It's not a correct usage of how feature bit is maintained and evaluated. The expected practice is that features are tracked in env->features[] and cpu_x86_cpuid() should be the consumer of env->features[]. Track CPUID_HT in env->features[FEAT_1_EDX] instead and evaluate it in cpu's realizefn(). Signed-off-by: Xiaoyao Li --- There is one issue[1] of CPUID_HT being user settable that when "-cpu xxx,-ht" with "-smp 2", HT flag is still exposed to guest. However, the issue is not irrelevant to this patch. If anyone has interest to reslove it please go ahead. [1] https://lore.kernel.org/qemu-devel/Z1FUDGnenETEFV6Z@intel.com/ --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fd59da5d445d..bee494bdd029 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6537,7 +6537,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = env->features[FEAT_1_EDX]; if (threads_per_pkg > 1) { *ebx |= threads_per_pkg << 16; - *edx |= CPUID_HT; } if (!cpu->enable_pmu) { *ecx &= ~CPUID_EXT_PDCM; @@ -7528,6 +7527,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) } } + if (x86_threads_per_pkg(&env->topo_info) > 1) { + env->features[FEAT_1_EDX] |= CPUID_HT; + } + for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { FeatureDep *d = &feature_dependencies[i]; if (!(env->features[d->from.index] & d->from.mask)) { From patchwork Thu Dec 19 11:01:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13914964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DE5EE77184 for ; Thu, 19 Dec 2024 11:18:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOEW0-0004of-VM; Thu, 19 Dec 2024 06:16:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVy-0004ly-AD for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:23 -0500 Received: from mgamail.intel.com ([198.175.65.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOEVv-0005Lm-TH for qemu-devel@nongnu.org; Thu, 19 Dec 2024 06:16:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734606980; x=1766142980; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3aacQW4Go5h00Zo2AHmCDChkTH3OubD3GyFn8d6eHoo=; b=kIUvQCHNW7aI0/UruYL4DXukO3jR7JKKvTw7bJmgLCbawFp1AZfchVgQ CYOuQga1+xnkmTRJDvV0hIRGibXmEJ3aZ1E/ghLb4l+3/Pr3BXFCNlvML exKnHQP7X9+SAho8vGx3gZ9zZpZTcPq2zV3Lu4ZvAiSEPT1r4Ftjh1DRF mOE+XNGkFl04Yun7tAj2kk1exCFvHHZrk8jEsL4dt95zFg6Zf8axxpL5J qIp980yj71kl0krdM2P3/L3sPwpVQHW2UFT4tvjknA2z7DP00pJ+xNaBx Jz+vR8mQqUfiOrgQYrDNR3s1GG357QGm8XWtiJ5YT4c9gpzF3NtH0w0iC Q==; X-CSE-ConnectionGUID: 6PewRgOaTbiy0K6LD5j11g== X-CSE-MsgGUID: k54lDruQR2m7+974RH1rjg== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34995001" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34995001" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 03:16:19 -0800 X-CSE-ConnectionGUID: wWQf+0NXSiadEMlzbe6Tmg== X-CSE-MsgGUID: d4h8tPa1Qh2o4FI+C5kYaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="97956217" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 19 Dec 2024 03:16:15 -0800 From: Xiaoyao Li To: Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= Cc: qemu-devel@nongnu.org, Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Marcelo Tosatti , xiaoyao.li@intel.com Subject: [PATCH v2 10/10] i386/cpu: Set and track CPUID_EXT3_CMP_LEG in env->features[FEAT_8000_0001_ECX] Date: Thu, 19 Dec 2024 06:01:25 -0500 Message-Id: <20241219110125.1266461-11-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219110125.1266461-1-xiaoyao.li@intel.com> References: <20241219110125.1266461-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.19; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The correct usage is tracking and maintaining features in env->features[] instead of manually set it in cpu_x86_cpuid(). Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bee494bdd029..8d3744aa6d26 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6952,17 +6952,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx = env->features[FEAT_8000_0001_ECX]; *edx = env->features[FEAT_8000_0001_EDX]; - /* The Linux kernel checks for the CMPLegacy bit and - * discards multiple thread information if it is set. - * So don't set it here for Intel to make Linux guests happy. - */ - if (threads_per_pkg > 1) { - if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || - env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || - env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { - *ecx |= 1 << 1; /* CmpLegacy bit */ - } - } if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && !(env->hflags & HF_LMA_MASK)) { *edx &= ~CPUID_EXT2_SYSCALL; @@ -7529,6 +7518,15 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (x86_threads_per_pkg(&env->topo_info) > 1) { env->features[FEAT_1_EDX] |= CPUID_HT; + + /* + * The Linux kernel checks for the CMPLegacy bit and + * discards multiple thread information if it is set. + * So don't set it here for Intel to make Linux guests happy. + */ + if (!IS_INTEL_CPU(env)) { + env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; + } } for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {