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[79.136.22.50]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223b28722sm145975e87.243.2024.12.19.04.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 04:31:29 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: andrew@lunn.ch, f.fainelli@gmail.com, olteanv@gmail.com, netdev@vger.kernel.org, linux@armlinux.org.uk, chris.packham@alliedtelesis.co.nz, pabeni@redhat.com Subject: [PATCH v2 net 1/4] net: dsa: mv88e6xxx: Improve I/O related error logging Date: Thu, 19 Dec 2024 13:30:40 +0100 Message-ID: <20241219123106.730032-2-tobias@waldekranz.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241219123106.730032-1-tobias@waldekranz.com> References: <20241219123106.730032-1-tobias@waldekranz.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Addiva Elektronik X-Patchwork-Delegate: kuba@kernel.org In the rare event of an I/O error - e.g. a broken bus controller, frozen chip, etc. - make sure to log all available information, so that there is some hope of determining _where_ the error; not just _that_ an error occurred. Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.c | 51 +++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 3a792f79270d..46926b769460 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -59,8 +59,11 @@ int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) assert_reg_lock(chip); err = mv88e6xxx_smi_read(chip, addr, reg, val); - if (err) + if (err) { + dev_err_ratelimited(chip->dev, "Failed to read from 0x%02x/0x%02x: %d", + addr, reg, err); return err; + } dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", addr, reg, *val); @@ -75,17 +78,19 @@ int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) assert_reg_lock(chip); err = mv88e6xxx_smi_write(chip, addr, reg, val); - if (err) + if (err) { + dev_err_ratelimited(chip->dev, "Failed to write 0x%04x to 0x%02x/0x%02x: %d", + val, addr, reg, err); return err; - + } dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", addr, reg, val); return 0; } -int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, - u16 mask, u16 val) +static int _mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, + u16 mask, u16 val, u16 *last) { const unsigned long timeout = jiffies + msecs_to_jiffies(50); u16 data; @@ -117,15 +122,45 @@ int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, if ((data & mask) == val) return 0; - dev_err(chip->dev, "Timeout while waiting for switch\n"); + if (last) + *last = data; + return -ETIMEDOUT; } +int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, + u16 mask, u16 val) +{ + u16 last; + int err; + + err = _mv88e6xxx_wait_mask(chip, addr, reg, mask, val, &last); + if (!err) + return 0; + + dev_err(chip->dev, + "%s waiting for 0x%02x/0x%02x to match 0x%04x (mask:0x%04x last:0x%04x)\n", + (err == -ETIMEDOUT) ? "Timed out" : "Failed", + addr, reg, val, mask, last); + return err; +} + int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, int bit, int val) { - return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), - val ? BIT(bit) : 0x0000); + u16 last; + int err; + + err = _mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), + val ? BIT(bit) : 0x0000, &last); + if (!err) + return 0; + + dev_err(chip->dev, + "%s waiting for bit %d in 0x%02x/0x%02x to %s (last:0x%04x)\n", + (err == -ETIMEDOUT) ? "Timed out" : "Failed", + bit, addr, reg, val ? "set" : "clear", last); + return err; } struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) From patchwork Thu Dec 19 12:30:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tobias Waldekranz X-Patchwork-Id: 13915021 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 322BE22757A for ; Thu, 19 Dec 2024 12:31:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734611498; cv=none; b=cuNrUsFb0nGvITrwkbk4t/wuP7NugmwNwBef/jWg8TxXZBBIn9wPgIFQLng9rlrwegmgPuv5+PqTeorRnozhvSI7fMgyV1/L1cVeV2Syn8ytWZOlakrMfyFaJy6rsUiBqQQCBQ1k58mHn7aIn8gxySfsNClSMpKs2eiIU/rHQqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734611498; c=relaxed/simple; bh=eG/KWNgmsoX96wx43T0aE6wr0gUHnDtXlepdD8zP+Ac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZU2JkPUxuhAhCUhSAVUPWCTlYZ181GcHTkyC5EsED4/AOz/d4T/xfm0oHHbxu2zuE6dTuD8jQtWytPKA+C1wX9WKY0eewnIQfs4IJlk9y5ycJOHrk0AAEFIzSon62M8a7+dnYLFVLDmYlyJ2XMiH/ibKbpAHcggyFnYLpVN+w60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=waldekranz.com; spf=pass smtp.mailfrom=waldekranz.com; dkim=pass (2048-bit key) header.d=waldekranz-com.20230601.gappssmtp.com header.i=@waldekranz-com.20230601.gappssmtp.com header.b=qBLcYn1r; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=waldekranz.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=waldekranz.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=waldekranz-com.20230601.gappssmtp.com header.i=@waldekranz-com.20230601.gappssmtp.com header.b="qBLcYn1r" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-53f22fd6832so656889e87.1 for ; Thu, 19 Dec 2024 04:31:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=waldekranz-com.20230601.gappssmtp.com; s=20230601; t=1734611494; x=1735216294; darn=vger.kernel.org; h=content-transfer-encoding:organization:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to; bh=T9ewfodQmWnYrWnDlQ1tRoBvOOanfWQbaFltm/ARv+c=; b=qBLcYn1ragVrSBJkydWwfOxE3F2ODpmh+pFIhFyiUiuvI2fkm633/j8Tit6AZaUBpU lhrP+6momFCVGJY7v1dnoyRX89mvIyhA2cHLewmACfbpebHR3rzRpBel4a5y60kWJhFC z8he41qLJPcRY6UBRdfH2GGL/19bQEGGadOg2PGoa0NFyHlKhStVK3VJveZ4ltaRB5+o /T52xMOw05bUD5Ky82N40SlFdF5oBlyWiI6aXtVbN2doethOE5gUTyKeq3YiWvjK7xFE zOa+x3/DjEQ1ahSdaNQnNP+tlS7sqwGcPTqUPNekdLH2LjVspOLdywBZ7GbzLu4ozP6o Psvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734611494; x=1735216294; h=content-transfer-encoding:organization:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=T9ewfodQmWnYrWnDlQ1tRoBvOOanfWQbaFltm/ARv+c=; b=g1JomSnKLmF+n1U8dTHWQDQ4yStTbmcDjrCWDGzpZoqeAamkVAsm/DL3/AT//iCQSD eQFnK6Xs+395s8DCG08bcn3LXaRsbbWPEyu5dk1JHsmF44dEo0N5xOk1ZLbKocqMUqf2 1zHDa7JRVVJxSqVFVdQQrk+WISx+HNSe46LsHZzhlD6jtyU5HVrEi90diyj4wmUGnTB+ Gfi8/HGgo5L7fGya495jdxKLv0U9iTFnqn8MWUQ06EYeMuKEoVY+M/ym7s/GowozMDWu tdGlAMgNLDuz004wbE7GgrF3sW3nqwxawIeMnkBt1dLbvAZ5j3qA4kg2QZ/4hf2ZtCzB eXpw== X-Forwarded-Encrypted: i=1; AJvYcCU49AarZ2r77QcUbDCQKlWMc05OiGJ1yOSSD7uVmxRfO5EG86P1uhW30hJKStCJFVZl5l3T6vc=@vger.kernel.org X-Gm-Message-State: AOJu0Yyg36HTZdA4N8Nf7R2YvWaJbVQl3EGB7vCVHU43ZW3MGx2E5Z7r NPk+eOR0EBR+fj4dYymK9l8kILggqYqg6eqle+Vdbig7ZrWdf/NgWZG1CExEj6o= X-Gm-Gg: ASbGncvzLvBdjPhFj9T0Y8FG4AvTeeNsh5B9QnFEoqm6tCRNmUul5oCq/oeKsLvICrp PY4BAsiENwOfZ/m50br603YCbyiC8qeE5YL4ZMqXN8UfPN6iU5tArT0CoIz48liAooUGpH9j8QR okBRbJhvsi/sKuLXX1z14coCmuRcs2t7TuDDXbuBXfBIXAGNZwpHOFno7mLEeTT/EBeE7Bw4PAa WUg6Sku0FDhaxhG/xiYlIcnE/2YvPOhIJugbmvHBF8Yrc3HLprIZwuiC3L2+W+7rh9lbiRpqgiA i7EdjzWaJEbl6ZI87TQx/9LT X-Google-Smtp-Source: AGHT+IEtt+caURBdLa9qm0DKCE0IhUhc8vtL5ravQ0ZXkEKN6ZWAAmoa/M9QHQhtH3GExu8YdQJAQA== X-Received: by 2002:a05:6512:3e07:b0:540:3561:962b with SMTP id 2adb3069b0e04-541ed8e4c74mr2238843e87.15.1734611494244; Thu, 19 Dec 2024 04:31:34 -0800 (PST) Received: from wkz-x13.addiva.ad (h-79-136-22-50.NA.cust.bahnhof.se. [79.136.22.50]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223b28722sm145975e87.243.2024.12.19.04.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 04:31:32 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: andrew@lunn.ch, f.fainelli@gmail.com, olteanv@gmail.com, netdev@vger.kernel.org, linux@armlinux.org.uk, chris.packham@alliedtelesis.co.nz, pabeni@redhat.com Subject: [PATCH v2 net 2/4] net: dsa: mv88e6xxx: Give chips more time to activate their PPUs Date: Thu, 19 Dec 2024 13:30:41 +0100 Message-ID: <20241219123106.730032-3-tobias@waldekranz.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241219123106.730032-1-tobias@waldekranz.com> References: <20241219123106.730032-1-tobias@waldekranz.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Addiva Elektronik X-Patchwork-Delegate: kuba@kernel.org In a daisy-chain of three 6393X devices, delays of up to 750ms are sometimes observed before completion of PPU initialization (Global 1, register 0, bit 15) is signaled. Therefore, allow chips more time before giving up. Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 46926b769460..c7683ea334a7 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -92,7 +92,7 @@ int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) static int _mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask, u16 val, u16 *last) { - const unsigned long timeout = jiffies + msecs_to_jiffies(50); + const unsigned long timeout = jiffies + msecs_to_jiffies(2000); u16 data; int err; int i; From patchwork Thu Dec 19 12:30:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tobias Waldekranz X-Patchwork-Id: 13915022 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C72EC227584 for ; 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[79.136.22.50]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223b28722sm145975e87.243.2024.12.19.04.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 04:31:35 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: andrew@lunn.ch, f.fainelli@gmail.com, olteanv@gmail.com, netdev@vger.kernel.org, linux@armlinux.org.uk, chris.packham@alliedtelesis.co.nz, pabeni@redhat.com Subject: [PATCH v2 net 3/4] net: dsa: mv88e6xxx: Never force link on in-band managed MACs Date: Thu, 19 Dec 2024 13:30:42 +0100 Message-ID: <20241219123106.730032-4-tobias@waldekranz.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241219123106.730032-1-tobias@waldekranz.com> References: <20241219123106.730032-1-tobias@waldekranz.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Addiva Elektronik X-Patchwork-Delegate: kuba@kernel.org NOTE: This issue was addressed in the referenced commit, but a conservative approach was chosen, where only 6095, 6097 and 6185 got the fix. Before the referenced commit, in the following setup, when the PHY detected loss of link on the MDI, mv88e6xxx would force the MAC down. If the MDI-side link was then re-established later on, there was no longer any MII link over which the PHY could communicate that information back to the MAC. .-SGMII/USXGMII | .-----. v .-----. .--------------. | MAC +---+ PHY +---+ MDI (Cu/SFP) | '-----' '-----' '--------------' Since this a generic problem on all MACs connected to a SERDES - which is the only time when in-band-status is used - move all chips to a common mv88e6xxx_port_sync_link() implementation which avoids forcing links on _all_ in-band managed ports. Fixes: 4efe76629036 ("net: dsa: mv88e6xxx: Don't force link when using in-band-status") Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.c | 35 +++----------------------------- drivers/net/dsa/mv88e6xxx/chip.h | 4 ---- drivers/net/dsa/mv88e6xxx/port.c | 17 ---------------- drivers/net/dsa/mv88e6xxx/port.h | 1 - 4 files changed, 3 insertions(+), 54 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index c7683ea334a7..707dfe5c1ed8 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -1007,8 +1007,8 @@ static void mv88e6xxx_mac_link_down(struct phylink_config *config, * updated by the switch or if we are using fixed-link mode. */ if ((!mv88e6xxx_port_ppu_updates(chip, port) || - mode == MLO_AN_FIXED) && ops->port_sync_link) - err = ops->port_sync_link(chip, port, mode, false); + mode == MLO_AN_FIXED)) + err = mv88e6xxx_port_sync_link(chip, port, mode, false); if (!err && ops->port_set_speed_duplex) err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, @@ -1048,8 +1048,7 @@ static void mv88e6xxx_mac_link_up(struct phylink_config *config, goto error; } - if (ops->port_sync_link) - err = ops->port_sync_link(chip, port, mode, true); + err = mv88e6xxx_port_sync_link(chip, port, mode, true); } error: mv88e6xxx_reg_unlock(chip); @@ -4213,7 +4212,6 @@ static const struct mv88e6xxx_ops mv88e6085_ops = { .phy_read = mv88e6185_phy_ppu_read, .phy_write = mv88e6185_phy_ppu_write, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, .port_set_policy = mv88e6352_port_set_policy, @@ -4257,7 +4255,6 @@ static const struct mv88e6xxx_ops mv88e6095_ops = { .phy_read = mv88e6185_phy_ppu_read, .phy_write = mv88e6185_phy_ppu_write, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6185_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_set_frame_mode = mv88e6085_port_set_frame_mode, .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, @@ -4292,7 +4289,6 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6185_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, .port_set_policy = mv88e6352_port_set_policy, @@ -4339,7 +4335,6 @@ static const struct mv88e6xxx_ops mv88e6123_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_set_frame_mode = mv88e6085_port_set_frame_mode, .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, @@ -4377,7 +4372,6 @@ static const struct mv88e6xxx_ops mv88e6131_ops = { .phy_read = mv88e6185_phy_ppu_read, .phy_write = mv88e6185_phy_ppu_write, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, .port_set_frame_mode = mv88e6351_port_set_frame_mode, @@ -4422,7 +4416,6 @@ static const struct mv88e6xxx_ops mv88e6141_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, .port_max_speed_mode = mv88e6341_port_max_speed_mode, @@ -4483,7 +4476,6 @@ static const struct mv88e6xxx_ops mv88e6161_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, .port_set_policy = mv88e6352_port_set_policy, @@ -4529,7 +4521,6 @@ static const struct mv88e6xxx_ops mv88e6165_ops = { .phy_read = mv88e6165_phy_read, .phy_write = mv88e6165_phy_write, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -4568,7 +4559,6 @@ static const struct mv88e6xxx_ops mv88e6171_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -4616,7 +4606,6 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -4671,7 +4660,6 @@ static const struct mv88e6xxx_ops mv88e6175_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -4719,7 +4707,6 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -4773,7 +4760,6 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { .phy_read = mv88e6185_phy_ppu_read, .phy_write = mv88e6185_phy_ppu_write, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6185_port_sync_link, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_set_frame_mode = mv88e6085_port_set_frame_mode, .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, @@ -4815,7 +4801,6 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, .port_max_speed_mode = mv88e6390_port_max_speed_mode, @@ -4875,7 +4860,6 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, .port_max_speed_mode = mv88e6390x_port_max_speed_mode, @@ -4935,7 +4919,6 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, .port_max_speed_mode = mv88e6390_port_max_speed_mode, @@ -4995,7 +4978,6 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5056,7 +5038,6 @@ static const struct mv88e6xxx_ops mv88e6250_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5100,7 +5081,6 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, .port_max_speed_mode = mv88e6390_port_max_speed_mode, @@ -5162,7 +5142,6 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5211,7 +5190,6 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5259,7 +5237,6 @@ static const struct mv88e6xxx_ops mv88e6341_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, .port_max_speed_mode = mv88e6341_port_max_speed_mode, @@ -5322,7 +5299,6 @@ static const struct mv88e6xxx_ops mv88e6350_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5368,7 +5344,6 @@ static const struct mv88e6xxx_ops mv88e6351_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5418,7 +5393,6 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, .port_tag_remap = mv88e6095_port_tag_remap, @@ -5481,7 +5455,6 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, .port_max_speed_mode = mv88e6390_port_max_speed_mode, @@ -5545,7 +5518,6 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, .port_max_speed_mode = mv88e6390x_port_max_speed_mode, @@ -5608,7 +5580,6 @@ static const struct mv88e6xxx_ops mv88e6393x_ops = { .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, .port_set_link = mv88e6xxx_port_set_link, - .port_sync_link = mv88e6xxx_port_sync_link, .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, .port_max_speed_mode = mv88e6393x_port_max_speed_mode, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 9fe8e8a7856b..27d19d55f9e5 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -525,10 +525,6 @@ struct mv88e6xxx_ops { */ int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); - /* Synchronise the port link state with that of the SERDES - */ - int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); - #define PAUSE_ON 1 #define PAUSE_OFF 0 diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index dc777ddce1f3..56ed2f57fef8 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -187,23 +187,6 @@ int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int int err = 0; int link; - if (isup) - link = LINK_FORCED_UP; - else - link = LINK_FORCED_DOWN; - - if (ops->port_set_link) - err = ops->port_set_link(chip, port, link); - - return err; -} - -int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) -{ - const struct mv88e6xxx_ops *ops = chip->info->ops; - int err = 0; - int link; - if (mode == MLO_AN_INBAND) link = LINK_UNFORCED; else if (isup) diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h index c1d2f99efb1c..26452e0a8448 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -484,7 +484,6 @@ int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); -int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); int 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[79.136.22.50]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223b28722sm145975e87.243.2024.12.19.04.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 04:31:39 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: andrew@lunn.ch, f.fainelli@gmail.com, olteanv@gmail.com, netdev@vger.kernel.org, linux@armlinux.org.uk, chris.packham@alliedtelesis.co.nz, pabeni@redhat.com Subject: [PATCH v2 net 4/4] net: dsa: mv88e6xxx: Limit rsvd2cpu policy to user ports on 6393X Date: Thu, 19 Dec 2024 13:30:43 +0100 Message-ID: <20241219123106.730032-5-tobias@waldekranz.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241219123106.730032-1-tobias@waldekranz.com> References: <20241219123106.730032-1-tobias@waldekranz.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Addiva Elektronik X-Patchwork-Delegate: kuba@kernel.org For packets with a DA in the IEEE reserved L2 group range, originating from a CPU, forward it as normal, rather than classifying it as management. Example use-case: bridge (group_fwd_mask 0x4000) / | \ swp1 swp2 tap0 \ / (mv88e6xxx) We've created a bridge with a non-zero group_fwd_mask (allowing LLDP in this example) containing a set of ports managed by mv88e6xxx and some foreign interface (e.g. an L2 VPN tunnel). Since an LLDP packet coming in to the bridge from the other side of tap0 is eligable for tx forward offloading, a FORWARD frame destined for swp1 and swp2 would be send to the conduit interface. Before this change, due to rsvd2cpu being enabled on the CPU port, the switch would try to trap it back to the CPU. Given that the CPU is trusted, instead assume that it indeed meant for the packet to be forwarded like any other. Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/port.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 56ed2f57fef8..bf6d558c112c 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1416,6 +1416,23 @@ static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, return 0; } +static int mv88e6393x_port_policy_write_user(struct mv88e6xxx_chip *chip, + u16 pointer, u8 data) +{ + int err, port; + + for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { + if (!dsa_is_user_port(chip->ds, port)) + continue; + + err = mv88e6393x_port_policy_write(chip, port, pointer, data); + if (err) + return err; + } + + return 0; +} + int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, enum mv88e6xxx_egress_direction direction, int port) @@ -1457,26 +1474,28 @@ int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) int err; /* Consider the frames with reserved multicast destination - * addresses matching 01:80:c2:00:00:00 and - * 01:80:c2:00:00:02 as MGMT. + * addresses matching 01:80:c2:00:00:00 and 01:80:c2:00:00:02 + * as MGMT when received on user ports. Forward as normal on + * CPU/DSA ports, to support bridges with non-zero + * group_fwd_masks. */ ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; - err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); + err = mv88e6393x_port_policy_write_user(chip, ptr, 0xff); if (err) return err; ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; - err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); + err = mv88e6393x_port_policy_write_user(chip, ptr, 0xff); if (err) return err; ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; - err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); + err = mv88e6393x_port_policy_write_user(chip, ptr, 0xff); if (err) return err; ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; - err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); + err = mv88e6393x_port_policy_write_user(chip, ptr, 0xff); if (err) return err;