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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Shahar Shitrit , Yevgeny Kliteynik , Tariq Toukan Subject: [PATCH net 1/4] net/mlx5: DR, select MSIX vector 0 for completion queue creation Date: Fri, 20 Dec 2024 10:15:02 +0200 Message-ID: <20241220081505.1286093-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241220081505.1286093-1-tariqt@nvidia.com> References: <20241220081505.1286093-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|CH2PR12MB4103:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cffd109-0d92-4297-5c84-08dd20ce8b70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: P6Q9nkdh7OdNQvZp3IYolQ8xFLZZj6j/nfnq3HaQ9hH1qwrxv1FRD+G2kvHCGe1QvuWmbxk+eNi8ve7efh8rLhEH5WUBYHZiSquLCLsxkmkYR/WoSaS6keBRlP7n80MMUSvba7BD2Xg9uS/dyg2VZ6V8LrkV+NVHlUZzIzhMwFHAs13fXYQpcuedvL/cA/85c0D9C654Lh3i+6HRaO7QGm1mokk31QjNMzL43k27gp0dDGnG89k7lZucp8ENMVYsN1/CtLD6cJTcpBdlfAY8vet/+iMP3dV3TPckP19FyquEsN7wuoCdUP0pJynaWUiM0F6cz9Tv8LpdNlPDv+LXjUxlMBnzOv0ppdmXn0XfHXHMR2jXhvg20TIKI3X+CdSi0xoVH40uJow7HiRcpmSxMDLQyMle8+tMlKQkga30SxNsQmfaWl4c/zLuWnwrrFui8UWMW6TfA42fbavZFmsTmbpS+wbiQxbxJt+nrAN/qXUhTOIBZEOlEWqrdcw3gocICAhQJLqJLJ8ePh9IzHT9YjghwviLwskhCnDld3VYvXNq7f5eXqWb9VMP6z1Np/OxioIkOLxypTX4eODksZLar1Js0JvRqpbiaOgHiiCtgGcsQ+Bsi2yv5KO9Yge87kN4gnJ485HZVD3GaocScBaSTy9sXAzplPclzUCM4GHWjRQcEUaHRMNWphQWxsFU78K7h/SFVtEy4+quDhfwnYO13yUxjs3DeCz+NDBEmuqrTvQkg9Yx77ZL5mmOXShP5EwWssxh8+HO/Orhb83Ek276H4LSADk3rGPAAgWqmaFKQYtBS9lNhVjji9QRLsQwdcnAGRYB8MDNEJ9LaqNVz96GLdm4MyYldbKljqvnRAiN/AXIGou1KQYW6R0I9hPEXFzEKRLVizW9r/SXscq7lY2l1D0hUGy2wiy3OLu8a6USlwu5ZbhSiAbQwu6udr2X1+D/d2taMuWaJgqaWMlF5hp0NZbygwXerOs8Eg9hGGFcPhOWzBwQGmsVrlYHdwNTa95jHLSvMLH7DKFmC6a0MF3wvj+DOWTs6Kb9RwyEG/+iR3W7860CaaET3PYfs/eLMHV670TJLsF9vVL13n93IsxjjFq1ksDYSBUtyeJQkcrSxhCciKLx6/iFmkQrlsfWuULfRKZDe8kmHeBmiy3bPLJZbI14p2W0t+em/W6d9d16PIQ8pzcuXRszZXPahAFkBENuICVqQ5jM8wa6Qc1AJqU++IKsbsozlpUGQO/NtEw1UlDFbGqmaWxMHgl42u0235EIp3Fy23mgFM/wUdvxoyajCIYyV1HJnjVbY6pH4c1x11TDPrFbQcHeALznQHNpze//rlXqWFn0Oat8ltmQuSlmlo3Ms2FMEY8pXBU8RiZPtt9UlG+/0/5nuy+/YxlgYRGEz6J17UqeCPeU7+tORqKuii9rGL79bWu/BbVbSK61xsRPVACW0UdFiImUQJSvDhMcry8RKFoykvnPGc5ZmpKC0ZUe/hp/aMwIG+pKZI9aV/o= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2024 08:16:02.9977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cffd109-0d92-4297-5c84-08dd20ce8b70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4103 X-Patchwork-Delegate: kuba@kernel.org From: Shahar Shitrit When creating a software steering completion queue (CQ), an arbitrary MSIX vector n is selected. This results in the CQ sharing the same Ethernet traffic channel n associated with the chosen vector. However, the value of n is often unpredictable, which can introduce complications for interrupt monitoring and verification tools. Moreover, SW steering uses polling rather than event-driven interrupts. Therefore, there is no need to select any MSIX vector other than the existing vector 0 for CQ creation. In light of these factors, and to enhance predictability, we modify the code to consistently select MSIX vector 0 for CQ creation. Fixes: 297cccebdc5a ("net/mlx5: DR, Expose an internal API to issue RDMA operations") Signed-off-by: Shahar Shitrit Reviewed-by: Yevgeny Kliteynik Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c index 6fa06ba2d346..f57c84e5128b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c @@ -1067,7 +1067,6 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_core_dev *mdev, int inlen, err, eqn; void *cqc, *in; __be64 *pas; - int vector; u32 i; cq = kzalloc(sizeof(*cq), GFP_KERNEL); @@ -1096,8 +1095,7 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_core_dev *mdev, if (!in) goto err_cqwq; - vector = raw_smp_processor_id() % mlx5_comp_vectors_max(mdev); - err = mlx5_comp_eqn_get(mdev, vector, &eqn); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Dragos Tatulea , Cosmin Ratiu , Lior Nahmanson , Tariq Toukan Subject: [PATCH net 2/4] net/mlx5e: macsec: Maintain TX SA from encoding_sa Date: Fri, 20 Dec 2024 10:15:03 +0200 Message-ID: <20241220081505.1286093-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241220081505.1286093-1-tariqt@nvidia.com> References: <20241220081505.1286093-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|PH0PR12MB7079:EE_ X-MS-Office365-Filtering-Correlation-Id: b464496b-d72e-461b-3c92-08dd20ce8ead X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: EWdtGyyG5AJMQgcYK9GOnpi9FcNZCNiy9mhnXawxFtz853k9utlqVzsR4jwZfhX7zTsqqtuP6E/QUXl/6isvT1H486UsTt3IR4e42f9rBqTX6YyFLOWU7uUhd0CsUXND+TDbebQwCMfzOmKCT++ZYakY5TAg9t/qKE/8ReiJ9w+ux+0zq88OqWh7KXiPReRSMKu7eJUuK/o80k5uKdc7ew00wR3jsvNFnLUZvGgYTch7RzBVCJxGFQFdmEiEE86+huKu3nt4iCe3sgvlOhcMMXP8U3EQKQstp4cuxtHZoO4nBb2OIx7RGVP6/lB0o6HyTrs0QeTPmKARVBqdbOh9d/mo/i3vOb9lUVbEMvpSa8ZQsJWWo2EvBmZ14c15JipHngFgpTum+y4CEZJqBwZqHiK0+XXkr4g8Dwp+yGJLokMlPJltdJ8ozDvTlB4AJpSBnhq3oTv0BYidQ3L1LE+Md3NfilMuI/dFC5SX0FHGcGHtpu241y+J4nZd3W1f7eJFAV6Q+H8nlsTL//EqJ+pMZPI+o1NA/XX7w24N7Tbw+zk7XQafD7D7JMGsgCG5gLrKwoPaWcCh15pX691ZqwQwmFe+L1ORJE0tUxQjXR2t3lJlU7bhXXBF5ZqbAtZlYikwyjN7ym/53jOwZBlbF/ihWYAdBNksJY+MijmE3pkvxYhVGuV9FNLkssmrMlecnAKL6q9hAlFm+tRMSIFHQtMePfsFo5QDbyXbHDfQj2o0CQzbgJPLBXc0k7aLYDS/WIcuqBVsYwTb74XEuRJqx75fey5sbIx7VzNRVd8UpEeAYwgmvNxBQviRLTAHqkDKBchgjoR5u4HK5iyuYHuaIXScrolTuNZPQ0YQZWiZvpdRYOIDH+FyZ+OpZONDOYp0HGrwgyzBdTXyX0gz/rpUiamULZuPvvj73hKU0Wkk5s+III1wpSPW9pUk01RU81Qdr+QbxUjcnuSlMec5GQ0NHThuLkh7vCfN+rGMHbQIN+oY8NUoTaykhLS0ykbOA5qCbEdDdtShnhPc8uIVm5EQ7SkTWEZteB5vkG1nqvlTRVX5Q02PsNWAFoH/uwK7sMrwzs8zHldX9YoDRsP9NbD1STBF7DfiuXKZrwLlgICM369gs5JQ0tbC6d7l7rBUZ7Rfci2J0sWFU9SQZpUNV6Q1UOllavvkNKOeZwQ2EloIRhcSovSJw5ufyM6Dow/lh1vNPFIEOXzKFEfSecoF+dKMuKaG8rT7m4R8mGMeZ6jTKMOkg+bs32/8DIztLxXMfKoAaF9nXdEwys2z/HwO0sTAnLxTXnmvTbnVqR2wGD+dPglvmJslKTeG4EGCPk6Se7lHv/JyHuqHWNmoiIoABSz+6COYXvkkZXZakwaD2wP/+esfDwvn6RFaBL4ouzE67m+kX/sW1K3AmAiQERJBnCB0bcVyZE6OEs8ahAdKBQTnSPSKNxFx88bMjj/UMT6gQjG/aamzGi70fzxbvuMM66T/VGitJCcaMT0khyM5nPPcEbGY+Po= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2024 08:16:08.4298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b464496b-d72e-461b-3c92-08dd20ce8ead X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7079 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea In MACsec, it is possible to create multiple active TX SAs on a SC, but only one such SA can be used at a time for transmission. This SA is selected through the encoding_sa link parameter. When there are 2 or more active TX SAs configured (encoding_sa=0): ip macsec add macsec0 tx sa 0 pn 1 on key 00 ip macsec add macsec0 tx sa 1 pn 1 on key 00 ... the traffic should be still sent via TX SA 0 as the encoding_sa was not changed. However, the driver ignores the encoding_sa and overrides it to SA 1 by installing the flow steering id of the newly created TX SA into the SCI -> flow steering id hash map. The future packet tx descriptors will point to the incorrect flow steering rule (SA 1). This patch fixes the issue by avoiding the creation of the flow steering rule for an active TX SA that is not the encoding_sa. The driver side tx_sa object and the FW side macsec object are still created. When the encoding_sa link parameter is changed to another active TX SA, only the new flow steering rule will be created in the mlx5e_macsec_upd_txsa() handler. Fixes: 8ff0ac5be144 ("net/mlx5: Add MACsec offload Tx command support") Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Reviewed-by: Lior Nahmanson Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index cc9bcc420032..6ab02f3fc291 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -339,9 +339,13 @@ static int mlx5e_macsec_init_sa_fs(struct macsec_context *ctx, { struct mlx5e_priv *priv = macsec_netdev_priv(ctx->netdev); struct mlx5_macsec_fs *macsec_fs = priv->mdev->macsec_fs; + const struct macsec_tx_sc *tx_sc = &ctx->secy->tx_sc; struct mlx5_macsec_rule_attrs rule_attrs; union mlx5_macsec_rule *macsec_rule; + if (is_tx && tx_sc->encoding_sa != sa->assoc_num) + return 0; + rule_attrs.macsec_obj_id = sa->macsec_obj_id; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Jianbo Liu , Tariq Toukan Subject: [PATCH net 3/4] net/mlx5e: Skip restore TC rules for vport rep without loaded flag Date: Fri, 20 Dec 2024 10:15:04 +0200 Message-ID: <20241220081505.1286093-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241220081505.1286093-1-tariqt@nvidia.com> References: <20241220081505.1286093-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636A:EE_|SA0PR12MB4494:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f26c80c-7131-4026-59a6-08dd20ce900c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: N9CPl0WllPtkSSOLxrlEMv0ARWKd5bokGGyV6GsFaprbVneeLb43YH9jVe7GRHdnXRZhNQSFlr//LY8LTKU8GC32NlwxBqcA5fjKA/EFV+z/GJCc2YARY2TQ5MOq+SluS+w84AWV/ST1w6PuemRmIu/kCyHTWbZIqy8+Dp19YeCVVEcex/nw5HuHjZlAZUkw4LQDHoctzUPJzm7gc0ZqorD3vHYpDtkJS3ep9EeKPyBXshKiVbRo7HULgCUtQBAtwozh/AVUoAZCQUbDxz+oAJWdA5A9IRmdqpu2c2V5W56y6WcKsvgdoea7JSiEot7c6FNw80iutfN6d/7VjWDpJzzu4K25bwTTlrKdQSbQhHfVkP6etG4Dh+7Hhud8xklFJi+GtF/20wpX34fWeMdCZOEsTBooBW9fIm1mExQA14gOwgrZ7IGxQ6q7+3WEczDoBrlyhtQxw+VECdYLmexdQ7GC1ZMnnpkmv610QhdZN7VD6dcyLmZCdi3eBbX4X9lxHmTOBbVYmA/931UXUiVDj9XlylHHFODi3Bvm17WcYVtnmRQkT8ScdRM3u71ZJ8TGcMf49rUm/0MOjG0MFWL1/gji/kS+1N86xRuwzWsz3L3UgqlcMXlkecwhwUNUiLrBiQgqh/ySyUiSHQVRdJ5ppYL1Kq9vQGNaaalY3OIheeX8v/8X2wOFU/L+o+9vAaBUthBBID5tXayjLa4dcTppGKKeCR0UkDMjmRn7mztCWvySTTM93vQo/UNIqcwSUkZr5a4fi5fIbbLh9YBo9qd8tdPYtDljmqdFgZH7LXBHHd7XJ9Beiexb/xkttXqSC0iLksgeuCbJDen1cDEh3ZgFpb3Z9dG/crgY/nyylFfV3Q2qdiwXQVoOucpKWgkq7JH0WyEgI3GvljmWi1PVI2BU+XjMAWEdJOeG9m+5F9+HW7haVDsO+Mgo/2kY8mO37UrnR13detQzlBsu4e7Lq3YB6g43fnZvtgOvyyRL0EzBTwvt/3uZYgbE8/o1G/mC5lf52s1S0j9sTeuCWj+yZLjRd9pyT7HFLX4IrVapE5lOGLZkxJYjZ5LWALaNzNklcTMDO9bjM8AL7M5VerGRauKEGmzQH89nY0TJ8+37lTsDYwtmHI44ipBOJzrfLsjnwnKBeuBhnKqx2vDXPpxhTLf1emQhn3AO7rtq11qnHFFMp2/p52qKi2iDiwpdXGV4LxIU+kz/FXcqoVCCJRBkroBi+ANzKJ2ZNaWs2HjZD35bpi8q0o5Ff4hPmj4WyapjIeMwi08OduMi2kvunYvLmPObHtsfO2tFr30+EvBwr3wVWhhc30Yj9e7oW3hi2QVK/eeMzjXUwN+L8C/pPAZbhbY2HqeTm4GnmObJrHsl48KT8oYa3NBrrc8SfyX81Cmm0eOYuaZ2UByppVndouUMo2Sef0o0Ry7hiz+QW0rcJ/PK0lBnz2U5Xqy77F6PZbHq3sCE0fHJwiDDC2ZK3xo5wEzesOnSHzZjIBwACvZ9Xjg9HAU= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2024 08:16:10.7308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f26c80c-7131-4026-59a6-08dd20ce900c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4494 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu During driver unload, unregister_netdev is called after unloading vport rep. So, the mlx5e_rep_priv is already freed while trying to get rpriv->netdev, or walk rpriv->tc_ht, which results in use-after-free. So add the checking to make sure access the data of vport rep which is still loaded. Fixes: d1569537a837 ("net/mlx5e: Modify and restore TC rules for IPSec TX rules") Signed-off-by: Jianbo Liu Reviewed-by: Saeed Mahameed Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c | 6 +++--- drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 3 +++ drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 3 --- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c index 5a0047bdcb51..ed977ae75fab 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c @@ -150,11 +150,11 @@ void mlx5_esw_ipsec_restore_dest_uplink(struct mlx5_core_dev *mdev) unsigned long i; int err; - xa_for_each(&esw->offloads.vport_reps, i, rep) { - rpriv = rep->rep_data[REP_ETH].priv; - if (!rpriv || !rpriv->netdev) + mlx5_esw_for_each_rep(esw, i, rep) { + if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED) continue; + rpriv = rep->rep_data[REP_ETH].priv; rhashtable_walk_enter(&rpriv->tc_ht, &iter); rhashtable_walk_start(&iter); while ((flow = rhashtable_walk_next(&iter)) != NULL) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index a83d41121db6..8573d36785f4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -714,6 +714,9 @@ void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\ (last) - 1) +#define mlx5_esw_for_each_rep(esw, i, rep) \ + xa_for_each(&((esw)->offloads.vport_reps), i, rep) + struct mlx5_eswitch *__must_check mlx5_devlink_eswitch_get(struct devlink *devlink); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index d5b42b3a19fd..40359f320724 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -53,9 +53,6 @@ #include "lag/lag.h" #include "en/tc/post_meter.h" -#define mlx5_esw_for_each_rep(esw, i, rep) \ - xa_for_each(&((esw)->offloads.vport_reps), i, rep) - /* There are two match-all miss flows, one for unicast dst mac and * one for multicast. */ From patchwork Fri Dec 20 08:15:05 2024 Content-Type: text/plain; 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Fri, 20 Dec 2024 00:16:01 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Jianbo Liu , Tariq Toukan Subject: [PATCH net 4/4] net/mlx5e: Keep netdev when leave switchdev for devlink set legacy only Date: Fri, 20 Dec 2024 10:15:05 +0200 Message-ID: <20241220081505.1286093-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241220081505.1286093-1-tariqt@nvidia.com> References: <20241220081505.1286093-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|PH0PR12MB8030:EE_ X-MS-Office365-Filtering-Correlation-Id: 12854554-e2c8-459a-c831-08dd20ce91ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024|30052699003; X-Microsoft-Antispam-Message-Info: Oknqf1ZEG5DKx3jY+9kZlfHwOSCbKDVVvIEZ33gf61F/or1n293uWWm/terkOKNQ6Li/FF4gyhY7pwVYT900WxO501RWvkiIzmaOqY3M9PBHccNaU2QGSEjBCgYULNc0k7zErnvmyC3Xwq1Dj0G2SskNjOIbDi35QV7M0VNUzvciPnk6/LDYwPBoltN20/CNOUd/5aaYJ6OrM36sKLv7XgZ4NLdD/nApF9x7643KjoyMqBbaYobYlPP2RLx8RJrVX28V+ItSQR2A3FAe4vMJiBOp4x9El47K7DXK1L+fVaxP2I9c18DDh7GSKsg/XQRhvKwez6w//WFAbUcuQr4OIQC2m6SOSaZhBKyCn9xm7TaiC5DHaRGx+0rVtF6acfb9KStV41xh/HDckdxAUCJsvgZzYyi+7Xb7h+N424ogpgHPg+bV8KYmhC4+IucETzAIaFJKhy1ckUjaynzKlZJS8bW8sP9uTYAmJfhjYko+jDFDEeixGDs8XaCVsoEE0bTMkFuKXXBxUtcNv7jGOo8MFsF2wHIYQxMWBNRkO8al4O7EjphV3E9IDaQjgZriZkqukgrM8ShEnDYHjMGUtHNbniYI0AGYEXerAYmHUnTD9ly/FIvCv5ybOe4vxJ5vlMDaeGZKnxTu4j/ZaBPYzjtBomzrbROvouvJ5m83w2IVvex77iWSF770bpHhJ3Ta9o6Ec13SosMgzVqwcHdbIyuDIngve3Z1doIM02yGy3itwcP13c/KEcjiQ7AGdeLguBhysXeSIDWQogRo/FgsOhFH09CzbZkW+QjXrp4fOBOHSMU1WX+8UMWcSkcNzrqRkjQDADbjRWpImxlfwhQ00GNoKIZ0IX5Ovrsg6b3iNo3D8fk+cfNP7KCO4XLZhNXQ0HzgLLEhikfZhuBPIVYZfhQa8X6xSJD+8THIzNdidUEMEb7D755jpUWLYm48k8PamkKOjMgVBpAILJOnw2Zkr6I03lUWGdjkbyuLJ7VFZzzkEV7KvyKgSjXpByjiip2S9gURxjEKxgMJZFDkvTR7zSD22MmTr1pCqzg8Bt8qNTiJTUYcc2p1WzsepRxOKJ3IodB8sWWWpOLAYbBqYt0U0CxraO0KZC8X5YtTSPYE0BHg1lsW52Cv8GOItnzR8MubPRiNGwja4+0+K3BfaNuwQ8vCGfXkza9U9aWys27PEjAmLfjY+TcJBPAJ1y0vxyS/ImbF/KN6ZQUZzA8cUzXAMn41fUBPzkjh+4AUq2HujXwcW3AH3eDw/nBYw9wSLgu1xBT92xtATkVDf+rlDJFauJtEavtaDfbSwmYDKDOGC5NOtIqSKvdrkAYjwb3vFH8CfS5Zo0UiHyqA1F2o3wW8kwADnSAwZ0VAYxLfXMwONJA2TNkQw9roCZYhARSe6Uy6if361pIb/eX8EBMG/Z50ED3fiukXEvTTnNp/1h4lp3MK40QTYKRsJJGERjqm57z8ZXIO5wd9Rs2bkEBW85KybWdpzySWYQ9wbJjKV+7eaSMipyo= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024)(30052699003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2024 08:16:13.9419 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 12854554-e2c8-459a-c831-08dd20ce91ec X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8030 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu In the cited commit, when changing from switchdev to legacy mode, uplink representor's netdev is kept, and its profile is replaced with nic profile, so netdev is detached from old profile, then attach to new profile. During profile change, the hardware resources allocated by the old profile will be cleaned up. However, the cleanup is relying on the related kernel modules. And they may need to flush themselves first, which is triggered by netdev events, for example, NETDEV_UNREGISTER. However, netdev is kept, or netdev_register is called after the cleanup, which may cause troubles because the resources are still referred by kernel modules. The same process applies to all the caes when uplink is leaving switchdev mode, including devlink eswitch mode set legacy, driver unload and devlink reload. For the first one, it can be blocked and returns failure to users, whenever possible. But it's hard for the others. Besides, the attachment to nic profile is unnecessary as the netdev will be unregistered anyway for such cases. So in this patch, the original behavior is kept only for devlink eswitch set mode legacy. For the others, moves netdev unregistration before the profile change. Fixes: 7a9fb35e8c3a ("net/mlx5e: Do not reload ethernet ports when changing eswitch mode") Signed-off-by: Jianbo Liu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 19 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/en_rep.c | 15 +++++++++++++++ .../mellanox/mlx5/core/eswitch_offloads.c | 2 ++ include/linux/mlx5/driver.h | 1 + 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index dd16d73000c3..0ec17c276bdd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -6542,8 +6542,23 @@ static void _mlx5e_remove(struct auxiliary_device *adev) mlx5_core_uplink_netdev_set(mdev, NULL); mlx5e_dcbnl_delete_app(priv); - unregister_netdev(priv->netdev); - _mlx5e_suspend(adev, false); + /* When unload driver, the netdev is in registered state + * if it's from legacy mode. If from switchdev mode, it + * is already unregistered before changing to NIC profile. + */ + if (priv->netdev->reg_state == NETREG_REGISTERED) { + unregister_netdev(priv->netdev); + _mlx5e_suspend(adev, false); + } else { + struct mlx5_core_dev *pos; + int i; + + if (test_bit(MLX5E_STATE_DESTROYING, &priv->state)) + mlx5_sd_for_each_dev(i, mdev, pos) + mlx5e_destroy_mdev_resources(pos); + else + _mlx5e_suspend(adev, true); + } /* Avoid cleanup if profile rollback failed. */ if (priv->profile) priv->profile->cleanup(priv); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c index 554f9cb5b53f..fdff9fd8a89e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c @@ -1509,6 +1509,21 @@ mlx5e_vport_uplink_rep_unload(struct mlx5e_rep_priv *rpriv) priv = netdev_priv(netdev); + /* This bit is set when using devlink to change eswitch mode from + * switchdev to legacy. As need to keep uplink netdev ifindex, we + * detach uplink representor profile and attach NIC profile only. + * The netdev will be unregistered later when unload NIC auxiliary + * driver for this case. + * We explicitly block devlink eswitch mode change if any IPSec rules + * offloaded, but can't block other cases, such as driver unload + * and devlink reload. We have to unregister netdev before profile + * change for those cases. This is to avoid resource leak because + * the offloaded rules don't have the chance to be unoffloaded before + * cleanup which is triggered by detach uplink representor profile. + */ + if (!(priv->mdev->priv.flags & MLX5_PRIV_FLAGS_SWITCH_LEGACY)) + unregister_netdev(netdev); + mlx5e_netdev_attach_nic_profile(priv); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 40359f320724..06076dd9ec64 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3777,6 +3777,8 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, esw->eswitch_operation_in_progress = true; up_write(&esw->mode_lock); + if (mode == DEVLINK_ESWITCH_MODE_LEGACY) + esw->dev->priv.flags |= MLX5_PRIV_FLAGS_SWITCH_LEGACY; mlx5_eswitch_disable_locked(esw); if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) { if (mlx5_devlink_trap_get_num_active(esw->dev)) { diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index fc7e6153b73d..8f5991168ccd 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -524,6 +524,7 @@ enum { * creation/deletion on drivers rescan. Unset during device attach. */ MLX5_PRIV_FLAGS_DETACH = 1 << 2, + MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3, }; struct mlx5_adev {