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Fri, 20 Dec 2024 09:39:38 GMT Received: from hu-ylal-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 20 Dec 2024 01:39:36 -0800 From: Yogesh Lal To: Marc Zyngier , Thomas Gleixner CC: , , , Yogesh Lal Subject: [PATCH v2] irqchip: gic-v3: Handle failure case of CPU enters low power state Date: Fri, 20 Dec 2024 15:09:07 +0530 Message-ID: <20241220093907.2747601-1-quic_ylal@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gonb4XauVaqLoCnvy-dNg_E4wS0Mm12S X-Proofpoint-ORIG-GUID: gonb4XauVaqLoCnvy-dNg_E4wS0Mm12S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxlogscore=645 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1011 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412200079 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241220_013954_356159_90EA1E6F X-CRM114-Status: GOOD ( 14.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding a new condition in gic_cpu_pm_notifier to address instances where the CPU fails to enter low power mode (CPU_PM_ENTER_FAILED). The CPU_PM framework signals CPU_PM_ENTER_FAILED upon such failures. When the CPU attempts to enter low power mode, it disables the redistributor and Group 1 interrupts and reinitializes the system registers upon wakeup. In case of failure while entering low power mode, it is necessary to re-enable the redistributor and Group 1 interrupts to restore normal operation. Signed-off-by: Yogesh Lal --- drivers/irqchip/irq-gic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- Changes in V2: * Updating the commit message * Link to V1: https://lore.kernel.org/all/1671734140-15935-1-git-send-email-quic_ylal@quicinc.com/ --- diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index c19083bfb943..2a99ca5c3f1d 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1495,7 +1495,7 @@ static int gic_retrigger(struct irq_data *data) static int gic_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v) { - if (cmd == CPU_PM_EXIT) { + if (cmd == CPU_PM_EXIT || cmd == CPU_PM_ENTER_FAILED) { if (gic_dist_security_disabled()) gic_enable_redist(true); gic_cpu_sys_reg_init();