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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad831148sm4725429b3a.53.2024.12.21.05.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Dec 2024 05:12:53 -0800 (PST) Date: Sat, 21 Dec 2024 22:12:51 +0900 From: Krzysztof =?utf-8?q?Wilczy=C5=84ski?= To: Linus Torvalds Cc: Bjorn Helgaas , Lorenzo Pieralisi , Manivannan Sadhasivam , Lukas Wunner , Niklas Schnelle , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [GIT PULL] PCI fixes for v6.13 Message-ID: <20241221131251.GA1086543@rocinante> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Hello Linus, The following changes since commit 40384c840ea1944d7c5a392e8975ed088ecf0b37: Linux 6.13-rc1 (2024-12-01 14:28:56 -0800) are available in the Git repository at: ssh://git@gitolite.kernel.org/pub/scm/linux/kernel/git/pci/pci.git tags/pci-v6.13-fixes-2 for you to fetch changes up to 774c71c52aa487001c7da9f93b10cedc9985c371: PCI/bwctrl: Enable only if more than one speed is supported (2024-12-19 16:36:36 +0000) ---------------------------------------------------------------- PCI fixes for Linux 6.13 Two small patches that are important for fixing boot time hang on Intel JHL7540 "Titan Ridge" platforms equipped with a Thunderbolt controller. The boot time issue manifests itself when a PCI Express bandwidth control is unnecessarily enabled on the Thunderbolt controller downstream ports, which only supports a link speed of 2.5 GT/s in accordance with USB4 v2 specification (p. 671, sec. 11.2.1, "PCIe Physical Layer Logical Sub-block"). As such, there is no need to enable bandwidth control on such downstream port links, which also works around the issue. Both patches were tested by the original reporter on the hardware on which the failure origin golly manifested itself. Both fixes were proven to resolve the reported boot hang issue, and both patches have been in linux-next this week with no reported problems. Signed-off-by: Krzysztof Wilczyński ---------------------------------------------------------------- Lukas Wunner (2): PCI: Honor Max Link Speed when determining supported speeds PCI/bwctrl: Enable only if more than one speed is supported drivers/pci/pci.c | 6 ++++-- drivers/pci/pcie/portdrv.c | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-)