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([183.82.41.52]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad90b949sm4877522b3a.176.2024.12.21.07.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Dec 2024 07:18:07 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Jagan Teki , Mitchell Ma Subject: [PATCH] arm64: dts: rockchip: Fix PCIe3 handling for Edgeble-6TOPS Modules Date: Sat, 21 Dec 2024 20:47:58 +0530 Message-Id: <20241221151758.345257-1-jagan@edgeble.ai> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241221_071809_443205_379C7EE4 X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The Edgeble 6TOPS modules has configured the PCIe3.0 with - 2 lanes on Port1 of pcie3x2 controller for M.2 M-Key - 2 lanes on Port0 of pcie3x4 controller for B and E-Key The, current DT uses opposite controller nodes that indeed uses incorrect reset, regulator nodes. The configuration also uses refclk oscillator that need to enable explicitly in DT to avoid the probe hang on while reading DBI. So, this patch fixes all these essential issues and make this PCIe work properly. Issues fixed are, - Fix the associate controller nodes for M and B, E-Key - Fix the reset gpio handlings - Fix the regulator handlings and naming convensions - Support pcie_refclk oscillator Fixes: 92eaee21abbd ("arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key") Fixes: 5d85d4c7e03b ("arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key") Reported-by: Mitchell Ma Co-developed-by: Mitchell Ma Signed-off-by: Jagan Teki --- .../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 81 ++++++++++++++----- 1 file changed, 59 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 05ae9bdcfbbd..7125790bbed2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -10,6 +10,15 @@ chosen { stdout-path = "serial2:1500000n8"; }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie2x1l0"; @@ -19,26 +28,26 @@ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { vin-supply = <&vcc_3v3_s3>; }; - vcc3v3_pcie3x2: regulator-vcc3v3-pcie3x2 { + vcc3v3_bkey: regulator-vcc3v3-bkey { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ pinctrl-names = "default"; - pinctrl-0 = <&pcie3x2_vcc3v3_en>; - regulator-name = "vcc3v3_pcie3x2"; + pinctrl-0 = <&pcie_4g_pwen>; + regulator-name = "vcc3v3_bkey"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; vin-supply = <&vcc5v0_sys>; }; - vcc3v3_pcie3x4: regulator-vcc3v3-pcie3x4 { + vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */ pinctrl-names = "default"; - pinctrl-0 = <&pcie3x4_vcc3v3_en>; - regulator-name = "vcc3v3_pcie3x4"; + pinctrl-0 = <&pcie30x4_pwren_h>; + regulator-name = "vcc3v3_pcie30"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; @@ -98,24 +107,52 @@ &pcie2x1l0 { }; &pcie30phy { + data-lanes = <1 1 2 2>; + /* separate clock lines from the clock generator to phy and devices */ + rockchip,rx-common-refclk-mode = <0 0 0 0>; status = "okay"; }; -/* B-Key and E-Key */ +/* M-Key */ &pcie3x2 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, + <&pcie30_port1_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + num-lanes = <2>; pinctrl-names = "default"; - pinctrl-0 = <&pcie3x2_rst>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ - vpcie3v3-supply = <&vcc3v3_pcie3x2>; + pinctrl-0 = <&pcie30x2_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; }; -/* M-Key */ +/* B-Key and E-Key */ &pcie3x4 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; pinctrl-names = "default"; - pinctrl-0 = <&pcie3x4_rst>; - reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ - vpcie3v3-supply = <&vcc3v3_pcie3x4>; + pinctrl-0 = <&pcie30x4_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_bkey>; status = "okay"; }; @@ -127,20 +164,20 @@ pcie2_0_rst: pcie2-0-rst { }; pcie3 { - pcie3x2_rst: pcie3x2-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; - pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { - rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + pcie_4g_pwen: pcie-4g-pwen { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; }; - pcie3x4_rst: pcie3x4-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; - pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x4_pwren_h: pcie30x4-pwren-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; }; };