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20241223125600eusmtip2c15e8572f2e770fc420851707013d25c~Tz55Y_9mD3173831738eusmtip2L; Mon, 23 Dec 2024 12:56:00 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 01/19] dt-bindings: clock: Add VO subsystem clocks and update address requirements Date: Mon, 23 Dec 2024 13:55:35 +0100 Message-Id: <20241223125553.3527812-2-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se1BUdRTH+917994LtnRdSX4joAJphYaPsek3wpA9YC440+TUaGVJW9wW Rti1XRBsmgkFNsElQyx0MViRx0a8lnZXIAjdJdYVZDYUFh12A0akNeTNWhoUy5Xyv+8553PO 95yZQ+MiI7mGTpSmcHKpOCmY9CaMHX91vzD8QaJka7bGD12xl2LI8FBNoerWbgyVtHcLkLNH j6EbcxMkqh2xUej31qME6tN+R6HMjjoSudROEk2pnAJ0vfkciWby2gEyzmSRqKbdQaG6uRIM nZ8yEKissRkgZU6FAP16NQo5nFcI5LquwpFS/RT6p6WRQgt9OgIVjbdRSD+WL0CWmn0oq+00 sWstO9GfTbFjLhfBmo/PUmyrW0OwTWoHxaqaugDbUJVDsgN9LSRbbN3D/nbCgrE/ln3BZtV0 YOzJ+a3sxM+9JPuVvgqwPZl26k3Re94R8VxS4mFOviXyQ+8Es3KBOGTxT5+scuEZwLw6F3jR kNkB7Vo3mQu8aRGjBdBdm4/xwSyA96eHCA8lYmYALLZ8tNxxbGgZqgTwRP81wAdjAObccWEe imS2w8HKEoGn4MtkEzD7l6NLFM6MAmi8fW7RkaZXMQeh4YdPPA0EswHe+rZuyU7IvAxb7IUC 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5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXcbjtH0vBcemKD6teMjcwHhbrYuTkkBAwkWh6OJGpi5GLQ0hgKaPEodvP mSASMhLXul+yQNjCEn+udbFBFL1ilOic95EZJMEmYCTxYPl8VhBbRGAxi8TefZUgRcwCbxkl rs/cCNYtLJApMe/lMUYQm0VAVeLWtPVgcV4Be4k916ezQmyQl9h/8CzYUE4BB4k1XTfA6oWA av6d+sAGUS8ocXLmE6BeDqAF6hLr5wmBhJmBWpu3zmaewCg4C0nVLISqWUiqFjAyr2IUSS0t zk3PLTbSK07MLS7NS9dLzs/dxAhMRtuO/dyyg3Hlq496hxiZOBgPMUpwMCuJ8B4SykwX4k1J rKxKLcqPLyrNSS0+xGgK9M1EZinR5HxgOswriTc0MzA1NDGzNDC1NDNWEudlu3I+TUggPbEk NTs1tSC1CKaPiYNTqoFp/+x/zBVi09TmG9hOuZRjFxm25NnxDKtDNsIhMR3sbx/oiyRY3LaI VbbYl/TCUWXeea4LZ2W3Sr+4FbXqbozy2vAPL2MmLqgQ23R2tvgdKz6P3FtXGEzN+Hh4fvNZ lNhmKrgVW36VLHwzcUGB0MXfKw49Emo7f+tKfcodLuuw6vZPLacuR1pILJ27X8FukvbXmY9v P5vZoc2xvubcRSXFRU/Cluu6b7P8FPEzoD3dZ+cXSb7SwLfT1/Q2vWjTkORa+/bbH5OvPFrX r/o/mC62mGNeZUrOy1Nc51cllEr8+/pt77yJjy0W3jWx9L6/uXvWa+38KzKnjQV7/z3k+qBS Etj6adqsRMZUmz8ftEWDlViKMxINtZiLihMBqefk2c8DAAA= X-CMS-MailID: 20241223125601eucas1p1d274193122638075dc65310a22616bae X-Msg-Generator: CA X-RootMTR: 20241223125601eucas1p1d274193122638075dc65310a22616bae X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125601eucas1p1d274193122638075dc65310a22616bae References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The T-Head TH1520 SoC’s AP clock controller now needs two address ranges to manage both the Application Processor (AP) and Video Output (VO) subsystem clocks. Update the device tree bindings to require two `reg` entries, one for the AP clocks and one for the VO clocks. Additionally, introduce new VO subsystem clock constants in the header file. These constants will be used by the driver to control VO-related components such as display and graphics units. Signed-off-by: Michal Wilczynski Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/thead,th1520-clk-ap.yaml | 15 +++++++-- .../dt-bindings/clock/thead,th1520-clk-ap.h | 33 +++++++++++++++++++ 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3..f0df97a450ef 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller description: | The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures + the clock gates for the HDMI, MIPI and the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -23,7 +24,13 @@ properties: const: thead,th1520-clk-ap reg: - maxItems: 1 + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: ap-clks + - const: vo-clks clocks: items: @@ -47,7 +54,9 @@ examples: #include clock-controller@ef010000 { compatible = "thead,th1520-clk-ap"; - reg = <0xef010000 0x1000>; + reg = <0xef010000 0x1000>, + <0xff010000 0x1000>; + reg-names = "ap-clks", "vo-clks"; clocks = <&osc>; #clock-cells = <1>; }; diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h index a199784b3512..8b9a98f878a6 100644 --- a/include/dt-bindings/clock/thead,th1520-clk-ap.h +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -93,4 +93,37 @@ #define CLK_SRAM3 83 #define CLK_PLL_GMAC_100M 84 #define CLK_UART_SCLK 85 + +/* VO clocks */ +#define CLK_AXI4_VO_ACLK 86 +#define CLK_GPU_CORE 87 +#define CLK_GPU_CFG_ACLK 88 +#define CLK_DPU_PIXELCLK0 89 +#define CLK_DPU_PIXELCLK1 90 +#define CLK_DPU_HCLK 91 +#define CLK_DPU_ACLK 92 +#define CLK_DPU_CCLK 93 +#define CLK_HDMI_SFR 94 +#define CLK_HDMI_PCLK 95 +#define CLK_HDMI_CEC 96 +#define CLK_MIPI_DSI0_PCLK 97 +#define CLK_MIPI_DSI1_PCLK 98 +#define CLK_MIPI_DSI0_CFG 99 +#define CLK_MIPI_DSI1_CFG 100 +#define CLK_MIPI_DSI0_REFCLK 101 +#define CLK_MIPI_DSI1_REFCLK 102 +#define CLK_HDMI_I2S 103 +#define CLK_X2H_DPU1_ACLK 104 +#define CLK_X2H_DPU_ACLK 105 +#define CLK_AXI4_VO_PCLK 106 +#define CLK_IOPMP_VOSYS_DPU_PCLK 107 +#define CLK_IOPMP_VOSYS_DPU1_PCLK 108 +#define CLK_IOPMP_VOSYS_GPU_PCLK 109 +#define CLK_IOPMP_DPU1_ACLK 110 +#define CLK_IOPMP_DPU_ACLK 111 +#define CLK_IOPMP_GPU_ACLK 112 +#define CLK_MIPIDSI0_PIXCLK 113 +#define CLK_MIPIDSI1_PIXCLK 114 +#define CLK_HDMI_PIXCLK 115 + #endif From patchwork Mon Dec 23 12:55:36 2024 Content-Type: text/plain; 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Mon, 23 Dec 2024 12:56:03 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-63-67695de3732d Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 73.73.19654.3ED59676; Mon, 23 Dec 2024 12:56:03 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125601eusmtip2baa8c26bb05f02aa7809fd2cddbadee5~Tz56pkl5p3253332533eusmtip2X; Mon, 23 Dec 2024 12:56:01 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 02/19] clk: thead: Add clock support for VO subsystem in T-Head TH1520 SoC Date: Mon, 23 Dec 2024 13:55:36 +0100 Message-Id: <20241223125553.3527812-3-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf1CTdRzH+z7Pw/OMXYPHifJFCIQSkAyh8+B7aUkI51NxZ9116nmnMeQB d8HQTaw8TAgYgjPURcT4MSSURUxyjsV2EuecDEKXsJiojDjBFIKQXxp0UIwHy/9e38/7/fm+ P5/vfXm4UE+u4Yklh1mpRJQWRPIJQ9us7bXBveLUiI77waj9dg2Gmv5WUaihxYYhtcXmhvq7 9Rj6dWacRBcf3KLQo5YcAjk0lRTKbWsk0bCqn0QTin43ZDdVkGjqlAUgw1QeibQWJ4UaZ9QY OjfRRKDaZhNA8sILbqjr53jk7G8n0LBdgSO5yhP9c6WZQguOSwQq/7OVQvrRM27Iqt2F8lq/ ImL8mfHefIoZHR4mmGsnpimm5Uk1wRhVTopRGG8ARldfSDJ9jiskU9XxAfPbSSvGXK49zuRp 2zCmeD6CGf+ph2S+1NcDpjv3NvW+cA9/SzKbJj7CSje+lcg/oMw5Cw464j51GH4H2cD4RhFw 50F6EzxZUoEXAT5PSGsAXCh2Ei5BSE8DON0VwglTANY06rBnHaraWyQn1AHYaVID7jAKYKGt DLhcJP06HKhTu7kELzqfgPnXc5ZcOP0QQMNQBelyraT3w1mtcjGQxyPodfDudJYLBfRWqCnc waUFwNarN3EXu9MxsKGod+l+Ab0CdpQNLY2KL3pym8qXdoD0JT5s1n6Pc81xsEd1geB4JRyx 6imO/WCnUrFcz4ADTZPL/ixoVFiXeTPss82Rrnlwej1sNG10IaTfhmVlL3HoAXvHVnATeMCz hlKcKwvgCbmQuyMYlihO/Zdp0xiWn5CBNyqridMgUPXcLqrndlH9H1sN8HrgzWbK0lNZWaSE /SRcJkqXZUpSw/dnpOvA4sfuXLBONoPKkYlwM8B4wAwgDw/yEpiF4lShIFn02VFWmvGRNDON lZmBL48I8hasSw5ghXSq6DD7McseZKXPVIznviYbOyQeXNV9f+SPIfDh9QLP0a1ex4D+Teh9 fq19YlPCL553Cny2x0QQPqpDoWPeVdHBolfqSyxJLwYC3zpwzGPz8LawFLqq7z1Mm/1ttMIW Lzh387sd+9buDmdao7qUcVcnHkRrc3W7Hnk7jZkdSXmrx47uvVc6+HLIEY9Qs/+7nRcfHxds /2Y9XyPfJpjDZy0Rl7XKscjYpz+MJMbuNO0z1k3++FeA/UxbQs7caq/S3edjCzYQ5QNJ81Qw updyTS25u0cQk1DkE5VSs0GT+LTdPxC+s7M3LET+Qnxdlt+rPjM2X/s4lhSq/px4+HhLfIVf Q9WTnju+04Ff6JSnZ+ajV0V9XRxEyA6IIsNwqUz0L4XP8bpHBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xe7qPYzPTDb594bI4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXMblxEmPBNZeKa9ueMTYw7rTqYuTkkBAwkZi15AJbFyMXh5DAUkaJ/ZOO sEAkZCSudb+EsoUl/lzrgip6xSjx9tUFJpAEm4CRxIPl81lBbBGBxSwSe/dVghQxC7xllLg+ cyNYt7BAokTjmx1ANgcHi4CqxK0vNSAmr4C9xIpOf4j58hL7D55lBrE5BRwk1nTdYASxhYBK /p36wAZi8woISpyc+QRsIjNQffPW2cwTGAVmIUnNQpJawMi0ilEktbQ4Nz232EivODG3uDQv XS85P3cTIzC5bDv2c8sOxpWvPuodYmTiYDzEKMHBrCTCe0goM12INyWxsiq1KD++qDQntfgQ oynQ1ROZpUST84HpLa8k3tDMwNTQxMzSwNTSzFhJnJftyvk0IYH0xJLU7NTUgtQimD4mDk6p BqYo/mPCx1d1hFdkfLO54nBtK/epoJbXaXuV7Tb9YLtrVLXi86eYs3dtivf+8tO90PjBiXPW 3YrL3Ex6R20sq7o6F+yyspv43VD/dUKlwfHsk/Ovnbge5euVXDuXdXucpfQ507U3uGxYF/TF rj+xIOZ03qornBzPMrhE5TRVJil9eCPvNq3vw9P/Xyb9kNu/xVq7/PIfkYCUuZrdpzNWJV27 wmPKti7vx0/m2MUFGerr5/RIWqaxbg9ef7BXbw+/INO1LSXLfRob3137ER9xRyGmNciY84NN rxfL9oe9IvkypsuPujRtFhe14E1jyZZ5Nl1I2WVPeDvL8qfOJ+Lsr4rZX/dhOLdyo8qT/57z viqxFGckGmoxFxUnAgCWyKIBtwMAAA== X-CMS-MailID: 20241223125603eucas1p26a140c47956d7901c08cb06e7be744c7 X-Msg-Generator: CA X-RootMTR: 20241223125603eucas1p26a140c47956d7901c08cb06e7be744c7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125603eucas1p26a140c47956d7901c08cb06e7be744c7 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The T-Head TH1520 SoC integrates a variety of clocks for its subsystems, including the Application Processor (AP) and the Video Output (VO) [1]. Up until now, the T-Head clock driver only supported AP clocks. This commit extends the driver to provide clock functionality for the VO subsystem. At this stage, the focus is on implementing the VO clock gates, as these are currently the most relevant and required components for enabling and disabling the VO subsystem functionality. Future enhancements may introduce additional VO-related clocks as necessary. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 160 ++++++++++++++++++++++++++---- 1 file changed, 142 insertions(+), 18 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 17e32ae08720..b3c719d4f4ac 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -840,6 +840,67 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", + video_pll_clk_pd, 0x0, BIT(0), 0); +static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, + 0x0, BIT(3), 0); +static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", + video_pll_clk_pd, 0x0, BIT(4), 0); +static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", + video_pll_clk_pd, 0x0, BIT(5), 0); +static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", + video_pll_clk_pd, 0x0, BIT(6), 0); +static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, + BIT(7), 0); +static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, + BIT(8), 0); +static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0, + BIT(9), 0); +static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_pd, + 0x0, BIT(10), 0); +static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0x0, + BIT(11), 0); +static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_pd, + 0x0, BIT(12), 0); +static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk", + video_pll_clk_pd, 0x0, BIT(13), 0); +static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk", + video_pll_clk_pd, 0x0, BIT(14), 0); +static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk", + video_pll_clk_pd, 0x0, BIT(15), 0); +static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk", + video_pll_clk_pd, 0x0, BIT(16), 0); +static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk", + video_pll_clk_pd, 0x0, BIT(17), 0); +static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk", + video_pll_clk_pd, 0x0, BIT(18), 0); +static CCU_GATE(CLK_HDMI_I2S, hdmi_i2c_clk, "hdmi-i2c-clk", video_pll_clk_pd, + 0x0, BIT(19), 0); +static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk", + video_pll_clk_pd, 0x0, BIT(20), 0); +static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk", + video_pll_clk_pd, 0x0, BIT(21), 0); +static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk", + video_pll_clk_pd, 0x0, BIT(22), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk, + "iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, BIT(23), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk, + "iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, BIT(24), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk, + "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0); +static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk", + video_pll_clk_pd, 0x0, BIT(27), 0); +static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk", + video_pll_clk_pd, 0x0, BIT(28), 0); +static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk", + video_pll_clk_pd, 0x0, BIT(29), 0); +static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk", + video_pll_clk_pd, 0x0, BIT(30), 0); +static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", + video_pll_clk_pd, 0x0, BIT(31), 0); +static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, + 0x4, BIT(0), 0); + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", &gmac_pll_clk.common.hw, 10, 1, 0); @@ -956,7 +1017,40 @@ static struct ccu_common *th1520_gate_clks[] = { &sram3_clk.common, }; -#define NR_CLKS (CLK_UART_SCLK + 1) +static struct ccu_common *th1520_vo_gate_clks[] = { + &axi4_vo_aclk.common, + &gpu_core_clk.common, + &gpu_cfg_aclk.common, + &dpu0_pixelclk.common, + &dpu1_pixelclk.common, + &dpu_hclk.common, + &dpu_aclk.common, + &dpu_cclk.common, + &hdmi_sfr_clk.common, + &hdmi_pclk.common, + &hdmi_cec_clk.common, + &mipi_dsi0_pclk.common, + &mipi_dsi1_pclk.common, + &mipi_dsi0_cfg_clk.common, + &mipi_dsi1_cfg_clk.common, + &mipi_dsi0_refclk.common, + &mipi_dsi1_refclk.common, + &hdmi_i2c_clk.common, + &x2h_dpu1_aclk.common, + &x2h_dpu_aclk.common, + &axi4_vo_pclk.common, + &iopmp_vosys_dpu_pclk.common, + &iopmp_vosys_dpu1_pclk.common, + &iopmp_vosys_gpu_pclk.common, + &iopmp_dpu1_aclk.common, + &iopmp_dpu_aclk.common, + &iopmp_gpu_aclk.common, + &mipi_dsi0_pixclk.common, + &mipi_dsi1_pixclk.common, + &hdmi_pixclk.common +}; + +#define NR_CLKS (CLK_HDMI_PIXCLK + 1) static const struct regmap_config th1520_clk_regmap_config = { .reg_bits = 32, @@ -965,13 +1059,40 @@ static const struct regmap_config th1520_clk_regmap_config = { .fast_io = true, }; +static int th1520_add_gate_clocks(struct device *dev, + struct clk_hw_onecell_data *priv, + struct regmap *map, void __iomem *base, + struct ccu_common **gate_clks, + size_t gate_clks_size) +{ + struct clk_hw *hw; + int i; + + for (i = 0; i < gate_clks_size; i++) { + struct ccu_gate *cg = hw_to_ccu_gate(&gate_clks[i]->hw); + + gate_clks[i]->map = map; + + hw = devm_clk_hw_register_gate_parent_data( + dev, cg->common.hw.init->name, + cg->common.hw.init->parent_data, 0, + base + cg->common.cfg0, ffs(cg->enable) - 1, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->hws[cg->common.clkid] = hw; + } + + return 0; +} + static int th1520_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct clk_hw_onecell_data *priv; - struct regmap *map; - void __iomem *base; + struct regmap *map, *map_vosys; + void __iomem *base, *base_vosys; struct clk_hw *hw; int ret, i; @@ -981,14 +1102,22 @@ static int th1520_clk_probe(struct platform_device *pdev) priv->num = NR_CLKS; - base = devm_platform_ioremap_resource(pdev, 0); + base = devm_platform_ioremap_resource_byname(pdev, "ap-clks"); if (IS_ERR(base)) return PTR_ERR(base); + base_vosys = devm_platform_ioremap_resource_byname(pdev, "vo-clks"); + if (IS_ERR(base_vosys)) + return PTR_ERR(base_vosys); + map = devm_regmap_init_mmio(dev, base, &th1520_clk_regmap_config); if (IS_ERR(map)) return PTR_ERR(map); + map_vosys = devm_regmap_init_mmio(dev, base_vosys, &th1520_clk_regmap_config); + if (IS_ERR(map_vosys)) + return PTR_ERR(map_vosys); + for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) { struct ccu_pll *cp = hw_to_ccu_pll(&th1520_pll_clks[i]->hw); @@ -1033,21 +1162,16 @@ static int th1520_clk_probe(struct platform_device *pdev) priv->hws[cm->common.clkid] = hw; } - for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) { - struct ccu_gate *cg = hw_to_ccu_gate(&th1520_gate_clks[i]->hw); - - th1520_gate_clks[i]->map = map; - - hw = devm_clk_hw_register_gate_parent_data(dev, - cg->common.hw.init->name, - cg->common.hw.init->parent_data, - 0, base + cg->common.cfg0, - ffs(cg->enable) - 1, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); + ret = th1520_add_gate_clocks(dev, priv, map, base, th1520_gate_clks, + ARRAY_SIZE(th1520_gate_clks)); + if (ret) + return ret; - priv->hws[cg->common.clkid] = hw; - } + ret = th1520_add_gate_clocks(dev, priv, map_vosys, base_vosys, + th1520_vo_gate_clks, + ARRAY_SIZE(th1520_vo_gate_clks)); + if (ret) + return ret; ret = devm_clk_hw_register(dev, &osc12m_clk.hw); if (ret) From patchwork Mon Dec 23 12:55:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918794 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C18C01ABEC6 for ; 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Mon, 23 Dec 2024 12:56:03 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 03/19] dt-bindings: power: thead,th1520: Add support for power domains Date: Mon, 23 Dec 2024 13:55:37 +0100 Message-Id: <20241223125553.3527812-4-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SfUxTVxzdfe/1vdKt+Cxs3gDRDeecLICoZJdBmFtm8qbZAovZR7NNOvpW Kp9pQWUhmXwqXRFlOGJhIsxIg1CwK7VtYMTyURDWqBVomK2Y4bo2bIwvI6h11Ieb/53f75xz z/kll4+LTGQYX56TzypyJFmRpIAwDi7bo+9+IZdtb+4j0dBEM4a6Hmgo1NZjx1Bjv52H3DcM GLq5NEsi3d1rFPqzp5hA49ofKVQ62EEir8ZNojm1m4cclgYSLVT1A2RcKCNRe7+LQh1LjRhq musi0HmTBaCKygs8dP3qHuRyDxHI61DjqEKzDj3uNlHIP36JQPV/91LIMHOKh2ztn6Cy3lpi 90Zm1llOMTNeL8H0HV+kmJ575wjGrHFRjNo8Chh9ayXJ3BrvJpmzw6nM7e9sGPPz+W+ZsvZB jKl+tJ2Z/WWMZE4YWgFzo3SCShGJBUlSNkt+iFXEJqcJMn5frAR5J8KP6Fwe8igwvKQCQXxI 74JT9UOECgj4IloL4AW9BeOGRQB9nnqcGxYA7KvtJp9arKXFgCNaALTrTSQ3zKz6vXNYQEXS O+BUSyMvQITS5QQsH+AsOO0B0Djd8OStEPoAbCmp5gUwQW+BF68PgwAW0m/DPu0YweVtgr1X fsUDOIjeDdtUzjXNejh8ZvqJBl/VlHZxZSHdLoBDj8cBZ34PdlaVYBwOgT6bgeJwBBz5Xr0W kAunuuZxDhdBs9q2hhPhLfvKalH+asA22GGJ5dbvQIN3nhdYQzoYOv9az1UIhjXGOpxbC+Hx ChGnfg2eVlf9F2rXGtfKMPAP6ylwEryieeYYzTPHaP7PPQfwVrCBLVBmy1jlzhz2cIxSkq0s yJHFpOdm68Hq5x7x25ZMQOubi7ECjA+sAPLxyFChVSSXiYRSSeE3rCL3gKIgi1VaQTifiNwg 3CLdxIpomSSfzWTZPFbxlMX4QWFHsRdGkq89tyv69rYxNDf9k1tnzojxhPCEkwffKCmVT9yp M2fWRH1+JPeyW8W0ddXG7XSMXTYXyRx+nTYi9R8y5dVEP5U+U3gx6krh4YMf3fe8LN3xoX5d y/5J99AdeUmOwscrjkjYu5W5lNysHXW8u29MtSxjV+YjBuItsO5hTfU0m7l4L7Ty7KDVmbjS ejpNbHjfcjPtRemAzPtb7KGvpPs/fdM9f9WftfXBVNJSZ34CVv3lZ31FcfF1Tv+kOP4t2wdG 10RjZlNa9KM88cmwj9NpbG/76OaGznpBSpPkdfjDQJl+Uu8Tb3yYgILreE5dXuro8vh00vOJ m4vCjx0j738dSSgzJHFRuEIp+RcfsFGcSwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7pPYjPTDTpvK1mcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLePylk7GgT7pi3d3nbA2MW8S6GDk5JARMJA41NzJ2MXJxCAksZZS4Ov8K E0RCRuJa90sWCFtY4s+1LjaIoleMEjdmdDKCJNgEjCQeLJ/PCmKLCCxmkdi7rxKkiFngLaPE 9ZkbwbqFBWIl/u88wAZiswioSqy+eBKsmVfAXuLwiqtQG+Ql9h88ywxicwo4SKzpugFWIwRU 8+/UBzaIekGJkzOfgNUzA9U3b53NPIFRYBaS1CwkqQWMTKsYRVJLi3PTc4uN9IoTc4tL89L1 kvNzNzECE8y2Yz+37GBc+eqj3iFGJg7GQ4wSHMxKIryHhDLThXhTEiurUovy44tKc1KLDzGa At09kVlKNDkfmOLySuINzQxMDU3MLA1MLc2MlcR52a6cTxMSSE8sSc1OTS1ILYLpY+LglGpg WtT74+3DyzavC9+FnM3Y2Fx8yW26I+tOtbV9C1TPCO5YvVEy4PJ5xma3F+LKa288jPCRCZ/x K27Lidkpd/7sWcmwdO2yXO8Hz5ryntvtY7K24fNg0tea66JcvSKimVvXtC18vvX/d/dEl6+y 2tiZND3jw5PMLL2TdnFyu26GBh/6tPRWTmXU6z++sZn8D7L3LrrPfaxy+pv7Jkb+h1tiFKcc kGPa753CubrX7qRxocj5fb4ft3ZL/Hv7U3ptsGP73ucPnmRW5y04f/mv3WLW45n7r4RejdDn lxC86Mxct7v4z0fuNJW2M7sZc+oMU89vb/pQvcX1XE2DLC9bbvcMF+8g08/rtuzYuFajhcGD TYmlOCPRUIu5qDgRAH3Joda5AwAA X-CMS-MailID: 20241223125604eucas1p26b870756eeaf2a5666b70de3f7554c13 X-Msg-Generator: CA X-RootMTR: 20241223125604eucas1p26b870756eeaf2a5666b70de3f7554c13 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125604eucas1p26b870756eeaf2a5666b70de3f7554c13 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Introduce a device tree binding for the T-HEAD TH1520 power domain controller. This allows devices to specify their power domain dependencies, thereby improving power management for subsystems such as the GPU. The new YAML schema describes the power domain node for the T-HEAD TH1520 SoC. Signed-off-by: Michal Wilczynski --- .../bindings/power/thead,th1520-power.yaml | 42 +++++++++++++++++++ MAINTAINERS | 1 + .../dt-bindings/power/thead,th1520-power.h | 18 ++++++++ 3 files changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/thead,th1520-power.yaml create mode 100644 include/dt-bindings/power/thead,th1520-power.h diff --git a/Documentation/devicetree/bindings/power/thead,th1520-power.yaml b/Documentation/devicetree/bindings/power/thead,th1520-power.yaml new file mode 100644 index 000000000000..28ff86f2cb05 --- /dev/null +++ b/Documentation/devicetree/bindings/power/thead,th1520-power.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/thead,th1520-power.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 Power Domain + +description: | + The T-HEAD TH1520 SoC includes a power domain controller responsible for + managing the power states of various hardware domains such as the GPU. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + const: thead,th1520-pd + + "#power-domain-cells": + const: 1 + +additionalProperties: false + +required: + - compatible + - "#power-domain-cells" + +examples: + - | + firmware { + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + + pd: power-domain { + compatible = "thead,th1520-pd"; + #power-domain-cells = <1>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 910305c11e8a..c0e9639ac210 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20192,6 +20192,7 @@ F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml +F: Documentation/devicetree/bindings/power/thead,th1520-power.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: drivers/mailbox/mailbox-th1520.c diff --git a/include/dt-bindings/power/thead,th1520-power.h b/include/dt-bindings/power/thead,th1520-power.h new file mode 100644 index 000000000000..45835f25010d --- /dev/null +++ b/include/dt-bindings/power/thead,th1520-power.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef __DT_BINDINGS_POWER_TH1520_H +#define __DT_BINDINGS_POWER_TH1520_H + +#define TH1520_AON_VDEC_PD 1 +#define TH1520_AON_NPU_PD 2 +#define TH1520_AON_VENC_PD 3 +#define TH1520_AON_GPU_PD 4 +#define TH1520_AON_DSP0_PD 5 +#define TH1520_AON_DSP1_PD 6 + +#endif From patchwork Mon Dec 23 12:55:38 2024 Content-Type: text/plain; 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Mon, 23 Dec 2024 12:56:06 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-c5-67695de685ba Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 38.73.19654.5ED59676; Mon, 23 Dec 2024 12:56:05 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125604eusmtip2399344dbdd237bafb93583527f56654c~Tz59OUaFT1804418044eusmtip2R; Mon, 23 Dec 2024 12:56:04 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 04/19] dt-bindings: firmware: thead,th1520: Add support for firmware node Date: Mon, 23 Dec 2024 13:55:38 +0100 Message-Id: <20241223125553.3527812-5-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sa0xTZxjmO+f0nLah7FjI+MIWRBy6S4ZC/PGZza0Mxs6SuWjMpjNOV8YR CbeuBcaIRpBLoFaYTEdoUXBjXEqRKG0D1YItjAIq46LAhBbZ1AnWcZUxZ9lsT7f57/ne53nf 53nffHxcbCCD+Imp6aw8VZocSgoJY/ef/a/f+zQxYfM9TSjqGf0OQ4a/1BTSmfsxVNXVz0OO IT2GbjyaJdH5uwMUum/OJdBI/RkK5XU3k2ha7SDRvMrBQ8OmShItnugCyLiYT6KmLjuFmh9V YejcvIFANa0mgAqLa3losO9dZHf0EGh6WIWjQvVz6O/LrRRaHblAIM3vHRTSO0/ykK1pN8rv OEVIgpnZsQKKcU5PE0xn0RLFmJerCaZNbacYVds1wFzUFpPMxMhlkjnbu5OZPG7DmJaao0x+ UzfGlLo2M7PtN0mmRK8FzFDeKLVDvFf4ZjybnJjJyje99Znw0OnBTkxmhFmV89UgB/T5KwGf D+kt8Ho9UAIhX0zXA5hTbMe4xxKA41OFXmYRwKKFckIJBJ6OFV0X6cZiug7AXy3JnMgJYP6p KY+IpCPh7boqnpsIoAsIWPBjrmcUTv8GoPFOpafdn46DFlcD4Q5C0GFwzhriLovot2FzawPg 3NbCDst13I0FtATqlGOA06yBvRV3PGb4U02eQYO750O6QQgnlye8zTFwVFWKcdgfztj0FIdf hFe/UXnXSYO3DQs4hw/DNpXNi9+AE/2PSXc2nH4FNps2ceUouGo6hnG384NjD9dwEfxgmbEc 58oiWFQo5tQb4GnVif9M++uN3jAMdJmc+NdgnfqZZdTPLKP+37ca4FoQyGYoUhJYRWQq+2W4 QpqiyEhNCP88LeUiePqzr67allpB3cx8uBVgfGAFkI+HBois4sQEsShe+lU2K087IM9IZhVW 8AKfCA0UhcWvZcV0gjSdTWJZGSv/l8X4gqAc7HtR/Gx25DH6QlzJteEQycjUesx3cPmT4MmV kQ9e+lD7cLxFz9P4+HS7jktNHY2ydxYUjUk73pux+pllQeO8gNRdMcaY6LuuAwLrvufTjSXB Tz7ec4u3kFse7jtmyRo8su/gL5JOsSbW9yfT+Lfbbq1Mxn2htZTJP4oz/HB0dmvYwKWTEVf2 yiJ2wv3jkdt8/tCZJO1zTQ51hU66cXdIfeBcFHlEubQ9nTkbXVNoe3xYEJW5XW9u2VUu7D3o jJ/OXL81K3bgwf3SWlVjsDDRFJu9euPnda6MK9qbFUFJC9HyBy/vL4ldfq3HMLTBvvH8+0V7 qLw+oj1py0yt9knZpbSW6NxQQnFIGvEqLldI/wH9qAJLSAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xe7rPYjPTDdYbW5y4vojJYuvvWewW a/aeY7KYf+Qcq8W9S1uYLK58fc9mse7pBXaLF3sbWSyurZjLbtF8bD2bxctZ99gsPvbcY7W4 vGsOm8Xn3iOMFts+t7BZrD1yl91i/df5TBYLP25lsViyYxejRVvnMlaLi6dcLe7eO8Fi8fJy D7NF2yx+i/97drBb/Lu2kcVi9rv97BZb3kxktTi+NtyiZf8UFgc5j/c3Wtk93rx8yeJxuOML u8febwtYPHbOusvu0bPzDKPHplWdbB53ru1h85h3MtDjfvdxJo/NS+o9WtYeY/Lo/2vg8X7f VTaPvi2rGD0uNV9nDxCK0rMpyi8tSVXIyC8usVWKNrQw0jO0tNAzMrHUMzQ2j7UyMlXSt7NJ Sc3JLEst0rdL0MuYevEwU8E2iYo5HxcwNjCeEu5i5OSQEDCR+LHmCFsXIxeHkMBSRon/3+4y QSRkJK51v2SBsIUl/lzrgip6xSixu7sDrIhNwEjiwfL5rCC2iMBiFom9+ypBipgF3jJKXJ+5 EaxbWCBBYnLjMyCbg4NFQFXiwyEFkDCvgL3E+h0rGSEWyEvsP3iWGcTmFHCQWNN1AywuBFTz 79QHNoh6QYmTM5+AjWQGqm/eOpt5AqPALCSpWUhSCxiZVjGKpJYW56bnFhvpFSfmFpfmpesl 5+duYgQml23Hfm7Zwbjy1Ue9Q4xMHIyHGCU4mJVEeA8JZaYL8aYkVlalFuXHF5XmpBYfYjQF Onsis5Rocj4wveWVxBuaGZgamphZGphamhkrifOyXTmfJiSQnliSmp2aWpBaBNPHxMEp1cA0 9ctxV9/vBdE2q91ZtJza/xgHr/x5brb4GWt1w8mL/z9gSRKqWa3RpHLmHHNA6LSZM5tMRA7v CY2ezRmySPSNqLG/auY05o4jXB6ncuZyTuZ8JrFiZuJ933n1Rkuy1T+aSr0uCv154Gzt1NTa hsrWpKU8M2c7b7hVy2r5amXTKtZzqztqE87v+3rpSYNoAU/EhhyrB3X8P5i9/Hpfe1yWfKF4 OMI4TWTbTdmW1JXOq5+1Xt13Yo/yhiD73K4Vxzd9l/fjcCqSeyCXvDNG3ajCpXRJT/3rAAlN pbISmXa9lcq3q57yeF9vTnUNb4gQnn6oKb3Lbk+KyYcHAR+vVmlfCwn1jT7CZmL+70lyuRJL cUaioRZzUXEiAIXen9a3AwAA X-CMS-MailID: 20241223125606eucas1p10ca3adc99322ff33d617a227733e5e67 X-Msg-Generator: CA X-RootMTR: 20241223125606eucas1p10ca3adc99322ff33d617a227733e5e67 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125606eucas1p10ca3adc99322ff33d617a227733e5e67 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The kernel communicates with the E902 core through the mailbox transport using AON firmware protocol. Add dt-bindings to document it the dt node. Signed-off-by: Michal Wilczynski --- .../bindings/firmware/thead,th1520-aon.yaml | 59 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml new file mode 100644 index 000000000000..ca4c276766a3 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AON (Always-On) Firmware Node + +description: | + The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing + low-power states, system wakeup events, and power management tasks. It is + designed to operate independently in a dedicated power domain, allowing it to + remain functional even during the SoC's deep sleep states. + + At the heart of the AON subsystem is the E902, a low-power core that executes + firmware responsible for coordinating tasks such as power domain control, + clock management, and system wakeup signaling. Communication between the main + SoC and the AON subsystem is handled through a mailbox interface, which + enables message-based interactions with the AON firmware. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + const: thead,th1520-aon + + mboxes: + maxItems: 1 + + mbox-names: + items: + - const: aon + + power-domain: + $ref: /schemas/power/thead,th1520-power.yaml# + description: Subnode representing the hardware power domain of the AON subsystem. + +additionalProperties: false + +required: + - compatible + - mboxes + - mbox-names + +examples: + - | + firmware { + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + + pd: power-domain { + compatible = "thead,th1520-pd"; + #power-domain-cells = <1>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c0e9639ac210..7705d1b6dd7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20188,6 +20188,7 @@ M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git +F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml From patchwork Mon Dec 23 12:55:39 2024 Content-Type: text/plain; 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Mon, 23 Dec 2024 12:56:07 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-c9-67695de75d46 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id BA.73.19654.7ED59676; Mon, 23 Dec 2024 12:56:07 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125606eusmtip265edc2547cb1cf3b132893f73b1a75dd~Tz5_j6kA-2641026410eusmtip2l; Mon, 23 Dec 2024 12:56:05 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 05/19] firmware: thead: Add AON firmware protocol driver Date: Mon, 23 Dec 2024 13:55:39 +0100 Message-Id: <20241223125553.3527812-6-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se1BUVRzH59x7uXdZW7guKAeiMAqbnGlF0+aMEVGEnalmyiat0QK2uC0g D91lFRoKGB4iLiBBmgvGa0ceQYzEbrCJG8+FFChIlgyQJmiB2XgjDxFjuVv53/f7+31+8/v+ zhwBKdbRboKwqBhOHiWN8KSFlK59pftZ84dhMu+sM/tQh6mEQNp7agZVNXYTqLC12w4N99YR 6NfFaRp9O/Yzg8YbkyjUX36ZQcntNTSaUA/TaFY1bIf69AU0ms9sBUg3n0Kj6tYhBtUsFhKo eFZLIU29HqC0s1fs0C8/BaCh4Q4KTfSpSJSmdkQPrtUzaL3/KoXypwwMqrPk2CFj9XsoxZBH +T2OpwdSGWyZmKBwS/oCgxvvFlG4QT3EYFXDTYBrK8/SeLD/Go2/7jyE75wzEvg7TQJOqW4n cPZ9bzx9/RaNs+oqAe5NNjFvi48KfUK4iLBTnHy3b7AwdLFBw5zoSAaxN78yg0Sg+yQDCASQ 3QdbiuIzgFAgZssBVP0xQvBmAUDD+CrDm3kAyy9oN4z95sTUObOtUQZgT64F8MYCoL4mg7JS NLsXjpQV2lkbzmwqBVPbkjYpkjUDqBstoK2UE3sIfl9RvTlBsV5QP7dOWVOJ2Jdg2cxJfp0H NDR1kVZtz/rBqowBYNUidivsvDS6OUpuMMnafJLntUI41fMBr1+FjWvrtroTnDTW2U5whzdy VRSvo+GIds7GxMMGldGmX4CD3au0NQ7JPgNr9Lv58stwcKAL8G/nAAf+3soncIBf6C6SfFkE 09PEPL0TfqnK/G9pd7mO4DWG93pXwHnwhPqhW9QP3aL+f28RICuBC6dURMo4xd4o7rREIY1U KKNkko+jI2vBxte+sW5cqAdlk7OSZkAIQDOAAtLTWdQsDpOJRSHSuE85eXSQXBnBKZrBowLK 00XkFeLBiVmZNIY7znEnOPm/XUJg75ZIVEOXtdcjsuGpLbmupUfxndSkBE3ceZOPAW2/vsU9 zvGYQ9tKyyu329md+4V/rSljDouX9mjrA/NP5okNQbcf+Jv9l++GKKWlxeWSDNHCsVx63vW5 g3G+vrcOjO1Qxp3J0fY53i89fCTep3ZpbjjfYZvlqbzwCsm2wKofHsk/Eh4if6vx3U52qa2p k/P88UpPrOs3xZWm0fROtTHRFEtsX90/MX4xuiT1wFy430xAVoDX5PH+meBM/OIbml05Th6/ Bz32p2756WZCro/1fucz82rZZbeEAI+ZNyV5Xb/RpTiwwNm9x9/p84/Ul4KyD5orntecHpsu eTK07v2rwUTTa8sX2h09KUWodM8uUq6Q/gN60vwcSQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7rPYzPTDT4cErI4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX8XXnEvaCE82MFWdmPGdsYNyW1sXIySEhYCLxrvs5excjF4eQwFJGie7W iywQCRmJa90voWxhiT/Xutggil4xSmxav5YdJMEmYCTxYPl8VhBbRGAxi8TefZUgRcwCbxkl rs/cCNYtLOAvsW7GQbAiFgFViV2f/gHFOTh4Bewlln8ohFggL7H/4FlmEJtTwEFiTdcNRhBb CKjk36kPbCA2r4CgxMmZT8BGMgPVN2+dzTyBUWAWktQsJKkFjEyrGEVSS4tz03OLjfSKE3OL S/PS9ZLzczcxAhPMtmM/t+xgXPnqo94hRiYOxkOMEhzMSiK8h4Qy04V4UxIrq1KL8uOLSnNS iw8xmgKdPZFZSjQ5H5ji8kriDc0MTA1NzCwNTC3NjJXEedmunE8TEkhPLEnNTk0tSC2C6WPi 4JRqYHJPWyUSmd/ho3m5SdfGnHsq10/lB3dy396+Yu35RL4qfpeV05EVU3pmm+wQCvx9qjz6 Us8Ev8BJAf2C7CtmFqX+zFXriVsTualgueqPD7Kbqr6ax1y6sYljR1MF1+O2EyX37CcmWK7O vTLzo45IBHuw9iMNW7vcqTNjLJxl730RSZk8T83j4vFXyR3Zb5mnrL559cn5KWF3+Bg1n3Ry Tb1UO+/n5d7vgt1q/StK9OWcBb4vTVrIFjd3BYfexg/Pbuw78qDX//6rZ9xS/A1RV22OOzzX XHTmpZBLt+f8sqvbpZm33q389a7v0/9NHKkKuhf75zotii/odpj56NDVv9zzl606+XTyrslX NoWxSDYqsRRnJBpqMRcVJwIAHwcVG7kDAAA= X-CMS-MailID: 20241223125607eucas1p1eac1c05d699337f9af118c1885b14b1d X-Msg-Generator: CA X-RootMTR: 20241223125607eucas1p1eac1c05d699337f9af118c1885b14b1d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125607eucas1p1eac1c05d699337f9af118c1885b14b1d References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The T-Head TH1520 SoC uses an E902 co-processor running Always-On (AON) firmware to manage power, clock, and other system resources [1]. This patch introduces a driver implementing the AON firmware protocol, allowing the Linux kernel to communicate with the firmware via mailbox channels. Through an RPC-based interface, the kernel can initiate power state transitions, update resource configurations, and perform other AON-related tasks. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 2 + drivers/firmware/Kconfig | 9 + drivers/firmware/Makefile | 1 + drivers/firmware/thead,th1520-aon.c | 203 ++++++++++++++++++ .../linux/firmware/thead/thead,th1520-aon.h | 186 ++++++++++++++++ 5 files changed, 401 insertions(+) create mode 100644 drivers/firmware/thead,th1520-aon.c create mode 100644 include/linux/firmware/thead/thead,th1520-aon.h diff --git a/MAINTAINERS b/MAINTAINERS index 7705d1b6dd7a..42aef66bd257 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20196,10 +20196,12 @@ F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: Documentation/devicetree/bindings/power/thead,th1520-power.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/firmware/thead,th1520-aon.c F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h +F: include/linux/firmware/thead/thead,th1520-aon.h RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 71d8b26c4103..e08e01de3ee3 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -212,6 +212,15 @@ config SYSFB_SIMPLEFB If unsure, say Y. +config TH1520_AON_PROTOCOL + tristate "Always-On firmware protocol" + depends on THEAD_TH1520_MBOX + help + Power, clock, and resource management capabilities on the TH1520 SoC are + managed by the E902 core. Firmware running on this core communicates with + the kernel through the Always-On protocol, using hardware mailbox as a medium. + Say yes if you need such capabilities. + config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on TI_MESSAGE_MANAGER diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 7a8d486e718f..5db9c042430c 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o obj-$(CONFIG_SYSFB) += sysfb.o obj-$(CONFIG_SYSFB_SIMPLEFB) += sysfb_simplefb.o +obj-$(CONFIG_TH1520_AON_PROTOCOL) += thead,th1520-aon.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/thead,th1520-aon.c b/drivers/firmware/thead,th1520-aon.c new file mode 100644 index 000000000000..82198bcfc3a8 --- /dev/null +++ b/drivers/firmware/thead,th1520-aon.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include +#include +#include + +#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) +#define MAX_TX_TIMEOUT 500 + +struct th1520_aon_chan { + struct mbox_chan *ch; + struct th1520_aon_rpc_ack_common ack_msg; + struct mbox_client cl; + struct completion done; + + /* make sure only one RPC is perfomed at a time */ + struct mutex transaction_lock; +}; + +struct th1520_aon_msg_req_set_resource_power_mode { + struct th1520_aon_rpc_msg_hdr hdr; + u16 resource; + u16 mode; + u16 reserved[10]; +} __packed __aligned(1); + +/* + * This type is used to indicate error response for most functions. + */ +enum th1520_aon_error_codes { + LIGHT_AON_ERR_NONE = 0, /* Success */ + LIGHT_AON_ERR_VERSION = 1, /* Incompatible API version */ + LIGHT_AON_ERR_CONFIG = 2, /* Configuration error */ + LIGHT_AON_ERR_PARM = 3, /* Bad parameter */ + LIGHT_AON_ERR_NOACCESS = 4, /* Permission error (no access) */ + LIGHT_AON_ERR_LOCKED = 5, /* Permission error (locked) */ + LIGHT_AON_ERR_UNAVAILABLE = 6, /* Unavailable (out of resources) */ + LIGHT_AON_ERR_NOTFOUND = 7, /* Not found */ + LIGHT_AON_ERR_NOPOWER = 8, /* No power */ + LIGHT_AON_ERR_IPC = 9, /* Generic IPC error */ + LIGHT_AON_ERR_BUSY = 10, /* Resource is currently busy/active */ + LIGHT_AON_ERR_FAIL = 11, /* General I/O failure */ + LIGHT_AON_ERR_LAST +}; + +static int th1520_aon_linux_errmap[LIGHT_AON_ERR_LAST] = { + 0, /* LIGHT_AON_ERR_NONE */ + -EINVAL, /* LIGHT_AON_ERR_VERSION */ + -EINVAL, /* LIGHT_AON_ERR_CONFIG */ + -EINVAL, /* LIGHT_AON_ERR_PARM */ + -EACCES, /* LIGHT_AON_ERR_NOACCESS */ + -EACCES, /* LIGHT_AON_ERR_LOCKED */ + -ERANGE, /* LIGHT_AON_ERR_UNAVAILABLE */ + -EEXIST, /* LIGHT_AON_ERR_NOTFOUND */ + -EPERM, /* LIGHT_AON_ERR_NOPOWER */ + -EPIPE, /* LIGHT_AON_ERR_IPC */ + -EBUSY, /* LIGHT_AON_ERR_BUSY */ + -EIO, /* LIGHT_AON_ERR_FAIL */ +}; + +static inline int th1520_aon_to_linux_errno(int errno) +{ + if (errno >= LIGHT_AON_ERR_NONE && errno < LIGHT_AON_ERR_LAST) + return th1520_aon_linux_errmap[errno]; + + return -EIO; +} + +static void th1520_aon_rx_callback(struct mbox_client *c, void *rx_msg) +{ + struct th1520_aon_chan *aon_chan = + container_of(c, struct th1520_aon_chan, cl); + struct th1520_aon_rpc_msg_hdr *hdr = + (struct th1520_aon_rpc_msg_hdr *)rx_msg; + u8 recv_size = sizeof(struct th1520_aon_rpc_msg_hdr) + hdr->size; + + if (recv_size != sizeof(struct th1520_aon_rpc_ack_common)) { + dev_err(c->dev, "Invalid ack size, not completing\n"); + return; + } + + memcpy(&aon_chan->ack_msg, rx_msg, recv_size); + complete(&aon_chan->done); +} + +int th1520_aon_call_rpc(struct th1520_aon_chan *aon_chan, void *msg) +{ + struct th1520_aon_rpc_msg_hdr *hdr = msg; + int ret; + + mutex_lock(&aon_chan->transaction_lock); + reinit_completion(&aon_chan->done); + + RPC_SET_VER(hdr, TH1520_AON_RPC_VERSION); + RPC_SET_SVC_ID(hdr, hdr->svc); + RPC_SET_SVC_FLAG_MSG_TYPE(hdr, RPC_SVC_MSG_TYPE_DATA); + RPC_SET_SVC_FLAG_ACK_TYPE(hdr, RPC_SVC_MSG_NEED_ACK); + + ret = mbox_send_message(aon_chan->ch, msg); + if (ret < 0) { + dev_err(aon_chan->cl.dev, "RPC send msg failed: %d\n", ret); + goto out; + } + + if (!wait_for_completion_timeout(&aon_chan->done, MAX_RX_TIMEOUT)) { + dev_err(aon_chan->cl.dev, "RPC send msg timeout\n"); + mutex_unlock(&aon_chan->transaction_lock); + return -ETIMEDOUT; + } + + ret = aon_chan->ack_msg.err_code; + +out: + mutex_unlock(&aon_chan->transaction_lock); + + return th1520_aon_to_linux_errno(ret); +} +EXPORT_SYMBOL_GPL(th1520_aon_call_rpc); + +int th1520_aon_power_update(struct th1520_aon_chan *aon_chan, u16 rsrc, + bool power_on) +{ + struct th1520_aon_msg_req_set_resource_power_mode msg = {}; + struct th1520_aon_rpc_msg_hdr *hdr = &msg.hdr; + int ret; + + hdr->svc = TH1520_AON_RPC_SVC_PM; + hdr->func = TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE; + hdr->size = TH1520_AON_RPC_MSG_NUM; + + RPC_SET_BE16(&msg.resource, 0, rsrc); + RPC_SET_BE16(&msg.resource, 2, + (power_on ? TH1520_AON_PM_PW_MODE_ON : + TH1520_AON_PM_PW_MODE_OFF)); + + ret = th1520_aon_call_rpc(aon_chan, &msg); + if (ret) + dev_err(aon_chan->cl.dev, "failed to power %s resource %d ret %d\n", + power_on ? "up" : "off", rsrc, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(th1520_aon_power_update); + +static int th1520_aon_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct th1520_aon_chan *aon_chan; + struct mbox_client *cl; + int ret; + + aon_chan = devm_kzalloc(dev, sizeof(*aon_chan), GFP_KERNEL); + if (!aon_chan) + return -ENOMEM; + + cl = &aon_chan->cl; + cl->dev = dev; + cl->tx_block = true; + cl->tx_tout = MAX_TX_TIMEOUT; + cl->rx_callback = th1520_aon_rx_callback; + + aon_chan->ch = mbox_request_channel_byname(cl, "aon"); + if (IS_ERR(aon_chan->ch)) { + ret = PTR_ERR(aon_chan->ch); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request aon mbox chan ret %d\n", + ret); + return ret; + } + + mutex_init(&aon_chan->transaction_lock); + init_completion(&aon_chan->done); + + platform_set_drvdata(pdev, aon_chan); + + return devm_of_platform_populate(dev); +} + +static const struct of_device_id th1520_aon_match[] = { + { .compatible = "thead,th1520-aon" }, + { /* Sentinel */ } +}; + +static struct platform_driver th1520_aon_driver = { + .driver = { + .name = "th1520-aon", + .of_match_table = th1520_aon_match, + }, + .probe = th1520_aon_probe, +}; +module_platform_driver(th1520_aon_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 Always-On firmware driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/firmware/thead/thead,th1520-aon.h b/include/linux/firmware/thead/thead,th1520-aon.h new file mode 100644 index 000000000000..3daa17c01d17 --- /dev/null +++ b/include/linux/firmware/thead/thead,th1520-aon.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#ifndef _THEAD_AON_H +#define _THEAD_AON_H + +#include +#include + +#define AON_RPC_MSG_MAGIC (0xef) +#define TH1520_AON_RPC_VERSION 2 +#define TH1520_AON_RPC_MSG_NUM 7 + +extern struct th1520_aon_chan *aon_chan; + +enum th1520_aon_rpc_svc { + TH1520_AON_RPC_SVC_UNKNOWN = 0, + TH1520_AON_RPC_SVC_PM = 1, + TH1520_AON_RPC_SVC_MISC = 2, + TH1520_AON_RPC_SVC_AVFS = 3, + TH1520_AON_RPC_SVC_SYS = 4, + TH1520_AON_RPC_SVC_WDG = 5, + TH1520_AON_RPC_SVC_LPM = 6, + TH1520_AON_RPC_SVC_MAX = 0x3F, +}; + +enum th1520_aon_misc_func { + TH1520_AON_MISC_FUNC_UNKNOWN = 0, + TH1520_AON_MISC_FUNC_SET_CONTROL = 1, + TH1520_AON_MISC_FUNC_GET_CONTROL = 2, + TH1520_AON_MISC_FUNC_REGDUMP_CFG = 3, +}; + +enum th1520_aon_wdg_func { + TH1520_AON_WDG_FUNC_UNKNOWN = 0, + TH1520_AON_WDG_FUNC_START = 1, + TH1520_AON_WDG_FUNC_STOP = 2, + TH1520_AON_WDG_FUNC_PING = 3, + TH1520_AON_WDG_FUNC_TIMEOUTSET = 4, + TH1520_AON_WDG_FUNC_RESTART = 5, + TH1520_AON_WDG_FUNC_GET_STATE = 6, + TH1520_AON_WDG_FUNC_POWER_OFF = 7, + TH1520_AON_WDG_FUNC_AON_WDT_ON = 8, + TH1520_AON_WDG_FUNC_AON_WDT_OFF = 9, +}; + +enum th1520_aon_sys_func { + TH1520_AON_SYS_FUNC_UNKNOWN = 0, + TH1520_AON_SYS_FUNC_AON_RESERVE_MEM = 1, +}; + +enum th1520_aon_lpm_func { + TH1520_AON_LPM_FUNC_UNKNOWN = 0, + TH1520_AON_LPM_FUNC_REQUIRE_STR = 1, + TH1520_AON_LPM_FUNC_RESUME_STR = 2, + TH1520_AON_LPM_FUNC_REQUIRE_STD = 3, + TH1520_AON_LPM_FUNC_CPUHP = 4, + TH1520_AON_LPM_FUNC_REGDUMP_CFG = 5, +}; + +enum th1520_aon_pm_func { + TH1520_AON_PM_FUNC_UNKNOWN = 0, + TH1520_AON_PM_FUNC_SET_RESOURCE_REGULATOR = 1, + TH1520_AON_PM_FUNC_GET_RESOURCE_REGULATOR = 2, + TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE = 3, + TH1520_AON_PM_FUNC_PWR_SET = 4, + TH1520_AON_PM_FUNC_PWR_GET = 5, + TH1520_AON_PM_FUNC_CHECK_FAULT = 6, + TH1520_AON_PM_FUNC_GET_TEMPERATURE = 7, +}; + +struct th1520_aon_rpc_msg_hdr { + u8 ver; /* version of msg hdr */ + u8 size; /* msg size ,uinit in bytes,the size includes rpc msg header self */ + u8 svc; /* rpc main service id */ + u8 func; /* rpc sub func id of specific service, sent by caller */ +} __packed __aligned(1); + +struct th1520_aon_rpc_ack_common { + struct th1520_aon_rpc_msg_hdr hdr; + u8 err_code; +} __packed __aligned(1); + +#define RPC_SVC_MSG_TYPE_DATA 0 +#define RPC_SVC_MSG_TYPE_ACK 1 +#define RPC_SVC_MSG_NEED_ACK 0 +#define RPC_SVC_MSG_NO_NEED_ACK 1 + +#define RPC_GET_VER(MESG) ((MESG)->ver) +#define RPC_SET_VER(MESG, VER) ((MESG)->ver = (VER)) +#define RPC_GET_SVC_ID(MESG) ((MESG)->svc & 0x3F) +#define RPC_SET_SVC_ID(MESG, ID) ((MESG)->svc |= 0x3F & (ID)) +#define RPC_GET_SVC_FLAG_MSG_TYPE(MESG) (((MESG)->svc & 0x80) >> 7) +#define RPC_SET_SVC_FLAG_MSG_TYPE(MESG, TYPE) ((MESG)->svc |= (TYPE) << 7) +#define RPC_GET_SVC_FLAG_ACK_TYPE(MESG) (((MESG)->svc & 0x40) >> 6) +#define RPC_SET_SVC_FLAG_ACK_TYPE(MESG, ACK) ((MESG)->svc |= (ACK) << 6) + +#define RPC_SET_BE64(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + u64 _set_data = (SET_DATA); \ + data[_offset + 7] = _set_data & 0xFF; \ + data[_offset + 6] = (_set_data & 0xFF00) >> 8; \ + data[_offset + 5] = (_set_data & 0xFF0000) >> 16; \ + data[_offset + 4] = (_set_data & 0xFF000000) >> 24; \ + data[_offset + 3] = (_set_data & 0xFF00000000) >> 32; \ + data[_offset + 2] = (_set_data & 0xFF0000000000) >> 40; \ + data[_offset + 1] = (_set_data & 0xFF000000000000) >> 48; \ + data[_offset + 0] = (_set_data & 0xFF00000000000000) >> 56; \ + } while (0) + +#define RPC_SET_BE32(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + u64 _set_data = (SET_DATA); \ + data[_offset + 3] = (_set_data) & 0xFF; \ + data[_offset + 2] = (_set_data & 0xFF00) >> 8; \ + data[_offset + 1] = (_set_data & 0xFF0000) >> 16; \ + data[_offset + 0] = (_set_data & 0xFF000000) >> 24; \ + } while (0) + +#define RPC_SET_BE16(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + u64 _set_data = (SET_DATA); \ + data[_offset + 1] = (_set_data) & 0xFF; \ + data[_offset + 0] = (_set_data & 0xFF00) >> 8; \ + } while (0) + +#define RPC_SET_U8(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + data[OFFSET] = (SET_DATA) & 0xFF; \ + } while (0) + +#define RPC_GET_BE64(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + *(u32 *)(PTR) = \ + (data[_offset + 7] | data[_offset + 6] << 8 | \ + data[_offset + 5] << 16 | data[_offset + 4] << 24 | \ + data[_offset + 3] << 32 | data[_offset + 2] << 40 | \ + data[_offset + 1] << 48 | data[_offset + 0] << 56); \ + } while (0) + +#define RPC_GET_BE32(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + *(u32 *)(PTR) = \ + (data[_offset + 3] | data[_offset + 2] << 8 | \ + data[_offset + 1] << 16 | data[_offset + 0] << 24); \ + } while (0) + +#define RPC_GET_BE16(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + *(u16 *)(PTR) = (data[_offset + 1] | data[_offset + 0] << 8); \ + } while (0) + +#define RPC_GET_U8(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + *(u8 *)(PTR) = (data[OFFSET]); \ + } while (0) + +/* + * Defines for SC PM Power Mode + */ +#define TH1520_AON_PM_PW_MODE_OFF 0 /* Power off */ +#define TH1520_AON_PM_PW_MODE_STBY 1 /* Power in standby */ +#define TH1520_AON_PM_PW_MODE_LP 2 /* Power in low-power */ +#define TH1520_AON_PM_PW_MODE_ON 3 /* Power on */ + +int th1520_aon_call_rpc(struct th1520_aon_chan *aon_chan, void *msg); +int th1520_aon_power_update(struct th1520_aon_chan *aon_chan, u16 rsrc, + bool power_on); + +#endif /* _THEAD_AON_H */ From patchwork Mon Dec 23 12:55:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918798 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 806001B4121 for ; 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Mon, 23 Dec 2024 12:56:07 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 06/19] soc: thead: power-domain: Add power-domain driver for TH1520 Date: Mon, 23 Dec 2024 13:55:40 +0100 Message-Id: <20241223125553.3527812-7-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTdxTH+d17e2/bWXYt3fyF6ciIkM1k4MBsv8gemGFyZzadcYmTjEkH N6VYHmlBnPiAtTCpBXzGUBTYQqDhTW07IDCgAsWhwHCWLoOCBIZVZkEKyQBxlMs2//ucc77n fM/55cfHxWbSny9PTmOVyVJFICkkLD1/D7ztipHLdg6WQ9Q7/COGzMt6CtW09WOotKufh5xD Jgz9tuAmUd3UIIUetmUTyG64QSF1Tz2JXHonieZ0Th6613KdRPP5XQBZ5jUkqu0apVD9QimG fpgzE6i8qQWg3LwKHvr1l71o1NlLINc9HY5y9S+j561NFFq1NxKo+Ek7hUwzF3nIVnsYadqv EJGvM25HDsXMuFwEc+uch2LaFssIplk/SjG65juAMVblkcyIvZVkSm4fZMbO2zDmZvlZRlPb gzGFz3Yy7p/vk0yBqQowQ+ph6nNxtPD9eFYhP84qQz+MFSY8KLgEUqujTvSUXiazwH2kBXw+ pHdBQ4NAC4R8MW0AcKDQxOMCD4CmwkmCC+YB7PNcI7VAsN5RM7NMcYVKAHtnXRvBzJrK0kh4 VSQdBscrS9dnSegcAuZ0ZwNvgNPTAFomr6/P8qO/gh2LFZR3E4IOguNLtBdF9EfwO9sZzi0A tnfexb0soCNhjdYBvCyiN8PbRZPrXviaRm0uxr3jId0ohDmlVpxrjoKrV7+nOPaDj2ymDd4K +y7rCI5T4Lj56Yb+FGzW2TY4Ao70L5HefXD6LVjfEsql98DZLjfJvZ0vdPy1mVvBF16yXMO5 tAieyxVz6mB4VZf/n2m/wYJxzMDVx4vUBfCG/oVj9C8co//ftwzgVWALm65KkrGq8GQ2I0Ql TVKlJ8tC4lKSjGDtZ/et2haagOHRXIgVYHxgBZCPB0pEVrFcJhbFS789ySpTjirTFazKCl7j E4FbREHxAayYlknT2GMsm8oq/61ifIF/Frb/yR/Gn+gHng8aXilpVMfqthdlFh+JvFmF/R4T zcjD/Sq/SQzAVPKDEy99krlywviZJVGSMTbhSBvaFr47Lyu2LPq0vyJ/uFOlEAtcf4Ya4qLC uosjlm69F3HllM+s07wnOPFNc930qx5hVILGx2fl6O4vJJJNvMe+sU0n91mCnq4qMpfFsW09 jiP7DvluXymWmD/9OvjY6NaMgJLpkHd3ne7UxhRO2c+vfGzXRFSkVrq+BCuti9nuhmcdD52D B+JEDkN18Ig6YUwn7jt8Nq3OFFWLH982ckG2d6psQreJ2nHoTMfd/IGSO0GYuiysXWAqaJOm BDzvtXQbpzqtRfsrqwMJVYL0nR24UiX9B0eyWkVIBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xe7ovYjPTDb7t1rI4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX8bBvEmPBapeKY/MnszUwXrXoYuTkkBAwkVjz5jd7FyMXh5DAUkaJ7o/9 TBAJGYlr3S9ZIGxhiT/Xutggil4xSmxvXMcIkmATMJJ4sHw+K4gtIrCYRWLvvkqQImaBt4wS 12duBOsWFoiSuPtpJnMXIwcHi4CqxINfAiAmr4C9RNPxOoj58hL7D55lBrE5BRwk1nTdABsv BFTy79QHNhCbV0BQ4uTMJ2ATmYHqm7fOZp7AKDALSWoWktQCRqZVjCKppcW56bnFhnrFibnF pXnpesn5uZsYgcll27Gfm3cwznv1Ue8QIxMH4yFGCQ5mJRHeQ0KZ6UK8KYmVValF+fFFpTmp xYcYTYGunsgsJZqcD0xveSXxhmYGpoYmZpYGppZmxkrivG6Xz6cJCaQnlqRmp6YWpBbB9DFx cEo1MGUdFhATZFr3kXO5X+TN6WLeyfv1D594bfjCU0l/67sOp8BpgvOy0/s8H7KnHpi5aW3p r1LL+z63DFLLLHy+JgpNmnxO+pD4KdVHWvL3Y3yq/9V7X9drzt/qlWXY0PGufadk0sW67/n7 Yhcsn/J+j0R4rCDvo8r0AMdXJcaMTM/7M77vCuT1zuY/vdio8MWduCfnD9asauxkWnL1vaJk dazywScJiXJGqTNOH+y+996fLeNzt2+cr2zrR8ObP7hE/xlN2rqQ02vaG53VR2YrTu0RLK26 9DJOMeGXQMif6IVLrLgXXG6UzZ9dsv2S9Qmvo3v/RJ1zO22/a8fG/bnuDyq0b+/m3/LsV1lD XzD/eiWW4oxEQy3mouJEAPfKQ8m3AwAA X-CMS-MailID: 20241223125608eucas1p25f0be9eb6fb7ab906f942201560dd881 X-Msg-Generator: CA X-RootMTR: 20241223125608eucas1p25f0be9eb6fb7ab906f942201560dd881 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125608eucas1p25f0be9eb6fb7ab906f942201560dd881 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The T-Head TH1520 SoC contains multiple power islands that can be programmatically turned on and off using the AON (Always-On) protocol and a hardware mailbox [1]. The relevant mailbox driver has already been merged into the mainline kernel in commit 5d4d263e1c6b ("mailbox: Introduce support for T-head TH1520 Mailbox driver"); This commit introduces a power-domain driver for the TH1520 SoC, which is using AON firmware protocol to communicate with E902 core through the hardware mailbox. This way it can send power on/off commands to the E902 core. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/Makefile | 1 + drivers/pmdomain/thead/Kconfig | 12 ++ drivers/pmdomain/thead/Makefile | 2 + drivers/pmdomain/thead/th1520-pm-domains.c | 181 +++++++++++++++++++++ 6 files changed, 198 insertions(+) create mode 100644 drivers/pmdomain/thead/Kconfig create mode 100644 drivers/pmdomain/thead/Makefile create mode 100644 drivers/pmdomain/thead/th1520-pm-domains.c diff --git a/MAINTAINERS b/MAINTAINERS index 42aef66bd257..173eeaf3bbe8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20200,6 +20200,7 @@ F: drivers/firmware/thead,th1520-aon.c F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c +F: drivers/pmdomain/thead/ F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/linux/firmware/thead/thead,th1520-aon.h diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 23c64851a5b0..91f04ace35d4 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -16,6 +16,7 @@ source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" source "drivers/pmdomain/tegra/Kconfig" +source "drivers/pmdomain/thead/Kconfig" source "drivers/pmdomain/ti/Kconfig" source "drivers/pmdomain/xilinx/Kconfig" diff --git a/drivers/pmdomain/Makefile b/drivers/pmdomain/Makefile index a68ece2f4c68..7030f44a49df 100644 --- a/drivers/pmdomain/Makefile +++ b/drivers/pmdomain/Makefile @@ -14,6 +14,7 @@ obj-y += st/ obj-y += starfive/ obj-y += sunxi/ obj-y += tegra/ +obj-y += thead/ obj-y += ti/ obj-y += xilinx/ obj-y += core.o governor.o diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdomain/thead/Kconfig new file mode 100644 index 000000000000..3b61e92dde43 --- /dev/null +++ b/drivers/pmdomain/thead/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config TH1520_PM_DOMAINS + tristate "Support TH1520 Power Domains" + depends on TH1520_AON_PROTOCOL || COMPILE_TEST + select REGMAP_MMIO + help + This driver enables power domain management for the T-HEAD + TH-1520 SoC. On this SoC there are number of power domains, + which can be managed independently. For example GPU, NPU, + and DPU reside in their own power domains which can be + turned on/off. diff --git a/drivers/pmdomain/thead/Makefile b/drivers/pmdomain/thead/Makefile new file mode 100644 index 000000000000..adfdf5479c68 --- /dev/null +++ b/drivers/pmdomain/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_TH1520_PM_DOMAINS) += th1520-pm-domains.o diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/thead/th1520-pm-domains.c new file mode 100644 index 000000000000..a56ba164a58d --- /dev/null +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include +#include + +#include + +struct th1520_power_domain { + struct th1520_aon_chan *aon_chan; + struct generic_pm_domain genpd; + u32 rsrc; +}; + +struct th1520_power_info { + const char *name; + u32 rsrc; +}; + +static const struct th1520_power_info th1520_pd_ranges[] = { + { "vdec", TH1520_AON_VDEC_PD }, + { "npu", TH1520_AON_NPU_PD }, + { "venc", TH1520_AON_VENC_PD }, + { "gpu", TH1520_AON_GPU_PD }, + { "dsp0", TH1520_AON_DSP0_PD }, + { "dsp1", TH1520_AON_DSP1_PD } +}; + +static inline struct th1520_power_domain * +to_th1520_power_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct th1520_power_domain, genpd); +} + +static int th1520_pd_power_on(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + return th1520_aon_power_update(pd->aon_chan, pd->rsrc, true); +} + +static int th1520_pd_power_off(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + return th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); +} + +static struct generic_pm_domain *th1520_pd_xlate(const struct of_phandle_args *spec, + void *data) +{ + struct generic_pm_domain *domain = ERR_PTR(-ENOENT); + struct genpd_onecell_data *pd_data = data; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + pd = to_th1520_power_domain(pd_data->domains[i]); + if (pd->rsrc == spec->args[0]) { + domain = &pd->genpd; + break; + } + } + + return domain; +} + +static struct th1520_power_domain * +th1520_add_pm_domain(struct device *dev, const struct th1520_power_info *pi) +{ + struct th1520_power_domain *pd; + int ret; + + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return ERR_PTR(-ENOMEM); + + pd->rsrc = pi->rsrc; + pd->genpd.power_on = th1520_pd_power_on; + pd->genpd.power_off = th1520_pd_power_off; + pd->genpd.name = pi->name; + + ret = pm_genpd_init(&pd->genpd, NULL, true); + if (ret) + return ERR_PTR(ret); + + return pd; +} + +static void th1520_pd_init_all_off(struct generic_pm_domain **domains, + struct device *dev) +{ + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd = + to_th1520_power_domain(domains[i]); + + ret = th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); + if (ret) + dev_err(dev, + "Failed to initially power down power domain %s\n", + pd->genpd.name); + } +} + +static int th1520_pd_probe(struct platform_device *pdev) +{ + struct generic_pm_domain **domains; + struct genpd_onecell_data *pd_data; + struct th1520_aon_chan *aon_chan; + struct device *dev = &pdev->dev; + int i; + + aon_chan = dev_get_drvdata(dev->parent); + if (!aon_chan) { + dev_err(dev, "Failed to get AON channel from parent\n"); + return -EINVAL; + } + + domains = devm_kcalloc(dev, ARRAY_SIZE(th1520_pd_ranges), + sizeof(*domains), GFP_KERNEL); + if (!domains) + return -ENOMEM; + + pd_data = devm_kzalloc(dev, sizeof(*pd_data), GFP_KERNEL); + if (!pd_data) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + pd = th1520_add_pm_domain(dev, &th1520_pd_ranges[i]); + if (IS_ERR(pd)) + return PTR_ERR(pd); + + pd->aon_chan = aon_chan; + domains[i] = &pd->genpd; + dev_dbg(dev, "added power domain %s\n", pd->genpd.name); + } + + pd_data->domains = domains; + pd_data->num_domains = ARRAY_SIZE(th1520_pd_ranges); + pd_data->xlate = th1520_pd_xlate; + + /* + * Initialize all power domains to off to ensure they start in a + * low-power state. This allows device drivers to manage power + * domains by turning them on or off as needed. + */ + th1520_pd_init_all_off(domains, dev); + + return of_genpd_add_provider_onecell(dev->of_node, pd_data); +} + +static const struct of_device_id th1520_pd_match[] = { + { .compatible = "thead,th1520-pd" }, + { /* sentinel */ } +}; + +static struct platform_driver th1520_pd_driver = { + .driver = { + .name = "th1520-pd", + .of_match_table = th1520_pd_match, + }, + .probe = th1520_pd_probe, +}; +module_platform_driver(th1520_pd_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC power domain controller"); +MODULE_LICENSE("GPL"); From patchwork Mon Dec 23 12:55:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918802 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 224B41B392B for ; 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Mon, 23 Dec 2024 12:56:08 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 07/19] riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs Date: Mon, 23 Dec 2024 13:55:41 +0100 Message-Id: <20241223125553.3527812-8-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTVxiHd+69vbd0AS+FjRM3J3ZxiSwiGhZPokPn2HI1ZGFzzulGpMod spVi2jJhKQ7WUj6sQ1RkFBwfIdqwYofQSsvX7IBC6yofo4ICugyDZZ2ICBEGOGjr5n+/877P Oe/zJoeL8xvJ1dwksYyViIUiAckjjJ1zjo0TcUmJEfVn1qGum1UYMvyjoZCuxYGh8nYHB432 NWDo95lJEl2+10Oh+y1ZBHJqL1BI0aknkUszSqIp9SgH9ZvLSDR9qh0g47SSRLXtIxTSz5Rj qHLKQKDqRjNAqryLHNRrew+NjHYRyNWvxpFKswo9bW6k0JKzjkClD9oo1OAu5CBr7X6kbDtH 7HyNmRzMphi3y0Uwv+Y+ppiW2QqCMWlGKEZtug6YKzV5JDPsbCaZH7s/ZO6ctGJMffW3jLK2 E2MKFiOYydYBkvm+oQYwfYqbVCz/IG97AitK+pqVbIqK5x3tMOrwY+f80pTFOioT2Kl84MeF dCS0WcZBPuBx+bQWwJnzObj38BhATWGrrzMN4MPmJuzZFbPiDsfbuATgoj3XR7kB7G7X4ysU SW+Bdy+Ve6hgOpuA2R1ZHgqnxwE0jpWRK1QQHQudeUMeFYJeD+f6mzkr2Z/eAZUKtU9xLWy7 9pvnVT96J9TlDwIvEwi7S8aIlYwvMwpDqccc0nU8eNle6pONhj9c7/DlIDhhbfA9+iq0n1UT 3pwC7xoe4d4shya11Ze3wWHH/LIod3nABqg3b/KW34Hls05PGdIBcPDvQK9CADxjLMa9ZX+Y q+J76TdgkfrUf0MdWqNPhoFN+SXYabBO89wymueW0fw/twLgNSCETZUmJ7LSzWL2eLhUmCxN FSeGH0lJvgKWP7d9yfqoEVyYmAq3AIwLLABycUGwv4WflMj3TxCmf8NKUg5JUkWs1AJe4RKC EP/1CWtZPp0olLFfsewxVvKsi3H9Vmdi+ecH5rc+2fu+zbHQEz8VHz0mTTse2poHX2J3Xc2z f64NvRF6q2BhNyO/rzo9XDdH3JYGhRugWfTmvq7cPZknUqoWsjIG9C+c/LIhzX4kveTwwcjY t1TFcWG9J2ziHseOyrQhXoU5RGablz+59jaeU7BvJmYpurd/Va741usHYiwo6N2KLz7Z8KlL tKgd+OVGVJUuchuGZuVr3Kqz83GWj3/O2aX8bvuLEZKn4qKLe7aQKfEBw+Hj1ca+n+TCj+o3 ake35gTXK/ZXynIkuiFd4OHFB1fvhe2dFrz8x233X1F9TZzgNY7CBfMHMapWmfNQQPFn6QfU fwpCi3rLdhdmPDRlmASE9KhwcxgukQr/BfWoE0ZLBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7qvYjPTDXZ/ZLY4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXcXTbGuaCKZwVLdPXsDcwnmbvYuTkkBAwkdjVfJ+1i5GLQ0hgKaPE1UOz mCASMhLXul+yQNjCEn+udbFBFL1ilPg3dw0jSIJNwEjiwfL5rCC2iMBiFom9+ypBipgF3jJK XJ+5EaxbWMBP4vy0uWANLAKqEj8v7wFr4BWwl2hp7oE6Q15i/8GzzCA2p4CDxJquG2D1QkA1 /059YIOoF5Q4OfMJ2ExmoPrmrbOZJzAKzEKSmoUktYCRaRWjSGppcW56brGhXnFibnFpXrpe cn7uJkZggtl27OfmHYzzXn3UO8TIxMF4iFGCg1lJhPeQUGa6EG9KYmVValF+fFFpTmrxIUZT oLsnMkuJJucDU1xeSbyhmYGpoYmZpYGppZmxkjiv2+XzaUIC6YklqdmpqQWpRTB9TBycUg1M Ur82Sx+ev+PgTNW5/30s3kpMcHNM0F176/vefr5i1cu3tOVe/s09oSu5+rfcpuOei09deTHZ vzmc736E65eyz77PzDLWG53Le/7fYn6HHJfFi787am+wtC1mjmZefuvS638ptZ/+SL0IPPG0 cnOMm7Duc8cT66Y5r2+YVlV8PbL8mtiRi+vuCJp82OOU+GFLz+xSDamdJ5x4lTP23H3Co7ho z8I9LzcZHw+91Ckzr0jtLduOSjGFdRVTzsxQ6vRbfsmb9fTLU5fZvPOiD/2tKj3tvVmA+8BU +Yh9GZc2rX419U4v+8WauA0a7P7zFSZEbRWN8I+PPOi65FrfZrYp8Yq7FkZcu+jnvXttS7x3 ywUlluKMREMt5qLiRADvTtLnuQMAAA== X-CMS-MailID: 20241223125610eucas1p2721f8a199bc6ff16345b3b46fc44dd63 X-Msg-Generator: CA X-RootMTR: 20241223125610eucas1p2721f8a199bc6ff16345b3b46fc44dd63 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125610eucas1p2721f8a199bc6ff16345b3b46fc44dd63 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> T-Head SoCs feature separate power domains (power islands) for major components like the GPU, Audio, and NPU. To manage the power states of these components effectively, the kernel requires generic power domain support. This commit enables `CONFIG_PM_GENERIC_DOMAINS` for T-Head SoCs, allowing the power domain driver for these components to be compiled and integrated. This ensures proper power management and energy efficiency on T-Head platforms. By selecting `PM_GENERIC_DOMAINS`, we provide the necessary framework for the power domain drivers to function correctly on RISC-V architecture with T-Head SoCs. Signed-off-by: Michal Wilczynski --- arch/riscv/Kconfig.socs | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index f51bb24bc84c..c414dc618b66 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -48,6 +48,7 @@ config ARCH_THEAD bool "T-HEAD RISC-V SoCs" depends on MMU && !XIP_KERNEL select ERRATA_THEAD + select PM_GENERIC_DOMAINS if PM help This enables support for the RISC-V based T-HEAD SoCs. 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Mon, 23 Dec 2024 12:56:11 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20241223125611eusmtrp1286a66d470035e4b45147ba9a17fe503~Tz6Dp-G552051220512eusmtrp1X; Mon, 23 Dec 2024 12:56:11 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-7e-67695dec664e Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 69.F3.19920.BED59676; Mon, 23 Dec 2024 12:56:11 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125610eusmtip2281e1d2b6afaaf58cf5d3611edb15604~Tz6CVq5Fm2296222962eusmtip2N; Mon, 23 Dec 2024 12:56:10 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 08/19] dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller Date: Mon, 23 Dec 2024 13:55:42 +0100 Message-Id: <20241223125553.3527812-9-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTVxzHPffe3ntpVnatTM+6DSIKeyngYrKTAA72SK7JSFhCQoLBrchd IeNlC0yWbcIoBbviABG0gtVJRgPUUmgbYLxkCDilykNA0zJC2HhYVqDia0NGuW7zv8/vcb6/ 7zc5NC42kxI6OS2Tk6dJU/xJIWHte2zb64xPloWcafZGA+M/Ysjyl5ZCDR02DOl6bQI0OWzG 0Oiqi0SXf79FobmOPAKN6asplN9nJNG8dpJEy5pJARppqyKRu7gXIKtbSSJDr4NCxlUdhi4u WwhU09IGkOrETwI09OtHyDE5QKD5EQ2OVNoX0Xp7C4WejpkIdO7PLgqZnaUC1G+IRcquciLC l3VNFFCsc36eYH8puk+xHQ8uEGyr1kGxmtYbgG2qO0Gy9rF2kj1/7RP2t+/7Mba55jirNPRh 7A9rIayr8zbJnjTXAXY4f5yKFscJwxK5lORsTh584DNh0so9vSDjgeSY1rlI5ILR7WrgRUNm P6zoOYergZAWM3oATW4X4Iv7AE7PPiH5wg1g0+1GSg3ozScDF/fw/VoAnU4TwRdOAE/ZKgiP Lsm8A6dqdQLPwIcpIGDB1bxNXZyZBdA6U0V6trYxcXBkukDgYYIJgN1V4xtOKFrEvAfLBLw/ P9h1ZRD3sBcTARvUE8DDImYrvHZ2ZvMWvrGTb+EzQMYihMa8JZx3+iEcqpHwOtvgQr+Z4vlV eP2UhuA5HU5ZVnCev4atmv5nHArtNk96ekP/TWhsC+bbkTBfdxfj1b3hxOJW3oE3LLNWPjsq gkUqMb8dCE9riv87atNbMZ5ZWFIySJSAndrnsmify6L9/+4FgNeBHVyWIlXGKfalcV8GKaSp iqw0WdCR9NQmsPGxrz/tX2kB1QvLQT0Ao0EPgDTu7yPqESfLxKJEac5XnDz9U3lWCqfoAa/Q hP8OUUCiHydmZNJM7guOy+Dk/04x2kuSi6XYXl+5FB178Bv5Unfw8LrBdDLg8yDaXSl7dGwu LmE2wmF6AWtos2VHhjaqhQELylu95YdVyiqFCLcHBFoTa1e7IqNidfunUmsL2ZFCapdd9a0f NphwJtrFfND46LHfFeNyfd0fZYdqZqKEPjHx34VnRv0dtn23+qUK6mhqbnNJ7GDta1vCffee ntaX7izHAmssa9kvF02Uzu8uemNOeu/tyIR3DQ+PmkMEa0afS+nKdcfHEqzzifumX8bNA6Eh ipz62aSlJoaarn7YXpB+vNDnaufZO+cjc+xbWkuU3Ydv7Nk1qg9sqwzEVOExQkZSnLtYb3D5 ht2di495/+c7Q0dE/oQiSbrvLVyukP4DiHW3K0cEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMKsWRmVeSWpSXmKPExsVy+t/xe7qvYzPTDd7/FrE4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX8en1CtaCb1IVs968ZWlgvCLWxcjBISFgInFioU4XIxeHkMBSRom3O1ew dzFyAsVlJK51v2SBsIUl/lzrYoMoesUosbD3AjNIgk3ASOLB8vmsILaIwGIWib37KkGKmAXe Mkpcn7kRrFtYIELixaG5YDaLgKrEgTnXgZrZOXgF7CUmsULMl5fYf/As2EhOAQeJNV03GEFs IaCKf6c+sIHYvAKCEidnPgGbwgxU37x1NvMERoFZSFKzkKQWMDKtYhRJLS3OTc8tNtQrTswt Ls1L10vOz93ECEwt24793LyDcd6rj3qHGJk4GA8xSnAwK4nwHhLKTBfiTUmsrEotyo8vKs1J LT7EaAp09URmKdHkfGByyyuJNzQzMDU0MbM0MLU0M1YS53W7fD5NSCA9sSQ1OzW1ILUIpo+J g1OqgamKbZrK4V32QvrTJ6vNCJArr0+8JuT1jbfBc3370c/ruLreZjlf/99SI/Z+4xfn+esC FyesDJNbuvwut5ycjeHOynAGpzesGyQlE/gP3brmMblZ79VR87iNe5mmfzde7s6woWCqYcJU +UTNreffnfdJ65t84pdyqw3X6ZyieY93pmr/YFmSeb09I3LLdD7hyc0ubyc/mztnXvOE90ZT 93W/DD4r+P/9oWid5ND9ezarzGS5drxC7+H+0MwzuvoNk7ucrx4oMVg0x3zv7RAPif6d/TpL Z08q0L/UGiaw6P7RMylc0bWeXmn+64+rT5y5+f+S7t4VmQfTOGQVJxw9Il3QOZVZ6u+xP8cL RBqrOv8osRRnJBpqMRcVJwIArJRzoLYDAAA= X-CMS-MailID: 20241223125611eucas1p1acf9a7f030c4c8687f946c34f8043bcd X-Msg-Generator: CA X-RootMTR: 20241223125611eucas1p1acf9a7f030c4c8687f946c34f8043bcd X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125611eucas1p1acf9a7f030c4c8687f946c34f8043bcd References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Add a YAML schema for the T-HEAD TH1520 SoC reset controller. This controller manages resets for subsystems such as the GPU within the TH1520 SoC. Signed-off-by: Michal Wilczynski --- .../bindings/reset/thead,th1520-reset.yaml | 45 +++++++++++++++++++ MAINTAINERS | 2 + .../dt-bindings/reset/thead,th1520-reset.h | 13 ++++++ 3 files changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml create mode 100644 include/dt-bindings/reset/thead,th1520-reset.h diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml new file mode 100644 index 000000000000..46d0e6b8c712 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 SoC Reset Controller + +description: | + The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts + resets for SoC subsystems. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + enum: + - thead,th1520-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 173eeaf3bbe8..db8c55058c29 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20194,6 +20194,7 @@ F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: Documentation/devicetree/bindings/power/thead,th1520-power.yaml +F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: drivers/firmware/thead,th1520-aon.c @@ -20202,6 +20203,7 @@ F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ F: include/dt-bindings/clock/thead,th1520-clk-ap.h +F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h RNBD BLOCK DRIVERS diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h new file mode 100644 index 000000000000..a4958b2ed710 --- /dev/null +++ b/include/dt-bindings/reset/thead,th1520-reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef _DT_BINDINGS_TH1520_RESET_H +#define _DT_BINDINGS_TH1520_RESET_H + +#define TH1520_RESET_ID_GPU 0 +#define TH1520_RESET_NUM_IDS 1 + +#endif /* _DT_BINDINGS_TH1520_RESET_H */ From patchwork Mon Dec 23 12:55:43 2024 Content-Type: text/plain; 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Mon, 23 Dec 2024 12:56:12 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-82-67695ded60de Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3E.73.19654.CED59676; Mon, 23 Dec 2024 12:56:12 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125611eusmtip2d22b094104dd478af478866667b01b85~Tz6DiN4vn3173831738eusmtip2M; Mon, 23 Dec 2024 12:56:11 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 09/19] reset: thead: Add TH1520 reset controller driver Date: Mon, 23 Dec 2024 13:55:43 +0100 Message-Id: <20241223125553.3527812-10-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xbZRz1u/f23tvO4l2Z2yeIzOJMUHkZST50WzBBcolRcVGZIw7u5MKY ULYWxlAjzAKyrgwZ4rLSCsMhDfKcpbxBuo7CeDkQaCKUoZDBAjY8RsTHZrt2uv/O75zz+875 JR+NS1pJLzpZls7LZVyKlBQRxr6tkYCVD5KTglsqPFD/VCWGmv/SUKi2awRD5eYRAbKNGTD0 8x07ieoXfqLQYtdpAk3qdRRS9jWQaEljI9Gq2iZA4+1aEq0XmgEyrueSqM48Q6GGO+UYurTa TKDLre0A5Z/5ToBuXH8Nzdj6CbQ0rsZRvuYxdK+zlUJ3J5sIVPZ7D4UMy8UCZKmLQbk9XxHh T7F2ax7FLi8tEezVgg2K7dqsINg2zQzFqtuGAHul5gzJTk92kuw3A2+zs2ctGPvD5Ww2t64P Y4v+CWbt3RMke85QA9gx5RQVLTkk2pvApySf5OVB++NFRxd7F6jjJaGnls5eoHKA+QUVENKQ eQmuDesxFRDREkYPoPW8hXQNGwDWNCrdyjqAqvpB4sFK0cIXbqEawHMD31OuYRnAv9s7caeL ZF6EN6vLBU5hB5NHwLxrp4FzwJlbABrntaTT5clEw7H2YsqJCWYPrJirAE4sZsLhkKqAcuX5 wp7e4fuvCh18rcrq9myHAxfn73fCHR5lcxnuDIBMnQj+2KgVuJYjYOngqLu4J7xtMbgffRIO lqjdfBq82byGu/CnsE1tceNX4PTIn46itCPAHza0B7noV2HP3B+4k4aMB7SubHdV8IDnjRfc tBgW5Etc7mdhqbrwv9ARvRFzYRYuNxmpL8HTmoeO0Tx0jOb/3AqA14BdfIYiNYlXhMj4zEAF l6rIkCUFfpiWegU4PvfgXctaK9DdXg00AYwGJgBpXLpDbJIkJ0nECVzWx7w8LU6ekcIrTMCb JqS7xHsSfHkJk8Sl8x/x/HFe/kDFaKFXDlZgEYXIrjKPnwjz2s0+83zwNt270zlZkdFe0zEB Qf6HO30Cek+EcUrUZN8WtV91rPfztaojLTP1eu0T+qHftoo00dZK3ey+uaqdm9lhn33r5783 PqY7Iev90Jqm+E/SD3T0Z0ca+k7VF8nSDt06IkzLFEmUo97dw8MGe3xUy9dmi3wi9pEOfXii p6nx4mSoLWSriheOHnx9yj8z/5dj7+0ebbxuKtt65/A9nwhrR5VHZmJkVO4N79rl0rYDurjC ShFdoreFL4an/1odUbwyAE8ScbETftek4wuxXGrbpX264vpe6JM4u7Jx0E/LcX4235fnzT07 Sdlbb/h5JGy+ufmoVkoojnIhz+FyBfcvg2aCVEsEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7pvYjPTDRYu17E4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX8eLgU/aCyaYVL7unszcwHtHpYuTkkBAwkeh/2s7UxcjFISSwlFHi+IkL jBAJGYlr3S9ZIGxhiT/Xutggil4xSrRMOwqWYBMwkniwfD4riC0isJhFYu++SpAiZoG3jBLX Z24EKxIW8JP4vPcs2FQWAVWJBQ8XgNm8Ag4SZ7o62CE2yEvsP3iWGcTmBIqv6boBViMkYC/x 79QHNoh6QYmTM5+AzWQGqm/eOpt5AqPALCSpWUhSCxiZVjGKpJYW56bnFhvpFSfmFpfmpesl 5+duYgQmmG3Hfm7Zwbjy1Ue9Q4xMHIyHGCU4mJVEeA8JZaYL8aYkVlalFuXHF5XmpBYfYjQF unsis5Rocj4wxeWVxBuaGZgamphZGphamhkrifOyXTmfJiSQnliSmp2aWpBaBNPHxMEp1cA0 87DDW5Yt5yVO7OQ67PT3yOoqFo0v5wr1ps5fa9wu6MEcra3ZJbeEJdvX4P52gejzUz3ffUyc 2hChVrtG0N7a89cW/YBjht96l78Jm8HP/OriiWKPql1WCg84fXK2ppzd//JyJWu2ce4NsemB +1o+OT7YucjsSMeflR67t029kX3x7xl3lhMHuPacnRrXz7UjYbvG/o12R5w3dk9k4bmjkMga y3O2XyvofP/pVUz50ifvrOe6b3n9IGNP3tK8Z//86i4VvzVaus31Tvlp3Wohw8kzFndkebxP 1Y38nK03o6yyPZz3dmDFJaEmQ9ljvzb02lrOYZ/OLDDP3i8t1IbT4f1hI7uVtdJsttoluUFK LMUZiYZazEXFiQALVyeRuQMAAA== X-CMS-MailID: 20241223125612eucas1p1d27f793116fa405911f07cfc926c0129 X-Msg-Generator: CA X-RootMTR: 20241223125612eucas1p1d27f793116fa405911f07cfc926c0129 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125612eucas1p1d27f793116fa405911f07cfc926c0129 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> This patch introduces the reset controller driver for the T-HEAD TH1520 SoC. The controller manages hardware reset lines for various SoC subsystems, such as the GPU. By exposing these resets via the Linux reset subsystem, drivers can request and control hardware resets to reliably initialize or recover key components. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-th1520.c | 151 +++++++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+) create mode 100644 drivers/reset/reset-th1520.c diff --git a/MAINTAINERS b/MAINTAINERS index db8c55058c29..38130ae25c6f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20202,6 +20202,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5b3abb6db248..fa0943c3d1de 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -272,6 +272,16 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. +config RESET_TH1520 + tristate "T-HEAD 1520 reset controller" + depends on ARCH_THEAD || COMPILE_TEST + select REGMAP_MMIO + help + This driver provides support for the T-HEAD TH1520 SoC reset controller, + which manages hardware reset lines for SoC components such as the GPU. + Enable this option if you need to control hardware resets on TH1520-based + systems. + config RESET_TI_SCI tristate "TI System Control Interface (TI-SCI) reset driver" depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 677c4d1e2632..d6c2774407ae 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o +obj-$(CONFIG_RESET_TH1520) += reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c new file mode 100644 index 000000000000..10ca200690d5 --- /dev/null +++ b/drivers/reset/reset-th1520.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + +#include + + /* register offset in VOSYS_REGMAP */ +#define TH1520_GPU_RST_CFG 0x0 +#define TH1520_GPU_RST_CFG_MASK GENMASK(2, 0) + +/* register values */ +#define TH1520_GPU_SW_GPU_RST BIT(0) +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) + +struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; +}; + +static inline struct th1520_reset_priv * +to_th1520_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct th1520_reset_priv, rcdev); +} + +static void th1520_rst_gpu_enable(struct regmap *reg) +{ + int val; + + /* if the GPU is not in a reset state it, put it into one */ + regmap_read(reg, TH1520_GPU_RST_CFG, &val); + if (val) { + regmap_update_bits(reg, TH1520_GPU_RST_CFG, + TH1520_GPU_RST_CFG_MASK, 0x0); + } + + /* rst gpu clkgen */ + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_CLKGEN_RST); + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + /* rst gpu */ + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_GPU_RST); +} + +static void th1520_rst_gpu_disable(struct regmap *reg) +{ + regmap_update_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_RST_CFG_MASK, 0x0); +} + +static int th1520_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + + switch (id) { + case TH1520_RESET_ID_GPU: + th1520_rst_gpu_disable(priv->map); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int th1520_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + + switch (id) { + case TH1520_RESET_ID_GPU: + th1520_rst_gpu_enable(priv->map); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct reset_control_ops th1520_reset_ops = { + .assert = th1520_reset_assert, + .deassert = th1520_reset_deassert, +}; + +const struct regmap_config th1520_reset_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static int th1520_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map = + devm_regmap_init_mmio(dev, base, &th1520_reset_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = TH1520_RESET_NUM_IDS; + priv->rcdev.ops = &th1520_reset_ops; + priv->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id th1520_reset_match[] = { + { .compatible = "thead,th1520-reset" }, + { /* sentinel */ } +}; + +static struct platform_driver th1520_reset_driver = { + .driver = { + .name = "th1520-reset", + .of_match_table = th1520_reset_match, + }, + .probe = th1520_reset_probe, +}; +module_platform_driver(th1520_reset_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC reset controller"); +MODULE_LICENSE("GPL"); From patchwork Mon Dec 23 12:55:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918797 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62F0E1B21B9 for ; Mon, 23 Dec 2024 12:56:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734958581; 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Mon, 23 Dec 2024 12:56:12 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 10/19] drm/imagination: Add reset controller support for GPU initialization Date: Mon, 23 Dec 2024 13:55:44 +0100 Message-Id: <20241223125553.3527812-11-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTZxjG851zek5hKR6ObnwyIhEHcUQB0cxvgTQQZ3L+2AWTZU7DLs16 UsnKxRYGOpaBXAZYQAQhq1ysGFoIFMS2FiYQK9KKkzEulUwobMNsdQwCiAxMYW0Pbv73fM/7 e/K8b/IJccZEBgqTUtI5RYpEHkL6EqaBtZ/2z3+SJItq1h5CtodXMWR8rqZQa88Qhhr6hwTI MWLA0NjKAon0j4cp9GdPLoHsujoK5Q20k8ipdpBoUeUQoNHuWhItl/YDZFrOJ1Fb/xSF2lca MKRZNBLomrkboMLiJgH6efAomnLYCOQcVeGoUL0Nbd4yU2jDfp1Al+f7KGSYqxAga9txlN9X RcTtYhcmCih2zukk2DtFTym259kVgu1ST1GsqutHwHa2FJPspP0WydbfO8ZOn7di7I1r37L5 bQMYW+6KYhd6x0m2zNAC2JG8h1QCc9I3VsrJk77iFJHiz31PfXdXi6U92J015hzBckBeUAnw EUL6EFQ1lRMezdA6AMddshLg69ZPAbyuXRPwj2UAf1NpqBeJ+sZOnE9oAay9EcJDcwDODWtI z4Cko+GMtsGb3kEXELDgbi7wPHD6DwBNs7VeajsthXn5MwKPJuhQWHezw7uIiI6DteYqkq8L hn23H3jrfNx+a8kE4Bl/eO/7WS+Pu5k842XcUwDpZl+oLysX8OF3oMVVjPN6O3xiNWzdEATv V6oIXqfCGePSFpMNu1TWLR0DJ4fW3UsI3QVvwvbuSN6Oh6tlDZTHhrQfnPjbn1/BD1401eC8 LYJFhQxPh8FLqtL/Sod0JozXLLxqnsYugN3ql45Rv3SM+v/eKwBvAQFchjJZxikPpnCZEUpJ sjIjRRbxRWpyJ3B/7fsb1hUz0D1ZjLAATAgsAArxkB0iC5MkY0RSyZmznCL1M0WGnFNawOtC IiRAFCoN5hhaJknnvuS4NE7xYooJfQJzsDP2ivnm4x8PiWoGR5ilsQQ0+k95Y+VOa/yFwXaV s6dCIzlm8Qv7VMaco1KOxGQuHY0aN23G2Q0FWVn1f40Zo/XR3b/rfsh5b1/TrsRH08aThD7t rVcV07/6h3e25EuGzwX3igIr48Oow+8G+cXTuWLhM3PH6Yt7GquKR2IL37AxTKSra89C7Gbg keyymzXZqLHdWP3YZJPHTx6MqXb8sg4zxNXK6rB9uWvkcAwUpEHxgdc4Qt7xoSvZVWpM9++k zgcczqmL1mQ9R4mntxXp61cnbBs2f6C5vX62T9yyqr8zqxbvDf3oG8nXOz8IDJIm9L4f/krr pROZ++cSHW8/CiGUpyQHwnGFUvIvZKabokkEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7rvYjPTDY6c4bI4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX0X50OVPBWcWKKy8vMTUwNst0MXJySAiYSMxbvIkZxBYSWMoocbfZCyIu I3Gt+yULhC0s8edaF1sXIxdQzStGiQ83GllBEmwCRhIPls8Hs0UEFrNI7N1XCVLELPCWUeL6 zI1g3cICSRKHm/rYQGwWAVWJuds3gMV5BRwk5uyYwgaxQV5i/8GzYFdwAsXXdN1ghLjIXuLf qQ9sEPWCEidnPgHrZQaqb946m3kCo8AsJKlZSFILGJlWMYqklhbnpucWG+kVJ+YWl+al6yXn 525iBKaXbcd+btnBuPLVR71DjEwcjIcYJTiYlUR4DwllpgvxpiRWVqUW5ccXleakFh9iNAW6 eyKzlGhyPjDB5ZXEG5oZmBqamFkamFqaGSuJ87JdOZ8mJJCeWJKanZpakFoE08fEwSnVwMRx qDm2wHzB5l8e85zu3eINW7Wmf1q//TaxjqypZSKXVLdwXjXz2uBYmrvErUnQ48PGlLmHfBV1 trWUpv70ljv2RPphQgJLb3F7WEDCwfN1GRoCZ27vTzvcJ5GfwHSN93vO12TNRZ3FkZ9S3zjs j3L5yWhwzrarI768V+7w9Ic7dwgxtH5TWRAn80ut78pOq7PT0ucwcUyy90390h304MLk46+t 1q2ruHrVZvcm+2bndfOeX221rWLRehseeuL7wjN7lOYo7GG4qyNT3H/w3q4Ngp/j9PoPWPf4 T9DUWbwpYfM/pXOcYZycXwqUypYEbNKLYrijXPLu8kwWV/aJPxg8583boZR4ec+6XPeOciWW 4oxEQy3mouJEALV9NhS4AwAA X-CMS-MailID: 20241223125614eucas1p181b9db4e69de9915f0234fb1d1348465 X-Msg-Generator: CA X-RootMTR: 20241223125614eucas1p181b9db4e69de9915f0234fb1d1348465 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125614eucas1p181b9db4e69de9915f0234fb1d1348465 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Certain platforms, such as the T-Head TH1520 and Banana Pi BPI-F3, require a controlled GPU reset sequence during the power-up procedure to ensure proper initialization. Without this reset, the GPU may remain in an undefined state, potentially leading to stability or performance issues. This commit integrates a dedicated reset controller within the drm/imagination driver. By doing so, the driver can coordinate the necessary reset operations as part of the normal GPU bring-up process, improving reliability and ensuring that the hardware is ready for operation. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_device.c | 21 +++++++++++++++++++++ drivers/gpu/drm/imagination/pvr_device.h | 9 +++++++++ drivers/gpu/drm/imagination/pvr_power.c | 15 ++++++++++++++- 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c index 1704c0268589..83a8ba70a30e 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,21 @@ static int pvr_device_clk_init(struct pvr_device *pvr_dev) return 0; } +static int pvr_device_reset_init(struct pvr_device *pvr_dev) +{ + struct drm_device *drm_dev = from_pvr_device(pvr_dev); + struct reset_control *reset; + + reset = devm_reset_control_get_optional_exclusive(drm_dev->dev, "gpu"); + if (IS_ERR(reset)) + return dev_err_probe(drm_dev->dev, PTR_ERR(reset), + "failed to get gpu reset line\n"); + + pvr_dev->reset = reset; + + return 0; +} + /** * pvr_device_process_active_queues() - Process all queue related events. * @pvr_dev: PowerVR device to check @@ -509,6 +525,11 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; + /* Get the reset line for the GPU */ + err = pvr_device_reset_init(pvr_dev); + if (err) + return err; + /* Explicitly power the GPU so we can access control registers before the FW is booted. */ err = pm_runtime_resume_and_get(dev); if (err) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 6d0dfacb677b..f6576c08111c 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -131,6 +131,15 @@ struct pvr_device { */ struct clk *mem_clk; + /** + * @reset: Optional reset line. + * + * This may be used on some platforms to provide a reset line that needs to be de-asserted + * after power-up procedure. It would also need to be asserted after the power-down + * procedure. + */ + struct reset_control *reset; + /** @irq: IRQ number. */ int irq; diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c index ba7816fd28ec..87a955600d8b 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -252,6 +253,9 @@ pvr_power_device_suspend(struct device *dev) clk_disable_unprepare(pvr_dev->sys_clk); clk_disable_unprepare(pvr_dev->core_clk); + if (pvr_dev->reset) + err = reset_control_assert(pvr_dev->reset); + err_drm_dev_exit: drm_dev_exit(idx); @@ -282,16 +286,25 @@ pvr_power_device_resume(struct device *dev) if (err) goto err_sys_clk_disable; + if (pvr_dev->reset) { + err = reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + } + if (pvr_dev->fw_dev.booted) { err = pvr_power_fw_enable(pvr_dev); if (err) - goto err_mem_clk_disable; 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Mon, 23 Dec 2024 12:56:15 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20241223125615eusmtrp1840abba5b4072feba5f4284e2ba926c9~Tz6Hirjy22059320593eusmtrp1y; Mon, 23 Dec 2024 12:56:15 +0000 (GMT) X-AuditID: cbfec7f5-e59c770000004fad-9b-67695df06cfc Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 04.83.19654.FED59676; Mon, 23 Dec 2024 12:56:15 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125614eusmtip2b8f68f28c34f19f988afc93cb65a78a9~Tz6GLQ_i22639426394eusmtip2Q; Mon, 23 Dec 2024 12:56:14 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 11/19] dt-bindings: gpu: Add 'resets' property for GPU initialization Date: Mon, 23 Dec 2024 13:55:45 +0100 Message-Id: <20241223125553.3527812-12-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf1CTdRzH+z7Ps+cZuxs9jHX7Rp7UwsREROrsm3idpNmDaeFdxlnXj9We JsdPNxHz7JQ2CMYIJIlzSIPEBJQ4aFtAwBBwU4glP0R+TuisNiMQN0r0GDEeKv97fT+f9+fz /nw+9+XjIhMZxI9PPsQqk2WJUlJAmK3z9g133o1XRBTnEujKjW8wZHqgp9DFFjuGDJ12HnL0 GTE0MDdDou9+vUYhZ0sGgQYrSymkttaSyKV3kGhW5+Ch/qYzJHLndQJkdmtIVNM5TqHaOQOG ymdNBKpoaAIoK+dbHurtegWNO64QyNWvw1GW/lG02NxAIe9gHYFKpi0UMk6d5CFbTRzSWE4R 21YzM0OZFDPlchFMR7aHYlr+KiOYRv04xegafwJMfXUOyYwNNpPM11f3MjdzbRjzfcVxRlNj xZj8hQhmpvU6yXxhrAZMn/oGFSt6W7BVzibGH2aVG1/6QHCgYv4mSJ2mjhgcA/gJ0EFqAZ8P 6efhL0NrtcCPL6IrAWwrDdMCwRJ7ABx/0Aq4hxvAy6dGgE/lKxjNd+JcxXkA+z6L4ERTAJa2 DS4nSDoSTpw38HwJMZ1JwMzLGcutcPp3AM23zpA+VSD9HjR7f6N8TNBrYF29B/OxkN4GDTNq irMLhpZLPctd/ZbiF7VDgNMEwKunbxE+xpc0alMJ7jOAdI0AfrUwjHHFO2Bh4fDK3IHwts24 0nQV7P5SR3CcAidMd3GOj8FGnW2Fo+CY/f7ykXB6Haxt2siFo+FElRlwt/OHQ38GcCP4w0Jz Mc6FhTA7S8Spn4FFurz/TO2V5pXBGNij68UKwFP6h5bRP7SM/n/fMoBXAwmbpkpSsKrnktn0 cJUsSZWWrAj/KCWpHiz97G6vba4BVN6eDW8HGB+0A8jHpWJhuyheIRLKZZ8cZZUp7yvTEllV O3iCT0glwjXyYFZEK2SH2ASWTWWV/2Yxvl/QCWx7ldfyYqRk3F06un74qHXP/h2C5gzx+u7X uz62lE0/3lkiPf1G2I/Xj00bL/B4eSWTC870O557o+fuN1rF19KjN3lCw2NeS3Mg9MLBrSfP JnbtBZO6I0/qq1yKn1c5zypH7k2ORc4vzMgL9v3x2IUw18Cbd3t46h92RockbJc9DbYMCNZC d+DfkghNnjpr86K4SDsbN/1IrOWdt+o2oJjWQC8qWOdUSBJ2k0SqYDE41BgZ17+zWxsTV1cc q5cXZm/J75A27ztcVB4SvflDzTlljjuqv7xZ2ZBLhrwcFcroK4xBn3+aljvSJQ/e5TxuFx+s fTU7oK13v7t8dbU/2hV6SUqoDsg2PYsrVbJ/ALyiZi1IBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7rvYzPTDZZvVbA4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXseTnfcaCd+wV8+9dYW5gPMzWxcjJISFgInG7/wVzFyMXh5DAUkaJtb1z mSESMhLXul+yQNjCEn+udbFBFL1ilNiwfh1Ygk3ASOLB8vmsILaIwGIWib37KkGKmAXeMkpc n7kRrEhYIEZi3dwnjCA2i4CqxMZNX5hAbF4BB4n575vZITbIS+w/eBZsMydQfE3XDbB6IQF7 iX+nPrBB1AtKnJz5BGwmM1B989bZzBMYBWYhSc1CklrAyLSKUSS1tDg3PbfYSK84Mbe4NC9d Lzk/dxMjMMFsO/Zzyw7Gla8+6h1iZOJgPMQowcGsJMJ7SCgzXYg3JbGyKrUoP76oNCe1+BCj KdDdE5mlRJPzgSkuryTe0MzA1NDEzNLA1NLMWEmcl+3K+TQhgfTEktTs1NSC1CKYPiYOTqkG Ju4Q63cM03eszY44topHX1EwQK4uJbLqH/Ptz1EOgpWGHIu/XQhhDzUTztTeqxk3U0plz3yH rbPvMi3Z11FXpq3usMP1+i0lJvbwCOXPu3dam9acsF6QGLWz3uD47XXP2QPl5ZeUnXv+fH7B z5CHHOaX6nr3/urMV+Ne2a04ufy9pKBM1LGNUxx/Xi+q51dyNvNR5Hm9+U9bUDv7+1B2H27V lUbcoZauL2uvcyT5tckcsta/+jeO+eOTnXfsXCWmqinK7XhwcffeTD+jJ9aXG2ReKaSvuzXT ze/N4tVH+fqOH22pXCqh/PTOtOhJpV+5dEVKdT8FH2yVmXhnLqOn8rFiz5ud7MlbfiuvCdmt xFKckWioxVxUnAgAYwq0B7kDAAA= X-CMS-MailID: 20241223125615eucas1p10cd69b9a6f03f33ce9b9346558de6ce6 X-Msg-Generator: CA X-RootMTR: 20241223125615eucas1p10cd69b9a6f03f33ce9b9346558de6ce6 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125615eucas1p10cd69b9a6f03f33ce9b9346558de6ce6 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Many RISC-V boards featuring Imagination Technologies GPUs require a reset line to be de-asserted as part of the GPU power-up sequence. To support this, add a 'resets' property (and corresponding 'reset-names') to the GPU device tree bindings. This ensures the GPU can be properly initialized on these platforms. Signed-off-by: Michal Wilczynski --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087..4078cc816ea1 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -37,6 +37,12 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 1 + + reset-names: + const: gpu + required: - compatible - reg From patchwork Mon Dec 23 12:55:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918803 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E8321B4137 for ; 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Mon, 23 Dec 2024 12:56:15 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 12/19] dt-bindings: gpu: Add compatibles for T-HEAD TH1520 GPU Date: Mon, 23 Dec 2024 13:55:46 +0100 Message-Id: <20241223125553.3527812-13-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sf1CTZRzved937zu4Nl8mxZNp5O7IqztAPQ+fKzPNsjc50/6y6Ax3471B jh9uLKWjgjZAcQL+6IiXEYg6abJQYgsI3LWQTbFRogOLgSYcwW3yY2LDHdTGS+V/n8/n+/l8 fzz3CHGJlVwhzMjKZVVZMqWUjCSs3XOu+Om9GYq1+qpnkLO/HkOWIEehxk4Xhmq7XAI0dKMF QzdnJ0n07egvFPqzs5BA7oYaCmm7m0g0zg2RaFo/JEB97QYS+Y91AWT160hk7vJQqGm2FkOn py0EOtvaDlDxEaMA/XrtTeQZchJovE+Po2JuGfq7o5VCC+5LBKq+b6NQi/e4ADnMe5DOdorY 8hwzOVBEMd7xcYL56fADiul8WEcwbZyHYvRt1wHTbDpCMoPuDpL5+uq7zPBRB8Z8d/ZzRmfu xpjy+bXM5OVbJFPWYgLMDW0/tVuSErkpjVVmfMyqEjfvi0z3XPKCnOPRhwpHnWQBmBKXgggh pDfACcsPoBRECiV0A4ALvptL5AGAfRedAp74ASwz9IYqwsVIjQ7y+nkArVeMFE+8AOpKglS4 L0mvh3fO1y6mo+kiAhZdKVzsi9NjociIgQy7ltN7YOOjjsUEQcdBW8AoCGMRvQVe0AYIfsNY aPvxZzyMI0J6Y+kA4D1R8GrVyKIHD3m0lmqc95sj4Tctah6/ASuDxRSPl8MJR8sSXgl7TuqX +mfDO5aZpWw+bNM7lvArcND1iAyfjNMvwqb2RF7eCm32EYx/CTEc8EXxG4jhCWslzssieLhY wrtfgF/qj/031NVgxXjMQNfJckEFWM09dgv32C3c/3PrAG4CMaxGnalg1euy2IMJalmmWpOl SJBnZzaD0NfuWXDMtIKaiekEO8CEwA6gEJdGi+ySDIVElCbL+4RVZaeqNEpWbQfPCglpjCgu LZaV0ApZLrufZXNY1b9VTBixogBL/GBDyV+3qEPoxNN7ffUXk15N6i1x3072f3Ft0Bf3+6b7 lerh/Nr8g6mG9Kden8obSV812tv5m8ZSl1qY/Jq3NWp0LkbQtOuc4Xv8zM4c7YQsdWF2rlsr lyk55YHyNW+lzHJFjiB3YKM0LdDzhGjlw9i7dNkO00cjz1eKc3Wng4qpVfvG5Mn3jrZ9en2b Uv7+9pfX1/VuZc9EGIt33XWURLmH2Nh60VfRyUkXKt6RmqtTSs7Fj6127h74w79MM79twHR7 TJOkwKoC90yYb7w/YSK+ojmQM0w3l8ft4Hy0Z+N7MzWtm+c/vJynrTLWArFg+9Rn2NtPeuQF iv3tUhe+ZqeUUKfL1r2Eq9SyfwAYRxV/SQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7ofYjPTDY60W1qcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLuLvxDWPBRJGKxqcn2BoYP/B1MXJwSAiYSMxtkehi5OIQEljKKPFk6wmW LkZOoLiMxLXul1C2sMSfa11sEEWvGCW6vj1kBUmwCRhJPFg+H8wWEVjMIrF3XyVIEbPAW0aJ 6zM3gnULC4RKnF/0mQ3EZhFQldj/YxlYA6+Ag8Tq5h9QG+Ql9h88ywxicwLF13TdYASxhQTs Jf6d+sAGUS8ocXLmE7B6ZqD65q2zmScwCsxCkpqFJLWAkWkVo0hqaXFuem6xoV5xYm5xaV66 XnJ+7iZGYHrZduzn5h2M81591DvEyMTBeIhRgoNZSYT3kFBmuhBvSmJlVWpRfnxRaU5q8SFG U6C7JzJLiSbnAxNcXkm8oZmBqaGJmaWBqaWZsZI4r9vl82lCAumJJanZqakFqUUwfUwcnFIN TDX3GfsSPohGmPDcPTtNmnVTof60uPg3nktvGz7dPr9Zt3atcOu2+aldzgkbdIQlS9YnBa59 XliZqPznvYLZ57UmBg+V75p9tuv+/+1p4sWvtzaqFyfoGk1c9eesmPH/5P9S/JMVKk+IRD65 E9X4LaQvwLxE7fsBv9sna1NnFbvUZrdV7nideVf9L1vv9L3hnfP/CZ96oW6e8+Z4tFxK3gnT Czc+bu+rXVnGdsn30kcd/v1iSnwzje1n3AucYThn27fybz2s/8/Uttze26Dhy3jNLsNJreC/ wqqs9Wv3buDV0pU4FN/mvD1aT4f1UHRvgFOycE7aUjMnvuydfNtr2G5dnsBwyzfV9erCtN5w JZbijERDLeai4kQAYzCmz7gDAAA= X-CMS-MailID: 20241223125617eucas1p25256081c64ae4e64a12c6ec427f75e8e X-Msg-Generator: CA X-RootMTR: 20241223125617eucas1p25256081c64ae4e64a12c6ec427f75e8e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125617eucas1p25256081c64ae4e64a12c6ec427f75e8e References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Add a new SoC-specific compatible ("thead,th1520-gpu") for the T-HEAD TH1520 GPU, alongside the Imagination BXM family compatible ("img,img-bxm"). This documents the GPU integration on the T-HEAD platform. Also adjust clock name constraints to accommodate a second clock named "sys" instead of "mem" for T-HEAD. This is achieved by changing the order, and making the 'sys' appear before 'mem'. Provide example of the new GPU node. Signed-off-by: Michal Wilczynski --- .../bindings/gpu/img,powervr-rogue.yaml | 32 +++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4078cc816ea1..1eb1c15baec4 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -15,7 +15,10 @@ properties: items: - enum: - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable + - thead,th1520-gpu + - enum: + - img,img-axe # IMG AXE GPU model/revision is fully discoverable + - img,img-bxm reg: maxItems: 1 @@ -27,8 +30,8 @@ properties: clock-names: items: - const: core - - const: mem - const: sys + - const: mem minItems: 1 interrupts: @@ -62,6 +65,15 @@ allOf: properties: clocks: maxItems: 1 + - if: + properties: + compatible: + contains: + const: thead,th1520-gpu + then: + properties: + clocks: + maxItems: 2 examples: - | @@ -77,3 +89,19 @@ examples: interrupts = ; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; }; + + #include + #include + #include + + gpu: gpu@fff0000 { + compatible = "thead,th1520-gpu", "img,img-bxm"; + reg = <0xfff0000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_GPU_CORE>, <&clk CLK_GPU_CFG_ACLK>; + clock-names = "core", "sys"; + power-domains = <&pd TH1520_AON_GPU_PD>; + resets = <&rst TH1520_RESET_ID_GPU>; + reset-names = "gpu"; + }; From patchwork Mon Dec 23 12:55:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918805 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E3AF1B4F15 for ; Mon, 23 Dec 2024 12:56:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 23 Dec 2024 12:56:16 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 13/19] drm/imagination: Add support for IMG BXM-4-64 GPU Date: Mon, 23 Dec 2024 13:55:47 +0100 Message-Id: <20241223125553.3527812-14-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xTZxzdd+/tvaVJ4VJ8fAGn2KVONkUgZH4Zm2HZMDd7OPljw2nIVuVa mRRMC2wSN2EFprXgdDBrwVHQ0AqUR6E8ukIdQqmgHag8zKCgwiasijzUMCMbpXXzv3N+5/x+ 5zvJx8UFTWQgNzE5lZUli5OEJI9otC04Ns/GJ0rCfjdEIvtgGYZMTzUUqmp1YKikw8FBzusN GLr5aJpE1RO9FLrXmkWgAf05CilsNSSa1DhJNKNyctANczGJ5vI6AGqcyyaRoWOEQjWPSjBU OmMi0IVmM0C5x8s5qK87Bo047QSavKHCUa7GD/1jaabQ4kAdgYoeWCnU4DrFQV2GOJRtLSCi 1zLTQzkU45qcJJjLx+YppvWxlmBaNCMUo2q5ChhjxXGSGR6wkMzPV2KZ0RNdGFN/4SiTbbBh zMlnYcx0Wz/J5DdUAOa6YpDaKdjNeyuBTUpMZ2Vbtn3BO2A1n8UOVXK//s2hIzOBglICHy6k I+F87hlMCXhcAa0HsP/xUy+ZB3BhoJv0kDkAZwq0+POV3gkl8Ag6ADO7n3hXXABWNv1CuF0k HQHHdCUct7CCziFgTmfW8gpO/wlg43gx6XYF0LHw0pwRuDFBi6Cx1raM+XQ0HK+yefPWQeuv 15axz9K8Sjnk9fjDK2fHl9PwJY/CVIS7AyBt4MGbhd1L/bhL5D3YZE333AmAU10N3tprYM+P KsKDU+CYadabdQS2qLq8OAoOO/4m3WdwOgTWmLd4xu9A7YgaeK77wqH7/p4X+MLTjWdwz5gP j+UKPO4NsFCV91+oQ9+IeTADrcoJ8gewXvNCF80LXTT/52oBXgFWs2lyqYSVhyezX4XKxVJ5 WrIkdF+K1AiW/nbPYtdsMzg3NRPaDjAuaAeQiwtX8NsFiRIBP0F8OIOVpXwuS0ti5e0giEsI V/NFCetYAS0Rp7IHWfYQK3uuYlyfwExsa1n53er0E30zaYMZ25yrtu9XfFreEfx25sffxp3/ pMw3+9bl+nb7qD7M1ma5uNh5XvDN3rEnkUF15ZvyTOUnR0Wczr6Q08aivIyYuvqIh/v3KOem aj8I6lkZpO4XajYFxvxRm2/cdVt4Z2rYsi8ty2+hz/pGvP+9HSN/VQ69bI7I/zIu6Frp2of5 /Xxn8Yd2i1Wh3rn51mctr8t3iw/roieiwkNElwrf33G14OBG7Mgu/bvSN7cPfvTK3l5NTupQ 9dZSKe/O9/cvLh4de+kns+5BVuEGNTZ7uyI+nPcdUouiVxW8Ot+mD1jpivKrkmyMXWNdb6+P CnS5gu9iBK3Nexa8R4J6hIT8gDj8NVwmF/8LFwOxyEoEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7qfYjPTDbofCFmcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DL2L9rJlPBao6K8+eWszUwNrN3MXJySAiYSFx42sXYxcjFISSwlFGi/0w/ G0RCRuJa90sWCFtY4s+1LjaIoleMEi8+zGAFSbAJGEk8WD4fzBYRWMwisXdfJUgRs8BbRonr MzeCdQsL+EscnvuTEcRmEVCV2LThGJjNK+Ag8WTNMWaIDfIS+w+eBbM5geJrum6A1QgJ2Ev8 O/WBDaJeUOLkzCdgM5mB6pu3zmaewCgwC0lqFpLUAkamVYwiqaXFuem5xYZ6xYm5xaV56XrJ +bmbGIEJZtuxn5t3MM579VHvECMTB+MhRgkOZiUR3kNCmelCvCmJlVWpRfnxRaU5qcWHGE2B 7p7ILCWanA9McXkl8YZmBqaGJmaWBqaWZsZK4rxul8+nCQmkJ5akZqemFqQWwfQxcXBKNTCZ O7nN3fHBf3KFzOtsr5NvC0Lb/6312DDn1xZ91w0T37MU7tIS2/3KuK/3g+zautropNU1W1dy 9+QG7VLdzhLS0y76JOldHEPr/otS1zeF7ltesl4yaZEPq6DF5kkHJOw73hjN+hY4M5bLZ451 5cQ8pUynCX+c3f/ItzFmXbI5XrjS117vEMOZ5zfuLVZ22S1zNLasuecQ3/nnJ/tzG93CnN4L 7vWcxH2Bc1dKy27HpzL79FMyhBkfTFBd+HnthdsnWG+FWjw7m+QVc5Dt1fJNGzcnTmqMZYnq 2ixt2TVxXtleCf2tW/91LJdx8JqZrntMz3Xh2y1HmwM8pH/9iBR6ULvizppU+9P//svsL1VT YinOSDTUYi4qTgQAOKNO7LkDAAA= X-CMS-MailID: 20241223125618eucas1p2ad4887b41bb99a9ebbd0b8c2e2aa4af4 X-Msg-Generator: CA X-RootMTR: 20241223125618eucas1p2ad4887b41bb99a9ebbd0b8c2e2aa4af4 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125618eucas1p2ad4887b41bb99a9ebbd0b8c2e2aa4af4 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The IMG BXM-4-64 GPU is integrated into the T-Head TH1520 SoC. This commit adds the compatible string "img,img-bxm" to the device tree match table in the drm/imagination driver, enabling support for this GPU. By including this GPU in the compatible devices list, the driver can initialize and manage the BXM-4-64 GPU on the TH1520 SoC, providing graphics acceleration capabilities upstream. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c index 85ee9abd1811..91af060bb3e0 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1475,6 +1475,7 @@ static void pvr_remove(struct platform_device *plat_dev) static const struct of_device_id dt_match[] = { { .compatible = "img,img-axe", .data = NULL }, + { .compatible = "img,img-bxm", .data = NULL }, {} }; MODULE_DEVICE_TABLE(of, dt_match); From patchwork Mon Dec 23 12:55:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918804 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2C271B21BA for ; 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Mon, 23 Dec 2024 12:56:18 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 14/19] drm/imagination: Enable PowerVR driver for RISC-V Date: Mon, 23 Dec 2024 13:55:48 +0100 Message-Id: <20241223125553.3527812-15-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sa0xbZRjH855zes6hW+FQiHsd4JCkU0HLhsS9TtQtbubsk9u+kMzM2YyT gpaCLZ2CDsa4jEu5TTakg5WNOaDAiNyEZojcWhBWudiCSWFMwa6IMqAQwMCka5379nv+z/95 /8+TvDQu/J7cTcfIEziFXCILIvlEq2Hd9JrjdIx0X/HaDtQ/fhNDLf9oKFTXYcKQttfEQ1Oj zRj6ZWWBRHdmhyn0sCOVQJbqcgqlGRpIZNdMkWhRPcVDY/oyEi3n9QLUupxOovreSQo1rGgx dGOxhUC32vQAZWbf5qGRn46iyal+AtnH1DjK1Hihx3fbKLRl+Y5A1/7upFDzfBEPGesjUXpn MXHoBXZhIoNi5+12gu3JclBsx2oFwbZrJilW3T4E2EZdNslaLXdJ9vrACfZ+rhFjm26lsOn1 Bowt2NzHLvxgJtn8Zh1gR9PGqePCU/yIKE4Wc45ThL7zMT/6R/0SFq+nvyia2cQvgEtUDvCg IRMOC68ObzOfFjLVAP5uKHEXDgANK2bCVSwD+Gf/+NMRW0ml21UFoLlqwO2aB7DC2kg6XSQT BqertDxnw5fJIGBGXypwFjhjA7B1pmzbRdM+zAn4zSOec4BgRLCnbwVzsoA5BKfHJoArbg/s 7LqHO9ljW6/LcekCxhsOlM4QTsa3PWkt13Dn+5Cp4cOLU4/dw0fgau19994+cM7Y7GZ/OPi1 mnBxHJxuWcJd/BVsVxvd/Ba0mjae7Ikzr8AGfahLPgxHzE1PZMh4wom/vF0reMLLrSW4SxbA rEyhy70XXlHnPQ01VbdiLmbh9VEtVQhe1DxzjOaZYzT/51YAXAd2cSplrJRTvi7nPhcrJbFK lVwqPhsX2wi2//bglnGlDVTPLYq7AUaDbgBpPMhX0C2MkQoFUZLEJE4Rd0ahknHKbuBHE0G7 BKKoPZyQkUoSuE85Lp5T/NfFaI/dF7AWQCdHJ1z5bePBtzWNi4pAP9MnpW17h4IrLyUf6ZN2 KOMsB5Wlso0Cv62XVu2JvuYP5RvnUh23sy7SP697/jFXVmsthJaR3qaEdf1ObaI2MnR2x/Cr b3/Qu2E96f/QkfZyXrLXRJLn8vn3Dgj1wZqu4/05Oktmbg/Y+aBBGiEO7BLZPA+mGjbvFdcd jpgN5EI/UwWIwgOevxG/qLOPZTYZf1U9Wq2fP2p+biipyWZbyynKb+4vLz+rSMkdqDkQ8FF4 6umQd48VyGt9agpCVCOTS5e90s+IUyoH76C198Wy6JA3JkoUomyu29+azEQeC58My/dGb0p0 X9r2V0JF2KnzQYQyWrI/GFcoJf8Cv0iVrkoEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7qfYzPTDZ5M1bA4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXcWDXJ6aCXRwVE5/8ZW5gbGfvYuTkkBAwkXg+fTGQzcUhJLCUUeLu7ePM EAkZiWvdL1kgbGGJP9e62CCKXjFKPJm3lBUkwSZgJPFg+XwwW0RgMYvE3n2VIEXMAm8ZJa7P 3AjWLSzgL3H+w06wdSwCqhKHj35lArF5BRwkHly+wQixQV5i/8GzYJs5geJruiDiQgL2Ev9O fWCDqBeUODnzCdhMZqD65q2zmScwCsxCkpqFJLWAkWkVo0hqaXFuem6xoV5xYm5xaV66XnJ+ 7iZGYILZduzn5h2M81591DvEyMTBeIhRgoNZSYT3kFBmuhBvSmJlVWpRfnxRaU5q8SFGU6C7 JzJLiSbnA1NcXkm8oZmBqaGJmaWBqaWZsZI4r9vl82lCAumJJanZqakFqUUwfUwcnFINTK3s m8K9g6b9UOJm9U6cbFzGdkInsvqDsa3mvNAPix89ZtmSdu6uwINpPbdLa6aubZyXHqG66e41 qbQTyxojQ9unXJRafVLWkMU9oXu/WonzTmZ1ppA4j3O5EhyXTntt5L7tu/zX1cSN28QvWb04 doMvd/aXI1NZahSdjRdPO/1pxvG0r80CtQ9TrasYc5tyrwhNbdNin7dUz/iiWFOb6muGlY7z NotKmx54pxdb0MNnVvMgK6Nr+/oLij327YX2t7iPXWL9kcWR6J20ruPC3ut7nr8psVPMaWks vaPfpnhtfo2dac4Sz3Bf76n7bf48i2lhjnpxcolgdlDHFRuxcqGNcQfC/5R6WeTr2jArsRRn JBpqMRcVJwIAdjCs2bkDAAA= X-CMS-MailID: 20241223125619eucas1p1f9c4afd9b4f458ab92750e0526c95581 X-Msg-Generator: CA X-RootMTR: 20241223125619eucas1p1f9c4afd9b4f458ab92750e0526c95581 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125619eucas1p1f9c4afd9b4f458ab92750e0526c95581 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 3bfa2ac212dc..5f218896114c 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,7 +3,7 @@ config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Graphics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM select DRM_EXEC From patchwork Mon Dec 23 12:55:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918806 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1F111BCA19 for ; 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Mon, 23 Dec 2024 12:56:19 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 15/19] riscv: dts: thead: Extend device tree clk with VO reg Date: Mon, 23 Dec 2024 13:55:49 +0100 Message-Id: <20241223125553.3527812-16-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxbVRjGc+69vfe22O1SphwZEUfCIpox5lxydK6ZBMzddIsLM0Si0So3 BQdltsVthmRAgRQoQ0EmFirModQ6xhjQUFxpKB8dQztGR2EDypx82MogwFg2DEPKRd1/v/M8 73Pe9z05NC5pIUPoFIWaUypkqeGkiDD3PHLuWPogRR5dYAxFV4e+x1DL33oKXbA6MVTd5RQg z0Azhm4uzZHo4mQ/hf60ZhPIbTRQSNPTQCKv3kOieZ1HgFxtVSRaLO4CyLyYS6L6rjEKNSxV Y+jcfAuBalvbAMov+FGAblyLQ2OeqwTyunQ4ytdvRqtXWin02N1IoMpZG4WaZ74SIEd9Asq1 fU3sf46dG86j2Bmvl2A7tfcp1vqghmAt+jGK1Vl+BexlUwHJjrqvkOx3vUfY8SIHxjbVnmZz 63swtmQlmp1rHyTZM80mwA5ohqh3JImi15O41JTPOeVO6Uei5OmROuy4gTrpnGmissCCoBAI aci8Akcu6rBCIKIljBHAilkP5TckzH0Aa3NO8MYigN2/OMhCQK8nvDczeb0OwNXyHMAfZgBc HLeR/jTJvAzv1FUL/MYWJo+Aed3Z61U4Mw2geaJq/aog5l34+/UEf4BgIqDbpl0Pi5n9cGrl NsXPFwZtHb/hfhau6RcKhwFfEwh7v50g/Iyv1WhaKnH//ZBpFMGyoo6NcCycqTy7wUHQ52je 4FDYV6YjeE6Hd1oWcJ4zoUXn2OC9cNS5vD4nzkTChradvPwGLF+xC/iX2ASH7wXyI2yCpeZv cF4WQ22+hK/eDst1xf81dRrNGM8sXNK7wZdgm/6JZfRPLKP/v28NwE0gmMtQpck51S4FdyJK JUtTZSjkUZ+kp10Gaz+777FjoRUYfPNRdoDRwA4gjYdvEdslKXKJOEl26gtOmf6hMiOVU9nB VpoIDxZHJIVxEkYuU3PHOO44p/zXxWhhSBaWn3wgVhj5Pl3y0lMr+8piLFmHoj2yR5Hk3We9 o0r7z4FHRP3b9hw9ey84/tKtxEO2EHlx9gtx8eeqOsTS3LnXuMGH4hpXGVPN5gTNifr7ig63 ZsRrlrmD+x6ejHm6ApcugYDk0tm/JEZjhfnS5O3Nz5zZ4ZL78qVbS917ym6pwgxTjZ/1lnhV JnHA4YT+3b67SSnT8I+YY9oRaeB8bI5avXyqPZWqT1gVT2nrfhjpPn/aZBl8K9znbfde6zz6 sXX11dQJ19uSOClt1UwKHsTObxeuvlmb+NPQuFdNmqgBRYcBhX46srtTbjgvf2/UKo5osrum 914/4AxYyCy68XxyOKFKlu16EVeqZP8Aj2OFO0gEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7pfYzPTDW5eZbY4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX8fz2cqaCuewV595sZm9g/MTaxcjBISFgIvHySk0XIxeHkMBSRol7Z64z dzFyAsVlJK51v2SBsIUl/lzrYoMoesUocWzzBXaQBJuAkcSD5fNZQWwRgcUsEnv3VYIUMQu8 ZZS4PnMjWLewQLDEpL4zYA0sAqoS1/Z3sIHYvAIOEs/+3mKH2CAvsf/gWbDNnEDxNV03GEFs IQF7iX+nPkDVC0qcnPkEbCYzUH3z1tnMExgFZiFJzUKSWsDItIpRJLW0ODc9t9hIrzgxt7g0 L10vOT93EyMwvWw79nPLDsaVrz7qHWJk4mA8xCjBwawkwntIKDNdiDclsbIqtSg/vqg0J7X4 EKMp0N0TmaVEk/OBCS6vJN7QzMDU0MTM0sDU0sxYSZyX7cr5NCGB9MSS1OzU1ILUIpg+Jg5O qQYmd18xpVwV4fW7uabviiq6ft950fwHe6dcaJZOds81uL5kraXuhO92NnzH12fMPKFvP2Pt apE17G/EK5+H35P1sNl+ftkSrpK+d4+Z/W+s/6cmPr/Y+pbSTJWEgFVfn9q43fn74Lhe4jvV UOe91522Cgaz2JadYQ8V33njs9Nj4VVq+yte9PGvZtW4alX/f9d7s5IqB4cJ3q77Dl16u+FH wJ1Fyef38KblPj/EWyscuWfezETTn58mOrXkF/XfeDqhO6B2Rcr8e+3qq1hf/GScHF2TaG/+ dK/JzUvCnc9PnP//3vOXwg93W7mKh5ODL6/vDHZzKlb0YMnRfbir4ANzzpu2pzfrAuo37mZJ aNtmqcRSnJFoqMVcVJwIAJkrhoi4AwAA X-CMS-MailID: 20241223125621eucas1p17ecf251c74bc60e69323afe1ffc0c8fb X-Msg-Generator: CA X-RootMTR: 20241223125621eucas1p17ecf251c74bc60e69323afe1ffc0c8fb X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125621eucas1p17ecf251c74bc60e69323afe1ffc0c8fb References: <20241223125553.3527812-1-m.wilczynski@samsung.com> VO clocks reside in a different address space from the AP clocks on the T-HEAD SoC. Extend the device tree node of a clock-controller to handle VO address space as well. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index acfe030e803a..d823b6da75df 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -484,7 +484,9 @@ uart2: serial@ffec010000 { clk: clock-controller@ffef010000 { compatible = "thead,th1520-clk-ap"; - reg = <0xff 0xef010000 0x0 0x1000>; + reg = <0xff 0xef010000 0x0 0x1000>, + <0xff 0xef528050 0x0 0xfb0>; + reg-names = "ap-clks", "vo-clks"; clocks = <&osc>; #clock-cells = <1>; }; From patchwork Mon Dec 23 12:55:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918807 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D6A81C07FC for ; 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Mon, 23 Dec 2024 12:56:21 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski , Drew Fustini Subject: [RFC PATCH v2 16/19] riscv: dts: thead: Add mailbox node Date: Mon, 23 Dec 2024 13:55:50 +0100 Message-Id: <20241223125553.3527812-17-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTZxTG9957e++lruxSXHyHWxiNujgzkEXMm00XyNTczIThzOJkbtDJ TWmAgi0gY27A+Ah0lTEoMAqVigxIpSLIt1QmshZ04ETkY0LFTFZhVORzEzI2ysXN/57znN95 n3OSl8bFl0kPWq6I5ZQKaaSEFBKNlic33/jzE7lsZ0kTgboGyzDUsKyjULW5F0Olnb0C9GNb LLL11WOof2GaRBfGf6HQQ3MKgQaq9BRKtdSQaEJnI9GMxiZAt1tLSDR3uhOgxrk0Epk6RylU s1CKobMzDQQqb24FKCOrQoBuXd+PRm1dBJq4rcFRhu4F9E9bM4VWBmoJVPyonUL1U98JkNV0 BKW1awl/T3Z6KJ1ipyYmCPZa5jzFmhcNBNuiG6VYTcvPgK0zZpHsyEAbyZ7pPsTe+8aKsZfK k9g0kwVjv/17Jzt95Q7JZtcbAduXOkgFuQcL94RxkfJ4TunzTqgwPFv7FxHzWJiwUDgoSAZ2 Wg1caMjsgsbxFEINhLSYqQLQPj2P88U8gN35VuCkxMwcgFdr/Z5OpI11rUOVAC7cKxDwxRSA 5mw95qRI5k04Vlm61tjIpBMw/acU4CxwJgeDZQNncCflzgTAO9aCNU0wW+Fy93mBU4sYf9j8 q4Xi8zxh+9WeNcZl1a9WDwGecYPdRQ8Ip8ZXmdSG4rWdINMihHrDBYIf3ge7ei4LeO0OJ631 64++DG/kadaZaDjWMIvz+hRs0VjX9dtwpHeJVAN6NWA7rGn14e0A+CBLv2ZDxhUOOdz4FVxh bmMhztsimJkh5ultMF9z+r/Q3qpGjNcsnLCrsRzgpXvmGN0zx+j+zzUA3Ag2cXGqKBmn8lVw J71V0ihVnELmfTw6qg6s/u8bK9bZZqCfnPHuABgNOgCkcclGUYdYLhOLwqSfJ3LK6BBlXCSn 6gCbaUKySbQ1zJMTMzJpLBfBcTGc8mkXo108krEi3fCOUOC9TZsQOhIkKri54cR4+dCe5fj7 OWWld+tyYGrh9uQSxe6oLW7PXd/1xwcx7/82/kOp6KvAgC8SRhfJt7KncxP3fhSyHFgV/S5p OJo72/NZiO+B/g37qrmkWxWnEhw+lYGXmo69Gpp3McDvNV9z/0hbrDzx6xcX54OLVPbQc8XD PUGHLEsXa7RLpvYV48EIL4/K6i/TH/WnA2WFq6O497CWOvnerD3Q5kZr5U2bRXlhRJNfRMlM j6PvpcmHB5ryj0h8d+/PN2R5HfO8/3vezMePTXsZ/xyy9pUPmxVP0LXzJz4dtoZ9b7oSHP88 d7TO/7j8sEd1/g4p7sgMP3c3qVBCqMKlvq/jSpX0X1usyE1OBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFKsWRmVeSWpSXmKPExsVy+t/xe7rfYjPTDZauVrU4cX0Rk8XW37PY LdbsPcdkMf/IOVaLA3tKLO5d2sJkceXrezaLdU8vsFu82NvIYnFtxVx2i+Zj69ksXs66x2bx seceq8XlXXPYLD73HmG02Pa5hc1i7ZG77Bbrv85nslj4cSuLxZIduxgt2jqXsVpcPOVqcffe CRaLl5d7mC3aZvFb/N+zg93i37WNLBaz3+1nt9jyZiKrxfG14RYt+6ewOMh7vL/Ryu7x5uVL Fo/DHV/YPfZ+W8DisXPWXXaPnp1nGD02repk87hzbQ+bx7yTgR73u48zeWxeUu/RsvYYk0f/ XwOP9/uusnn0bVnF6HGp+Tp7gHCUnk1RfmlJqkJGfnGJrVK0oYWRnqGlhZ6RiaWeobF5rJWR qZK+nU1Kak5mWWqRvl2CXkbflB8sBR+4Kr5Ov87awPico4uRk0NCwESi5cEJ5i5GLg4hgaWM EpfnHWSESMhIXOt+yQJhC0v8udbFBlH0ilHiwMmDTCAJNgEjiQfL57OC2CICi1kk9u6rBCli FpjBJLHn+RWwScICjhJXj09jBrFZBFQlfp9cDdbAK+AgsePWMXaIDfIS+w+eBavhBIqv6boB 1iskYC/x79QHNoh6QYmTM5+AXcQMVN+8dTbzBEaBWUhSs5CkFjAyrWIUSS0tzk3PLTbSK07M LS7NS9dLzs/dxAhMNNuO/dyyg3Hlq496hxiZOBgPMUpwMCuJ8B4SykwX4k1JrKxKLcqPLyrN SS0+xGgKdPdEZinR5HxgqssriTc0MzA1NDGzNDC1NDNWEudlu3I+TUggPbEkNTs1tSC1CKaP iYNTqoGpSUM1d9H/2XmPnzdsZzpr9cKxX/LKLyfXHbcvOMQv0LoqqiL0735MYav3n5io8A7t DZFHK74xpabkPz0z27bm3QoXY63V3xbOfrN/9sN0tVzW5eaZrqbNV/bc1fP4cj2tN72ilOPn N243HrV327SWh6hL7/woy+u+7K9Q8IqTf/jMfq1f+fB8IdcJDfsL5ZEC1ZOXpT/kOPBh17uu ZfFmfhxf467EnNrTtnJ90+m2s+5nVs8VWbbr+5Oy35/TH3BNSy2MuzalZp/I8Xre/0pWrb/b tzz8tPHVn611cy2tp/1gm2p4fs+mo13zLfzufNnI9eBnWcmkLUsO/3wVNe30SUvpvQ9cYyTz OkvvHCya3qvEUpyRaKjFXFScCACbfIuSvQMAAA== X-CMS-MailID: 20241223125622eucas1p18f67a49dd69b93f0e7770e12b95ceb77 X-Msg-Generator: CA X-RootMTR: 20241223125622eucas1p18f67a49dd69b93f0e7770e12b95ceb77 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125622eucas1p18f67a49dd69b93f0e7770e12b95ceb77 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Add mailbox device tree node. This work is based on the vendor kernel [1]. Link: https://github.com/revyos/thead-kernel.git [1] Reviewed-by: Drew Fustini Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d823b6da75df..0993de0cdd44 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -601,6 +601,22 @@ timer7: timer@ffffc3303c { status = "disabled"; }; + mbox_910t: mailbox@ffffc38000 { + compatible = "thead,th1520-mbox"; + reg = <0xff 0xffc38000 0x0 0x6000>, + <0xff 0xffc40000 0x0 0x6000>, + <0xff 0xffc4c000 0x0 0x2000>, + <0xff 0xffc54000 0x0 0x2000>; + reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; + clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, + <&clk CLK_MBOX3>; + clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", + "clk-remote-icu2"; + interrupt-parent = <&plic>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 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Mon, 23 Dec 2024 12:56:24 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20241223125624eusmtrp1124a03bf8da2633b53cbea692959bcef~Tz6Pg-og12059320593eusmtrp1X; Mon, 23 Dec 2024 12:56:24 +0000 (GMT) X-AuditID: cbfec7f2-b09c370000005155-ae-67695df8b0f6 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 08.04.19920.8FD59676; Mon, 23 Dec 2024 12:56:24 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241223125622eusmtip2fbbb647a5c6dde66ff718aa7a1fd23f6~Tz6OE7vgZ3149631496eusmtip2H; Mon, 23 Dec 2024 12:56:22 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 17/19] riscv: dts: thead: Introduce power domain nodes with aon firmware Date: Mon, 23 Dec 2024 13:55:51 +0100 Message-Id: <20241223125553.3527812-18-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se1BUZRjG5zvn7Dlnt8DDyug3xGXaJGed4uLUzEdaUWN1bDTULMcmrR04 7iK3nV0JdKxALiIuN5PbggJKgbRAwLIBcYmNq8AmSy5MyuI4oguRtAKFGUssB8v/fs/7Pu/3 Pu/MR+NiA+lBh0cf41TRskgJKSIMPQ9NLy4eCpcHTJukqG/0EoYaH2kppGszYaikyyRAVrMe Q78szJKoZvIahWxtiQSyVF6gUFJPLYmmtFYS2TVWARppKSbRXEYXQIa5ZBJVd41TqHahBENl 9kYClTe1AJR65hsBGr76Fhq39hFoakSDo1TtOrTc2kQhh6WOQEX3Oyikn8kRoN7qAyi54zwR 7M3OjqVQ7MzUFMH+lDZPsW1/lhJss3acYjXNg4CtrzpDsjctrSR7sX8vO3G2F2Mbyr9kk6t7 MDZrKYCdbb9Ospn6KsCak0apPeKPRNvDuMjwzziV/2ufihTdN7IoZb0ovqjHRiWANjodCGnI vAQH6yxUOhDRYqYSwInlBJwX8wAW1+hIXsytiByD4PFIck/RWqMCwLMaHeDFDIBXrK2U00Uy W+GtihKBs+HOpBAwpTtx1YUz9wA03Clemafp9YwMpuVvdg4QjC8svHYKONmFCYbduaM4v84H dnQOrbJwpa5LH1vzuMH+wjuEk/EVT1Jj0WpwyFwRwc6lH0l+eAdcGk5Zy70eTvfqKZ494cBX GoLnGHir8cHaspOwWdO7xtvgTdPfqzlxRgprW/ydCJk3YJ8tnkdXOPa7G5/AFZ4z5ON82QWm pYr5N56HuZqM/3aaKg0Yzyw0J47i2eBZ7RO3aJ+4Rfv/2lKAV4GNXKw6Ss6pA6O5OD+1LEod Gy33C42JqgcrX3vA0fugCVyYtvsZAUYDI4A0LnF3MYrD5WKXMNnxE5wq5hNVbCSnNoJnaEKy 0cU3zIcTM3LZMS6C45Sc6nEXo4UeCdiBI1tvpGyP+22/zaPGzVGomvCweGe8sHenktzT9749 e520dH+q8dLBqWD1kd1BxsH7QQGfKySNVo/MhMlmL2UoF75Bcfvl9IK8d/0fFQY8fUKaYC/n jPu+9fLVO4YbovQ7KtSbfGotcVl1fzzVfrtAGD/06ndBwo+F0D2k7/DuH67eFRREFmlaL/+T nbtYGtKvZrZtiPTURTiW648WHH949y86hys/WLNo+9Vc9nreF/T8wMK5Vw59ELxJEdi86+t7 32OHA99W6vKHylwjTiqljGfmc3nZpyeXduWyXm+GhiiouIb2zvNWyVHv61vsI66O9+I/3Bcz nJ/XNaww234+ffHUznckhFohC9yCq9SyfwEtFZeKSQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7o/YjPTDd7M57A4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXcfR2P3vBJq6K2cdesDcw7uXoYuTkkBAwkWg5Nputi5GLQ0hgKaPEhx9n GSESMhLXul+yQNjCEn+udUEVvWKUWHNsMStIgk3ASOLB8vlgtojAYhaJvfsqQYqYBd4ySlyf uRGsW1ggXmLb4itgU1kEVCVmXmgCs3kFHCSOTr3ODLFBXmL/wbNgNidQfE3XDbAaIQF7iX+n PrBB1AtKnJz5BGwmM1B989bZzBMYBWYhSc1CklrAyLSKUSS1tDg3PbfYUK84Mbe4NC9dLzk/ dxMjMMFsO/Zz8w7Gea8+6h1iZOJgPMQowcGsJMJ7SCgzXYg3JbGyKrUoP76oNCe1+BCjKdDd E5mlRJPzgSkuryTe0MzA1NDEzNLA1NLMWEmc1+3y+TQhgfTEktTs1NSC1CKYPiYOTqkGpuRr sn07HC76tOwIsecqTTob+UJl+5MNW16bVqctd59veS5MMrSCh7OXaZ9S9sa5ro7e31XV3XLP v5RS/FK9SfWX4s6pb5w2ea9k+bOJnan+1BW5KaJcSdEz135XuMPAfFFxqliS1JQDGX7V56Ji Xu94V2j4y1vR1MDp55Rm0469Im3FNxk/6bJKOen+0vg3+2HzTFbh+8tMVYRfRZ09+bxp4qqd ieZldzInnT1SwbPjaWRot5TYuhmNXL/WsfQlylWttdss0qXbZRTYYbGwlFFcRla/ZqNBWNa7 E5O8TA33VXZ/NbCUcdp58o7H1AtGh09vuBj/6cx99wTvxuIT3/fHXJCLOFBqrBt84edDJZbi jERDLeai4kQA3Yth+7kDAAA= X-CMS-MailID: 20241223125624eucas1p217e1756d45cfb39429c7a4543a84d7f2 X-Msg-Generator: CA X-RootMTR: 20241223125624eucas1p217e1756d45cfb39429c7a4543a84d7f2 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125624eucas1p217e1756d45cfb39429c7a4543a84d7f2 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> The DRM Imagination GPU requires a power-domain driver. In the T-HEAD TH1520 SoC implements power management capabilities through the E902 core, which can be communicated with through the mailbox, using firmware protocol. Add AON node, as a parent for the power-domain controller. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 0993de0cdd44..d4090074fd27 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "thead,th1520"; @@ -229,6 +230,19 @@ stmmac_axi_config: stmmac-axi-config { snps,blen = <0 0 64 32 0 0 0>; }; + firmware { + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + + pd: power-domain { + compatible = "thead,th1520-pd"; + #power-domain-cells = <1>; + }; + }; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; From patchwork Mon Dec 23 12:55:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918809 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3EB31C5F05 for ; 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Mon, 23 Dec 2024 12:56:24 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 18/19] riscv: dts: thead: Introduce reset controller node Date: Mon, 23 Dec 2024 13:55:52 +0100 Message-Id: <20241223125553.3527812-19-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xTVxzOuff23kvD41rYOIFlClHn5gBxMk7iXMDIdo1jCswNXBZtxk1l 8tBWhlvcwPAQsMwHLIvlUeeqVNKOx9paiIBWpCDQbLyVh0wRLK/ykk0ZsMLFzf++8z1+3++X HBoX6UkPOib+OCeNF8d6k0LCUP/M4vPsixjJFn16IGrouowh/byCQppqC4aUdRYB6m/VYaj9 qY1Evz7+nUJPqk8RqFNdSKHU+lISWRX9JJqS9wtQW1UBiWZy6gAyzKSRSFvXR6HSp0oM/Tyl J5DKWAVQRtZVAfrjbgjq628gkLVNjqMMhQtaumGk0GJnOYHyJ2oppBs7L0Bm7WcorTaPCHqd tXWnU+yY1UqwtzNnKbZ67hLBVir6KFZe2QzYipIsku3tvEGyRY1h7IMzZoz9TZXMpmnrMfbs whbWVtNBsj/oSgDbmtpF7RMdEL4XzcXGfM1J/d4/JDysurKEHx2mT5R1uKYALZUNHGjIbIN/ 2bIE2UBIixg1gCW/zAqWBREzC6A57xgvzAD4uPkC/iLx8PwY4IViAIfapkn+MQbgo5Q/sWUX yWyFA8XKlbluTDoB0++cWongzDCAhsECctnlyoRDfU4zsYwJZgNMb1eudDgxQfDOGaOA71sL a2+1rPAOdl6T3Q14zxrYeHFwJYvbPan6/NX9tEJYcMuFx7tgv3oc8NgVjph1q1e/Bpty5QSP E+CAfno1exJWys2reDvstTy370nb578JS6v8eDoY/p1RLFimIeMMu8fX8Bs4wwuGn3CedoKZ GSLevRH+KM/5r9SiNmA8ZqFBU4OfA16Kl25RvHSL4v/eSwAvAe5coixOwsn847kkX5k4TpYY L/H9MiGuAth/dtOiedoICkemfE0Ao4EJQBr3dnMyiWIkIqdo8TffctKEg9LEWE5mAp404e3u tCF6LSdiJOLj3BGOO8pJX6gY7eCRgoUNtUygTwsdomc2jx+pVa/zpAP+GXH1zA+8hiVeCR0k DrzakuvqGBnqNVnssnNbJBkc9X2S2z2ux/l+UGby5/PGnGPvTipVe3uuSq77a+Y7en18BkQm VZKfe4+pGgvz6P6k4eGseDTcc2JpdDHPPLTr5t0dm3qGQoo+iD2ZG3F6t0JzWbs+sNMabgnR zIyeC7rXpXmwP3PJK4CN/Op+ZaS5KTNq+HZjcvkbWz+cUyoiLka3frfHtyzg+uly6Bt1om3h lZ3qibB1nrsPLbR/vCPL5wmz5+bBazrbZseU8SWX7XstjpKPYFlw6ORQX41t8NHbRRV1tfsr BuY2Ee+sjzA+J4qF3oTssNj/LVwqE/8LcV+ZtkgEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xe7o/YzPTDaZOl7U4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CXsWTpf+aC5xwVG64KNzCuZe9i5OSQEDCReDTxDWMXIxeHkMBSRolXT84y QSRkJK51v2SBsIUl/lzrYoMoesUoMamzF6yITcBI4sHy+awgtojAYhaJvfsqQYqYBd4ySlyf uRGsW1ggQGLqpimMIDaLgKpE65X5zCA2r4CDxNHuHawQG+Ql9h88CxbnBIqv6boBVi8kYC/x 79QHNoh6QYmTM5+AzWQGqm/eOpt5AqPALCSpWUhSCxiZVjGKpJYW56bnFhvpFSfmFpfmpesl 5+duYgSml23Hfm7Zwbjy1Ue9Q4xMHIyHGCU4mJVEeA8JZaYL8aYkVlalFuXHF5XmpBYfYjQF unsis5Rocj4wweWVxBuaGZgamphZGphamhkrifOyXTmfJiSQnliSmp2aWpBaBNPHxMEp1cC0 uEpCYUJuKN+6i9ON+H9vTFrw6DzTJC5BIY72zbOOc7CtlFnz/GND1cya2uWaXxZet7qnECW8 iWnf6VkKhdv11YXvBZSsnLXcs+ivSvdSI54zwndY/F7Y7dW98rTqyEbxaQlv86b/Xl1S4t+u ekXhA3vzt7/7fONe6PFkLCk9dH5G7wOXykXW7ySKQ4OPTBDrXMArZqH6r82biZ/7vGav2pF3 kdtVM2+w/r4R5JZaPt2mTWGBz9T0dy+/n25g/d26+cbO8gebNdSj7uYwhNxP+xOeNaXyrlPh dpW2dd63Z1S7vUmNn3+2pMI50vTv25rrza9bmLWMedtKNi7evkVrzgzNqSkrmP8rKRs1PEhU YinOSDTUYi4qTgQAEU9Hc7gDAAA= X-CMS-MailID: 20241223125625eucas1p2ffc3f2d8fd13bd71550ebed4e901b7de X-Msg-Generator: CA X-RootMTR: 20241223125625eucas1p2ffc3f2d8fd13bd71550ebed4e901b7de X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125625eucas1p2ffc3f2d8fd13bd71550ebed4e901b7de References: <20241223125553.3527812-1-m.wilczynski@samsung.com> T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part of the power-up sequence. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d4090074fd27..c6fe2ea3197d 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "thead,th1520"; @@ -505,6 +506,12 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x4f>; + #reset-cells = <1>; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; From patchwork Mon Dec 23 12:55:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13918810 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AEFC1CDA02 for ; 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Mon, 23 Dec 2024 12:56:25 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 19/19] riscv: dts: thead: Add GPU node to TH1520 device tree Date: Mon, 23 Dec 2024 13:55:53 +0100 Message-Id: <20241223125553.3527812-20-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241223125553.3527812-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sf1CTdRi/7/u+e9+X2ebr8PJ7mpIr7OwHIpV9u0rmCfXecRdEaV0cxa69 ty35oZtkeVxKMG7AQEESGSAQxI8JkTAW7IAFEcOsmZhIBAM7iiCQ2ABBwcV4pfzv8/k8n+f5 PM/dQ+OSb8jNtDr+KKeJl8dKSSFh6V50PHM3Wq0M/PtPKeq58QWGmu4aKVTb5sBQSZdDgJy9 Zgz9MjdNoq/++JlCf7UlE6ivuphCKd31JBo3Okk0Y3AK0DVrEYncWV0AWdypJKrrGqJQ/VwJ hspmmghU0WwFKC29UoCu/hCKhpw9BBq/ZsBRmnE98rQ2U+he30UCFd6yUcg8mSNA9rq3Uaot j5BtY6f7dRQ7OT5OsN/pZym2bb6UYFuMQxRraPkRsA2mdJId7Gsl2fOX3mCHM+0Y21hxgk2t 68bYU8uB7HT7dZLNNpsA25tyg4qQvCt8WcHFqj/iNLv2xghV+oYa8rBH+LFtYRQ7CZboDOBD Q+Y5WL5UJsgAQlrCVAM4PmAheTILYM2Um+KJG8CUcznkWku+ca1QBaDDdQXnySSArvZi3Osi mSA4UlWyOngjoyOg7vtk4CU4MwagZbRodZYvcwDaqvMpLyYYf5hdPLzaLWJkcObrsxif5wdt HT+t6j4rem1GP+A9G+ClglHCi/EVT0pT4eoakKkTQt1E6f3mENhi0wEe+8IJu5ni8SPw8hkD weMEONLkwnmcBFsM9vv4JTjouLOyKL0SsBPWW3fx8j444M6jvDJkxLB/agO/ghjmWvJxXhZB fZqEd++Anxuy/gt1VFsw3sLCjvMRp8F24wO3GB+4xfh/bCnATWATl6iNU3LaoHjuWIBWHqdN jFcGfJAQ1wBWfvvyPftsM6iamAnoBBgNOgGkcelGUadErZSIFPJPjnOahPc1ibGcthNsoQnp JpG/wo+TMEr5Ue4Qxx3mNGtVjPbZfBIzX4hsd1lHf9/yyrehN9veuz2j+E3cGCJWmzIXzn6Z XHvhQ1n0PEOFKawDvbvljSdeKEtPHjK59ohU4rFI4bO3VMJ3staFl4zkjAmeL4oVSLYJPl2K cciqqgdVN3utIQqXfjnpqufQZ7pCsmDrm7X0Dk9FQF5QlFh1p3Ii7VXnqXC/8JrWqfhBfc/p vRHSrWG+jz/2RFy73/7gA1nlx0ZiogKlT8msR6bt2HISWlzn7rn+cOXBMqJgPvKiK7hheN9B 07nQNGXpkejbg6P+0tdH5j0RvwbXxTy907XfcuXRtxLxofXZ+iVxbtRrHXP/ZFYuHDdLhC/u aex+aDF1u6081xYbJiW0KvnuJ3GNVv4vFJVQf0oEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xe7q/YjPTDTbOM7E4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVrcvXeCxeLl 5R5mi7ZZ/Bb/9+xgt/h3bSOLxex3+9kttryZyGpxfG24Rcv+KSwOch7vb7Sye7x5+ZLF43DH F3aPvd8WsHjsnHWX3aNn5xlGj02rOtk87lzbw+Yx72Sgx/3u40wem5fUe7SsPcbk0f/XwOP9 vqtsHn1bVjF6XGq+zh4gFKVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9n k5Kak1mWWqRvl6CX0bFpJVvBf66K/T+eMDUw/uHoYuTkkBAwkZg+6zN7FyMXh5DAUkaJvV+v sUIkZCSudb9kgbCFJf5c62KDKHrFKNH5fgNYgk3ASOLB8vlgDSICi1kk9u6rBCliFnjLKHF9 5kawImGBYInZZ36xg9gsAqoSfXPvM4PYvAIOEh83TGOC2CAvsf/gWbA4J1B8TdcNRhBbSMBe 4t+pD2wQ9YISJ2c+AZvJDFTfvHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy021CtOzC0uzUvX S87P3cQITDDbjv3cvINx3quPeocYmTgYDzFKcDArifAeEspMF+JNSaysSi3Kjy8qzUktPsRo CnT3RGYp0eR8YIrLK4k3NDMwNTQxszQwtTQzVhLndbt8Pk1IID2xJDU7NbUgtQimj4mDU6qB qe2GXUtiUrSczt1ZnGcv8i5ce2Tzi2cJTTEWdzsP8pV+3TZx5SeuFO225svvDpzmEZnz3emL XVfi6SWTA6aoyHTHTlm/Y2/1/69XZMUNYi97H5n8oFZlHfeqH9quv9wtTwcVy3huV+eO2D/j pcGLXJnqtzeOHeIo4jK48fH3z/x5p1YeV9T6xGl6S8lwWqD1ZtVvu2ZsU+zLXCi/vMWSM8Re v1RPR7H9AXeGzZqkMD5d2cZH+14Kykxa6lqx68WPbcz9ybYtQm98uOpzhf4Gsvqq7ly8oFdC ekNpfTWHJZtArcWV7nnPTyl9/Vpu9HNOm3blDOXcP+LJ7bU+H4/IzFm0x72St/vRt+0/vB7c VGIpzkg01GIuKk4EAO7N0Ve5AwAA X-CMS-MailID: 20241223125626eucas1p137d01dbee3cb24c38c0d4aa46404c7d5 X-Msg-Generator: CA X-RootMTR: 20241223125626eucas1p137d01dbee3cb24c38c0d4aa46404c7d5 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125626eucas1p137d01dbee3cb24c38c0d4aa46404c7d5 References: <20241223125553.3527812-1-m.wilczynski@samsung.com> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index c6fe2ea3197d..7e4b97f9e1b5 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -506,6 +506,19 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + gpu: gpu@ffef400000 { + compatible = "thead,th1520-gpu", "img,img-bxm"; + reg = <0xff 0xef400000 0x0 0x100000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_GPU_CORE>, + <&clk CLK_GPU_CFG_ACLK>; + clock-names = "core", "sys"; + power-domains = <&pd TH1520_AON_GPU_PD>; + resets = <&rst TH1520_RESET_ID_GPU>; + reset-names = "gpu"; + }; + rst: reset-controller@ffef528000 { compatible = "thead,th1520-reset"; reg = <0xff 0xef528000 0x0 0x4f>;