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([145.224.66.70]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c847714sm13938184f8f.54.2024.12.24.02.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:44:37 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, irogers@google.com, yeoreum.yun@arm.com, will@kernel.org, mark.rutland@arm.com Cc: robh@kernel.org, James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH v2 1/5] perf: arm_spe: Add format option for discard mode Date: Tue, 24 Dec 2024 10:44:08 +0000 Message-Id: <20241224104414.179365-2-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241224104414.179365-1-james.clark@linaro.org> References: <20241224104414.179365-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 FEAT_SPEv1p2 (optional from Armv8.6) adds a discard mode that allows all SPE data to be discarded rather than written to memory. Add a format bit for this mode. If the mode isn't supported, the format bit isn't published and attempts to use it will result in -EOPNOTSUPP. Allocating an aux buffer is still allowed even though it won't be written to so that old tools continue to work, but updated tools can choose to skip this step. Reviewed-by: Yeoreum Yun Signed-off-by: James Clark --- drivers/perf/arm_spe_pmu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index fd5b78732603..9aaf3f98e6f5 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -193,6 +193,9 @@ static const struct attribute_group arm_spe_pmu_cap_group = { #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */ #define ATTR_CFG_FLD_store_filter_LO 34 #define ATTR_CFG_FLD_store_filter_HI 34 +#define ATTR_CFG_FLD_discard_CFG config /* PMBLIMITR_EL1.FM = DISCARD */ +#define ATTR_CFG_FLD_discard_LO 35 +#define ATTR_CFG_FLD_discard_HI 35 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */ #define ATTR_CFG_FLD_event_filter_LO 0 @@ -216,6 +219,7 @@ GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); +GEN_PMU_FORMAT_ATTR(discard); static struct attribute *arm_spe_pmu_formats_attr[] = { &format_attr_ts_enable.attr, @@ -228,9 +232,15 @@ static struct attribute *arm_spe_pmu_formats_attr[] = { &format_attr_event_filter.attr, &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, + &format_attr_discard.attr, NULL, }; +static bool discard_unsupported(struct arm_spe_pmu *spe_pmu) +{ + return spe_pmu->pmsver < ID_AA64DFR0_EL1_PMSVer_V1P2; +} + static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, struct attribute *attr, int unused) @@ -238,6 +248,9 @@ static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, struct device *dev = kobj_to_dev(kobj); struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); + if (attr == &format_attr_discard.attr && discard_unsupported(spe_pmu)) + return 0; + if (attr == &format_attr_inv_event_filter.attr && !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) return 0; @@ -502,6 +515,12 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, u64 base, limit; struct arm_spe_pmu_buf *buf; + if (ATTR_CFG_GET_FLD(&event->attr, discard)) { + limit = FIELD_PREP(PMBLIMITR_EL1_FM, PMBLIMITR_EL1_FM_DISCARD); + limit |= PMBLIMITR_EL1_E; + goto out_write_limit; + } + /* Start a new aux session */ buf = perf_aux_output_begin(handle, event); if (!buf) { @@ -743,6 +762,10 @@ static int arm_spe_pmu_event_init(struct perf_event *event) !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; + if (ATTR_CFG_GET_FLD(&event->attr, discard) && + discard_unsupported(spe_pmu)) + return -EOPNOTSUPP; + set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT)) From patchwork Tue Dec 24 10:44:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13919926 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D7771C3C1C for ; Tue, 24 Dec 2024 10:44:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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([145.224.66.70]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c847714sm13938184f8f.54.2024.12.24.02.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:44:41 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, irogers@google.com, yeoreum.yun@arm.com, will@kernel.org, mark.rutland@arm.com Cc: robh@kernel.org, James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH v2 2/5] perf tool: arm-spe: Pull out functions for aux buffer and tracking setup Date: Tue, 24 Dec 2024 10:44:09 +0000 Message-Id: <20241224104414.179365-3-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241224104414.179365-1-james.clark@linaro.org> References: <20241224104414.179365-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 These won't be used in the next commit in discard mode, so put them in their own functions. No functional changes intended. Reviewed-by: Yeoreum Yun Signed-off-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 83 +++++++++++++++++----------- 1 file changed, 51 insertions(+), 32 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index 22b19dcc6beb..1b543855f206 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -274,33 +274,9 @@ static void arm_spe_setup_evsel(struct evsel *evsel, struct perf_cpu_map *cpus) evsel__set_sample_bit(evsel, PHYS_ADDR); } -static int arm_spe_recording_options(struct auxtrace_record *itr, - struct evlist *evlist, - struct record_opts *opts) +static int arm_spe_setup_aux_buffer(struct record_opts *opts) { - struct arm_spe_recording *sper = - container_of(itr, struct arm_spe_recording, itr); - struct evsel *evsel, *tmp; - struct perf_cpu_map *cpus = evlist->core.user_requested_cpus; bool privileged = perf_event_paranoid_check(-1); - struct evsel *tracking_evsel; - int err; - - sper->evlist = evlist; - - evlist__for_each_entry(evlist, evsel) { - if (evsel__is_aux_event(evsel)) { - if (!strstarts(evsel->pmu->name, ARM_SPE_PMU_NAME)) { - pr_err("Found unexpected auxtrace event: %s\n", - evsel->pmu->name); - return -EINVAL; - } - opts->full_auxtrace = true; - } - } - - if (!opts->full_auxtrace) - return 0; /* * we are in snapshot mode. @@ -330,6 +306,9 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, pr_err("Failed to calculate default snapshot size and/or AUX area tracing mmap pages\n"); return -EINVAL; } + + pr_debug2("%sx snapshot size: %zu\n", ARM_SPE_PMU_NAME, + opts->auxtrace_snapshot_size); } /* We are in full trace mode but '-m,xyz' wasn't specified */ @@ -355,14 +334,15 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, } } - if (opts->auxtrace_snapshot_mode) - pr_debug2("%sx snapshot size: %zu\n", ARM_SPE_PMU_NAME, - opts->auxtrace_snapshot_size); + return 0; +} - evlist__for_each_entry_safe(evlist, tmp, evsel) { - if (evsel__is_aux_event(evsel)) - arm_spe_setup_evsel(evsel, cpus); - } +static int arm_spe_setup_tracking_event(struct evlist *evlist, + struct record_opts *opts) +{ + int err; + struct evsel *tracking_evsel; + struct perf_cpu_map *cpus = evlist->core.user_requested_cpus; /* Add dummy event to keep tracking */ err = parse_event(evlist, "dummy:u"); @@ -388,6 +368,45 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, return 0; } +static int arm_spe_recording_options(struct auxtrace_record *itr, + struct evlist *evlist, + struct record_opts *opts) +{ + struct arm_spe_recording *sper = + container_of(itr, struct arm_spe_recording, itr); + struct evsel *evsel, *tmp; + struct perf_cpu_map *cpus = evlist->core.user_requested_cpus; + + int err; + + sper->evlist = evlist; + + evlist__for_each_entry(evlist, evsel) { + if (evsel__is_aux_event(evsel)) { + if (!strstarts(evsel->pmu->name, ARM_SPE_PMU_NAME)) { + pr_err("Found unexpected auxtrace event: %s\n", + evsel->pmu->name); + return -EINVAL; + } + opts->full_auxtrace = true; + } + } + + if (!opts->full_auxtrace) + return 0; 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([145.224.66.70]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c847714sm13938184f8f.54.2024.12.24.02.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:44:44 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, irogers@google.com, yeoreum.yun@arm.com, will@kernel.org, mark.rutland@arm.com Cc: robh@kernel.org, James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH v2 3/5] perf tool: arm-spe: Don't allocate buffer or tracking event in discard mode Date: Tue, 24 Dec 2024 10:44:10 +0000 Message-Id: <20241224104414.179365-4-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241224104414.179365-1-james.clark@linaro.org> References: <20241224104414.179365-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The buffer will never be written to so don't bother allocating it. The tracking event is also not required. Reviewed-by: Yeoreum Yun Signed-off-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index 1b543855f206..4301181b8e45 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -376,7 +376,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, container_of(itr, struct arm_spe_recording, itr); struct evsel *evsel, *tmp; struct perf_cpu_map *cpus = evlist->core.user_requested_cpus; - + bool discard = false; int err; sper->evlist = evlist; @@ -396,10 +396,17 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, return 0; evlist__for_each_entry_safe(evlist, tmp, evsel) { - if (evsel__is_aux_event(evsel)) + if (evsel__is_aux_event(evsel)) { arm_spe_setup_evsel(evsel, cpus); + if (evsel->core.attr.config & + perf_pmu__format_bits(evsel->pmu, "discard")) + discard = true; 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([145.224.66.70]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c847714sm13938184f8f.54.2024.12.24.02.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:44:48 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, irogers@google.com, yeoreum.yun@arm.com, will@kernel.org, mark.rutland@arm.com Cc: robh@kernel.org, James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH v2 4/5] perf test: arm_spe: Add test for discard mode Date: Tue, 24 Dec 2024 10:44:11 +0000 Message-Id: <20241224104414.179365-5-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241224104414.179365-1-james.clark@linaro.org> References: <20241224104414.179365-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a test that checks that there were no AUX or AUXTRACE events recorded when discard mode is used. Reviewed-by: Yeoreum Yun Signed-off-by: James Clark --- tools/perf/tests/shell/test_arm_spe.sh | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/tests/shell/test_arm_spe.sh b/tools/perf/tests/shell/test_arm_spe.sh index 3258368634f7..a69aab70dd8a 100755 --- a/tools/perf/tests/shell/test_arm_spe.sh +++ b/tools/perf/tests/shell/test_arm_spe.sh @@ -107,7 +107,37 @@ arm_spe_system_wide_test() { arm_spe_report "SPE system-wide testing" $err } +arm_spe_discard_test() { + echo "SPE discard mode" + + for f in /sys/bus/event_source/devices/arm_spe_*; do + if [ -e "$f/format/discard" ]; then + cpu=$(cut -c -1 "$f/cpumask") + break + fi + done + + if [ -z $cpu ]; then + arm_spe_report "SPE discard mode not present" 2 + return + fi + + # Test can use wildcard SPE instance and Perf will only open the event + # on instances that have that format flag. But make sure the target + # runs on an instance with discard mode otherwise we're not testing + # anything. + perf record -o ${perfdata} -e arm_spe/discard/ -N -B --no-bpf-event \ + -- taskset --cpu-list $cpu true + + if perf report -i ${perfdata} --stats | grep 'AUX events\|AUXTRACE events'; then + arm_spe_report "SPE discard mode found unexpected data" 1 + else + arm_spe_report "SPE discard mode" 0 + fi +} + arm_spe_snapshot_test arm_spe_system_wide_test +arm_spe_discard_test exit $glb_err From patchwork Tue Dec 24 10:44:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13919929 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43F1B1D90D9 for ; Tue, 24 Dec 2024 10:44:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735037095; cv=none; b=t1rhth4deVfPef5l2I8XPOcK8ZMWFCOYLwhA+fd/pfPdGZgE/k7OfDa8NL0Pmh6dyqKQpVOs+3KJLOL3bGlCn6dy1AgNMtY6AwgsrEwpvPcz+8dCVNSYBocKtg5lu0SBg5P2fbwT+POZzGfFkWgEgDFBGdIEVIRbRgtBHG3lUn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735037095; c=relaxed/simple; bh=RerMUU2iJNRvAH+P/WRIzJRF2OXWh6S/x0SNAoX8N2I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tm2j8vzwU+2KgSTyZGMLp+2NE+CQTKh3lb2gHvzrCe5KK0xQ2XNyDY5b99Pq0ux0E4LaHDoz4tlihpmgbZ51ZocI01WqlRcY/CS9oqsWoxxrjYFCYPEoI1LuPoiQW/Fb5ANEshCfMSwSd5BAtbwClpdwIeCNpokCbU8p1ALY9eE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JoVoOiWU; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JoVoOiWU" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-385de59c1a0so2998073f8f.2 for ; Tue, 24 Dec 2024 02:44:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735037093; x=1735641893; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BwyNoR0SnuVGySQmrh3vEyVb1ET66P1aG6x3YnivKGw=; b=JoVoOiWU+LTn+LzaphtbuB4Uy4oRwIAX12TYoxTIyc99OcRv0k1xpgCYbeGRUQukqO 9BC0T/W69NXtBNB8oxSdTsUYaMqVBU/eIwjInM/SutQGRFGmEYuO0/Pn00AisA5/bna9 b8hz7lX+wYeObujE3ZP2+HMLlLXlaNzqVk5MKhsUTSVXm8B+ilfBmX3M6ZO9N8nrxAdz MW6B+BwJCdndxPaFQ3Q1hYTc6nrxeKtIssYKApNQGxpN6mB9rQfojH1X7grvoEeh7EkF tpKo4esC7tqLroFw4E13Dz26NWZQ7MmKiwa7hJ94zkun6Iq7mzP3Hxlw0VKKUrSVIBRx h6HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735037093; x=1735641893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BwyNoR0SnuVGySQmrh3vEyVb1ET66P1aG6x3YnivKGw=; b=FCcbp4SAUmXZ17JPKfPxMtblhi/BVISByvIBesP4B9dkI760Il5MKv/yV0JI25s+k6 q4wDd50Bq6IbwTQlLttaiGRRZ+gAFxyDbAcP8R+VxvdX9gB2Yfpon51c0/TuVXgCqXN/ C47kucNCQN6wBSXnwIIETKk7m50HFimc+AfbmWx6XFrH0nrbsybtf/r9sQZ92TFoRLqU 3LUJwwN2iT4HDO2v/qYPdUGmXiyjQdW3mKgI/jOoTWXKpu9nG9Is4egoKmNrelJXjntz XYwVyCVN78ePjShRGiHOigyCGSapCZ1AixfqxBXKHQFox5o6l2UJduesvVu/COPxF7PQ ua1g== X-Forwarded-Encrypted: i=1; AJvYcCUcmXbGl2nfpgNX8o7ExypMR7p1DqZO8RPXV4IdcW6N3f5pSfPCD8c6oEdD+A5bs5GbVIM=@vger.kernel.org X-Gm-Message-State: AOJu0YzwU6vyeAOKsURt4fnxma2Nfi5T16Ipc8kz2ORHTsLQhmVF9uMc bYtu+Rj5l4cWycBtLuOmo/1zVu0EIAgPVfHO7m9FDnD4VSQ32+NSjuoPzimMmfY= X-Gm-Gg: ASbGncu2gwhOxU4vlV8JOV6t5C5Vy4HGaycdlFmPkNE3RJGSgcmjotwkzwd3bzXbPDa sTZ4OaTK2FfQB+ysfMxu1vAch0zV7B67nAOncXkrBpbqJgDAjBJc0wZSZdrEdo2C2enj5hWZ+B7 eN1Ao60Kdflvv/KbHRUW8IwT/fMROwi1aZiaeGLoqNUQYX+hBmZIH3KnWmbKaIbxw623XYQvNHp 1FDw83TNyEZPeVnQ0uNbfW2H83MdzREoKjmzXeAq0i4JnnpQmu+Afg= X-Google-Smtp-Source: AGHT+IEHX62hM4cRXueG3YQu6eg84405e7WqgYcT9lFPGrHLB17v7HhSKT3GSKfbXrWS+gmH7kk2Dw== X-Received: by 2002:a05:6000:794:b0:385:e013:b842 with SMTP id ffacd0b85a97d-38a221ea331mr12569563f8f.14.1735037092689; Tue, 24 Dec 2024 02:44:52 -0800 (PST) Received: from pop-os.. ([145.224.66.70]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c847714sm13938184f8f.54.2024.12.24.02.44.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:44:52 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, irogers@google.com, yeoreum.yun@arm.com, will@kernel.org, mark.rutland@arm.com Cc: robh@kernel.org, James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , "Liang, Kan" , John Garry , Mike Leach , Leo Yan , Graham Woodward , linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: [PATCH v2 5/5] perf docs: arm_spe: Document new discard mode Date: Tue, 24 Dec 2024 10:44:12 +0000 Message-Id: <20241224104414.179365-6-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241224104414.179365-1-james.clark@linaro.org> References: <20241224104414.179365-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the flag along with PMU events to hint what it's used for and give an example with other useful options to get minimal output. Reviewed-by: Yeoreum Yun Signed-off-by: James Clark --- tools/perf/Documentation/perf-arm-spe.txt | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documentation/perf-arm-spe.txt index de2b0b479249..37afade4f1b2 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -150,6 +150,7 @@ arm_spe/load_filter=1,min_latency=10/' pct_enable=1 - collect physical timestamp instead of virtual timestamp (PMSCR.PCT) - requires privilege store_filter=1 - collect stores only (PMSFCR.ST) ts_enable=1 - enable timestamping with value of generic timer (PMSCR.TS) + discard=1 - enable SPE PMU events but don't collect sample data - see 'Discard mode' (PMBLIMITR.FM = DISCARD) +++*+++ Latency is the total latency from the point at which sampling started on that instruction, rather than only the execution latency. @@ -220,6 +221,31 @@ Common errors Increase sampling interval (see above) +PMU events +~~~~~~~~~~ + +SPE has events that can be counted on core PMUs. These are prefixed with +SAMPLE_, for example SAMPLE_POP, SAMPLE_FEED, SAMPLE_COLLISION and +SAMPLE_FEED_BR. + +These events will only count when an SPE event is running on the same core that +the PMU event is opened on, otherwise they read as 0. There are various ways to +ensure that the PMU event and SPE event are scheduled together depending on the +way the event is opened. For example opening both events as per-process events +on the same process, although it's not guaranteed that the PMU event is enabled +first when context switching. For that reason it may be better to open the PMU +event as a systemwide event and then open SPE on the process of interest. + +Discard mode +~~~~~~~~~~~~ + +SPE related (SAMPLE_* etc) core PMU events can be used without the overhead of +collecting sample data if discard mode is supported (optional from Armv8.6). +First run a system wide SPE session (or on the core of interest) using options +to minimize output. Then run perf stat: + + perf record -e arm_spe/discard/ -a -N -B --no-bpf-event -o - > /dev/null & + perf stat -e SAMPLE_FEED_LD SEE ALSO --------