From patchwork Wed Dec 25 18:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920840 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E77F1BBBC9; Wed, 25 Dec 2024 18:13:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150429; cv=none; b=e07b1iUmvN8fZ2+ohL3xRzovPyHsxBxbNPt2MuTiwsvaKR5F+1Lg8hiKmaeMMfkv/Mp9KBd8Fi4L6Y1DLORbmnKtgUQynLRT2RhJy+WCXB7WVodrCbaRJPi3EJfrHj+Qi2ixeA5j4cFC/HNGaTxtZtiinjHS7U80QB7OULh3bEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150429; c=relaxed/simple; bh=wo26MPasJSxpEXKI6bj/8PzZDxtrQwJnBbZ7PVj6Dxk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RXQNWbb+xU6dc5kPZsquQpSbL55oO/GzIbVhg+osX1KO6ZRAoicken8qMp1jpyyTrJvkTjoFIWt7drzHVuATRYx0knUPVbe8shQtjvUC3cApaYGeqQxfeP897iPZMJoS0k7SeL7GWyD71fCmH4/lcha2uv6qnbJtO0lEfaREJog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P8x0+iBJ; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P8x0+iBJ" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5d44550adb7so1183740a12.2; Wed, 25 Dec 2024 10:13:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150426; x=1735755226; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eVmzYFglhbWVJo29AKC/1HcZCKPPQeWX0Z8Su8VQcMk=; b=P8x0+iBJILNHMDrKCJUKcivuRrCZ+vRjA44Za4DvhPiUC8j7UGAxeBNvQE7C/EjPNn pg/dddas2/AxqSzgMEFYsuLiJ+lKGIOzThkX/M04DvW1tBkX2KfihI2VU6MlmVo+cL/O EvMvpn4U8SF7HVXuqKUlSIRuTcVHOZEpHweEdMbk3bUYOWEmTO/RyqMWkZlsnoxGdVS9 BHPM1O4hnBPftKhWohG1yoGQxAF/yGcAIeH7Hr65W7tVtfLAlFXZB91TMKSRquT/HELz HKrMNQlGMUUfdqZscqDnhWKsEmlgCCIK6mmhrdNglOTA2S+MsaA6d2jGy0xmeacJjVBy FPAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150426; x=1735755226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eVmzYFglhbWVJo29AKC/1HcZCKPPQeWX0Z8Su8VQcMk=; b=a/ciDUFtmjEDxvvolVJPvQ0wNZiYPyhLMax4SuWPjTp8dN8VHQZh2iVxJg1t9SF2FV ZtzbCPqsyfLZeuI8OhvNk9qS9Qpg4vevgif1afb0Lh0L+U0nhEzZZOoUTpYUcXHNK4Yc 5k3L/A19K9vfMxZQK+U1ehYqF7qr9ADu8c9g5KT7u5oI3D4QhecB4M71ZHg9O3vfRf5Z uso7AJ01rQChfKL+azBNF9KBNUZktqDUggMA0oR/NfHbEJ9d+HQJqyU/LiNNOALAV/PP 68eYJlZB2de/4Uaq6F8smXcUN+q76oLeGuwG0ZSsRCVHU3Qu6ETy03tz6YRfABhsiktT ufHA== X-Forwarded-Encrypted: i=1; AJvYcCWgryrAfUkVEJoUpO9/r9udDZhWroI7HB7Ff+3E8SrKksAZHfXA4o7O8bmdld0syCLbthSaqlqCPlqMYJa+@vger.kernel.org, AJvYcCXXKop9CJWezVadmUWIclyLfq02lPtuVpsglvv1dmWY2+qNE6khGOu2xrEtoedhtc55sbOUHgNPCLc=@vger.kernel.org X-Gm-Message-State: AOJu0YwgPhnwbhyWfMaS246TMc8i4q0/fzlFW5rQicp9wUMe90KPeglh hSoYzYjqhq0VmbNmyFPLVVnrrk4jN8ZWKD062iY2nG8/xC9owO8QH2XVmQ== X-Gm-Gg: ASbGncv1xBthqixtw/CdDZfDcW2Zlxbcbz2EnSMbRT4ciPAXOiJ2bjKSQdb0hfiYlSk F575k17sKQMYsm+mqRjxze2HpDmB5Q+/QL2vbaojgx0CRG5jtBwg8I3sownZc90/PNQJumN8aEX VxeuDTNzRg0Lnqzk+gnvNl8tbFb4gcWS3hWawWd23w5+g2pfBxfXwD8tqikzrps8xujsgP7zxK0 MZ2bz9iarl/rP/Z3CmVvCagEZwoWuLeT8h++1UsmZHG7jL/Z8lhW6TjbIAoAPyiu9Le+SpYe9Z1 AUw1gk8O537Edn9DtbYkCLyMNpoPNsfDsOY= X-Google-Smtp-Source: AGHT+IESkMO0HKzi6Lf3GyzkrmBPK7xs0U8xmn0IEeqxlLAk7HfjldVAZ2+pnBW9qIBBVn7sPEfsAw== X-Received: by 2002:a05:6402:350d:b0:5d4:35c7:cd7b with SMTP id 4fb4d7f45d1cf-5d81dd8ffb2mr7601691a12.4.1735150426501; Wed, 25 Dec 2024 10:13:46 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:45 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 1/7] iio: accel: adxl345: add function to switch measuring mode Date: Wed, 25 Dec 2024 18:13:32 +0000 Message-Id: <20241225181338.69672-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace the powerup / powerdown functions by a generic function to put the sensor in STANDBY, or MEASURE mode. When configuring the FIFO for several features of the accelerometer, it is recommended to put measuring in STANDBY mode. Signed-off-by: Lothar Rubusch --- Please squash with a3fb9f5202c3de0ca84848a475f59a0e0584d9fc Just introduces a cosmetic simplification to the already applied commit, under the same title. drivers/iio/accel/adxl345_core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index b48bc838c..27d70a1f0 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -153,9 +153,8 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, */ static int adxl345_set_measure_en(struct adxl345_state *st, bool en) { - unsigned int val = 0; + unsigned int val = en ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; - val = (en) ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; return regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); } From patchwork Wed Dec 25 18:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920841 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 220551C3C03; Wed, 25 Dec 2024 18:13:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150432; cv=none; b=kaSSchBlpOJnv54vI8qgCeu3DlM6YODCchwy0mQR0CKpRyoNlk1y70Unqr0fY3g1kBocPVj/7sZpuAK51lU3YI5dA2evvyfuZEAXPtX49fDTOxAGpXsd513FViUrEr6Hm17a4Zcy31ZFk2+afQqBaeW4tSnRo12j8Fa5FdSC4NM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150432; c=relaxed/simple; bh=65dl+3BrRongku0AWNhcG9naAriQMM5Jtmkrnh/lkBo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Uugwcod+OSyTPk/j55vdMlvYn27YZv9vmB1YFGK89Gds6RkBe6rHTPWiFH4Gp9CvwvV4BJHFRFRdjBe5EpLP162W43/A9qZZEjT/OH0SaDHRUdnANA6p48gPe4yQCI4jgYbh+SsUg2ez28Q9ql91ejf6oN4jbK66doYKt1hv9gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WHEfHCyU; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WHEfHCyU" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-aa67bc91f87so96447566b.1; Wed, 25 Dec 2024 10:13:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150429; x=1735755229; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cO2/4aH5cQSk3uy/JmgG5dJ+8jnFA9jLBVp9LA1IxKo=; b=WHEfHCyUKVhkjApdnhL3qEtWq7/9JJ9dxipiT1MaVEV4TJpvZbVxc2oEkds6WBqiBi 9io1+Wab2Ppm6FXwlFms87P1ooEVLikXoQhNzazgLVXYOAmSLJ/Q2ozzyuLzAg9UPik/ JkSuigbEUQQd7ftUqZzDVmgxwQepDf9RZmVCkZoIkibLYigcGFMjgrFgOzoicl3NEmDO bWRqzd9IUU1XjscAb7z5I/kufVBrYbIuYDb8dfGWM/hmKftCyYBn0f6+ubt9UrJHw7gI CJFfpjSdj3HbJmvtTTG5zRTKALN2ZwLuoCXagGUQV13j3oIda9UdSKRRR+u9HE6Coveh rDfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150429; x=1735755229; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cO2/4aH5cQSk3uy/JmgG5dJ+8jnFA9jLBVp9LA1IxKo=; b=NP3WuqLKlcvrgbpfiEukAVxeUc2uiC4pB5eioYl8WjtJAkeBnX32tUbd0uWpdFQpqB SXbZoByTooOt4ZofVk326OYLpYVAUSdv2VrxVZ/t4D350xJnsUCWVWnNxaH/xIo9ncR8 MF1cVKnZbqdbYpM7Vd0Iok0mOKWMiNB8nuTg6jvnCP45d0IRlxIFlqUjgoBne2Vs/EQq yXENvg6BJiobO9iBhTWHOifyMCmMtm7H8xxO+x9QEILExPlCcBuiHi+2weOzU0ZqX6z0 0Khyrf4fVQxDeTypbQYREipRs27wcMjZNTL39lzqkNShZYo8mabQEaajcML2AhIkzhAv JBKg== X-Forwarded-Encrypted: i=1; AJvYcCWNCQQ/RwYMfsRB/FhGD1b9nLbklAooqivTpfTqNC7CHHvIA/x+Gu6Waaipt/cNyqbrpVQ+GhzAvwNgHfjQ@vger.kernel.org, AJvYcCXTkDFzaqDNo9pP5OvUzRJzqehHI1v3V/vp06B7WW5c/7j9RzyTG6rLRLDnOXkAjEjDAI4aMnvdK58=@vger.kernel.org X-Gm-Message-State: AOJu0Yx3oq1h5eoNhcbkhizzIl/H1JXP3f5zBOugZRledN9bfPfQH1mf dgjVKLobkdR4Dab0DTUzZBsr6339dDoQ6A0C529gRv/Ad60+gDzTxhBPaQ== X-Gm-Gg: ASbGncs9DVe9jBLT3bUYwr3yqQl0fs8Y0A1NQjP+KM94PrX0SwbC+rsv1uBIzK2BDG9 fqtkjOd3YEhNmQ/3icToXMFDJXsYeg9rBc3+qnbjaAdbjuLxYP8exRIUCKYDBZ1R/fxJzVM3RJJ HKa20b/GfI9NVpA+zYFJiQibpj7diS8SOTxt3SfFzsPsoKvQxlNvpEDX47MqtM1pz10+Ok3QQRh Im+M+PsXS3h8VXjHyjxyeezTWhfnfth0xEzzBXxeo4G1zfCEEEE8HivIJRaqoCD6C+1AO6kERDI tAxH1zZUrGjbApk5+H91aq8yVfcvvN7q9A0= X-Google-Smtp-Source: AGHT+IGeJPhjgLl7snfyXVdVE6ESFoZQZetb49VI2ndejO5KMzLMJRsusERhe2r8lf9/NkyGW9r0cQ== X-Received: by 2002:a05:6402:3550:b0:5d4:35c7:cd70 with SMTP id 4fb4d7f45d1cf-5d81dd9cbebmr7516660a12.4.1735150428998; Wed, 25 Dec 2024 10:13:48 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:47 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com, Krzysztof Kozlowski Subject: [PATCH v8 2/7] dt-bindings: iio: accel: adxl345: make interrupts not a required property Date: Wed, 25 Dec 2024 18:13:33 +0000 Message-Id: <20241225181338.69672-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove interrupts from the list of required properties. The ADXL345 does not need interrupts for basic accelerometer functionality. Acked-by: Krzysztof Kozlowski Signed-off-by: Lothar Rubusch --- Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index 280ed479e..bc46ed00f 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -40,7 +40,6 @@ properties: required: - compatible - reg - - interrupts allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# From patchwork Wed Dec 25 18:13:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920842 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CE2D1C460B; Wed, 25 Dec 2024 18:13:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150435; cv=none; b=bgkHmabptVg9MUFz5Fge+KojXIeeujYE1Pgk6/yp8RNuIq292wZlLi8VDHHgWogqslyuZcHg+/z7fQ/3geUzX/XGaQKy6/92tDMj8psTtlBj8ZGTdIkZ0YspvIhUCRdPrp3zrUxGHZz/NEQYVgdgPmjcD3o+alBiqiks6POp8dA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150435; c=relaxed/simple; bh=ggdrW/BTcLogCPS2mh2i3gna8+7b4XdfkZbjCw7lz6Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tGMk4NDxPGO6xVe4PveQzerg6+dsqk6R78JxjW31y+j7IBFIEe6aMiDn4USjVXOi+833BiHCnBM/vfqx47+bYbre/MPWyV96dUVBi3tRDpKj6j2FWvKvVn7XVKaKwUaQpFuUKPOc1dxtiO8L20a188BP4YBUaOZMC+aZTvQwxIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PyqG/I0Q; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PyqG/I0Q" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-aa6a47a3da3so118299966b.1; Wed, 25 Dec 2024 10:13:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150432; x=1735755232; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wYDrZiVle4k+26gWV15uDrwllCdtK3uFZaGukHuklik=; b=PyqG/I0Qr+TZGA05pQOIEiaTroX8mLLegcenfeCfrqO7exQEbSwnAt9k0+UfZ1R2CH RWO+oR2X6UeBRMJEckO+8y6Z48KVbilcER2goFb/VUQ2Qh9a1xXaBonocrtb5foVGUuy 12agkrDuAqTyqMx9L+60WH0YW7sMxgSOy/IGKjRTVjRwq6tc8/o867MkeZ6/ch40lJAs SV8u7CSBLFv2FZpUC4Wv19vdh1qWWeyAKofDr+bJOMFOqGP4zkfky7lIcuVmTWjB1U48 4FxjUSpSae4u4k58yFlbjiyev70WK6nRPdYDVITItniBFChF0R/F4P12qid80qQxQGQN osqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150432; x=1735755232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wYDrZiVle4k+26gWV15uDrwllCdtK3uFZaGukHuklik=; b=CLgn9rfZn+/KWLTbkpTXN48MXweUkLJZj/SpFUpInElv9ZI97dForbA51mfBUQ3pj5 3GC/kp1UCq/4SZqD148mVVG1jPwkeZHk+TDbpT+8+G00t2jTp5LXUQ4UiE81GbDmlAxO sssCBlDcA0XS5iV5yxF5cuwVxns3wH6uREnPiisFi9XnPgDzNYarnmfl0mvVwFf281JU p7bKjGoGHFkrmpUcL6KJJtrioLmo3BWBBeEIJVlrcCP3ec+yqYNYc/442vcMVck2obVF dYLVJW2X6TX7HfOc6btFQ7fRzBIrGKdlv3jR9hHjCaPMCUKKpUxGLDKPJFiUMUb0FX/C wFAA== X-Forwarded-Encrypted: i=1; AJvYcCWj5HX03QQq1oHKH5rmdyHb2Z2ZuOvv/mdRBWwioYjAmzvI6exj+cL/8RX6xHlH8b7E80PnIZJb8XwP+DiF@vger.kernel.org, AJvYcCWvnt9PNCWBxJeEON/5qQfdWGnlZ+gzIEc+gkEPQhy280SpmLvSsPH7iyG7O/99LBXjkk9i1wMabSI=@vger.kernel.org X-Gm-Message-State: AOJu0YxVduwNhGmU4OIKSEqgb76ecGG0P+43Q1yxBEgmPQNsDFc13KUx Ib/jjDcdXWcBHHWBYB1YlRFCVtp4NtGPey7LPfSPUk7fGTH0iwkI X-Gm-Gg: ASbGncthJZTWTlT6c5ozbUkFdYzy460xqzHdX9XFbb8/WN+ZPKpGC5mxKUkfwu4AZYE 2h1IP5fnBLpc+/2NPWyDN4sZyU+bDHGvghGzracZW4SFyCqNwJlAdp0Yow0h+crgdiprPT6g8Fy homUDjVw69dtwUWokdqr94HWdOOJDYvS+6qBtWocULGf0XH6Y8fGOC+BoDrDpY2NgOyYRhcMoMQ vmx4HjF6tfKmt9b5cPlYk/4gn0/fQlDJf2A81IABQ6lAKH9Rvu4BuOIYLpNdR/aNVdDisG8NwwS UP7cRWYJwwy3NM4B9TtOgpFSOCo2tCZO6xc= X-Google-Smtp-Source: AGHT+IHRyY6uaLLGd97ERIYdcLr+jR5gBisEWLT7NW4xPVidPjix8m9NnTlWJib8hWgSUBpzMDy5ug== X-Received: by 2002:a05:6402:13c7:b0:5d3:ba42:e9f8 with SMTP id 4fb4d7f45d1cf-5d81ddf80bcmr5435836a12.7.1735150431509; Wed, 25 Dec 2024 10:13:51 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:50 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 3/7] dt-bindings: iio: accel: adxl345: add interrupt-names Date: Wed, 25 Dec 2024 18:13:34 +0000 Message-Id: <20241225181338.69672-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add interrupt-names INT1 and INT2 for the two interrupt lines of the sensor. When one of the two interrupt lines is connected, the interrupt as its interrupt-name, need to be declared in the devicetree. The driver then configures the sensor to indicate its events on either INT1 or INT2. If no interrupt is configured, then no interrupt-name should be configured, and vice versa. In this case the sensor runs in FIFO BYPASS mode. This allows sensor measurements, but none of the sensor events. Signed-off-by: Lothar Rubusch Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/iio/accel/adi,adxl345.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index bc46ed00f..84d949392 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -37,6 +37,14 @@ properties: interrupts: maxItems: 1 + interrupt-names: + items: + - enum: [INT1, INT2] + +dependencies: + interrupts: [ interrupt-names ] + interrupt-names: [ interrupts ] + required: - compatible - reg @@ -60,6 +68,7 @@ examples: reg = <0x2a>; interrupt-parent = <&gpio0>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; }; }; - | @@ -78,5 +87,6 @@ examples: spi-cpha; interrupt-parent = <&gpio0>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT2"; }; }; From patchwork Wed Dec 25 18:13:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920843 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345E51C5494; Wed, 25 Dec 2024 18:13:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150436; cv=none; b=tCI8wzONOR9MMLSa+b/W1mi/aB1GPQTZ9FpnssYDZByv0ejpmOrGjHRZrLceawVsFhbqgV59Cu8/CW8aIrhk2RwaItOMWM7Z37599uKc9DXizt30ai9j/xoyO8Yi2OjDRHiD0Y+ITkXStw4iuDlMG/kVK3U7GzCN8wQupSShvx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150436; c=relaxed/simple; bh=muD/nJJlClqgww6SxT3wbYOjpIPUZERAZ7g3O/5sAks=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Imk0N6DrjAaUdRef6mj/IlFSU5yZHP4J/nLzuCv6ZV+wj9KchK8DSGhsMpd3PhTDPK+l6cHX1NkzcVwHSBv6L1l/c0EcZsQ1zv+FOl15PAg9eqf3YR/rNUy9vRG1o4/GrfWbjT5ESq8My1pHto4x2QIT4QDOJhphDTQoUmJC/+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Q0RU73NI; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Q0RU73NI" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-aa69599b4b0so113726766b.3; Wed, 25 Dec 2024 10:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150433; x=1735755233; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DntmeBaXtuyXrfh+kAwMzaleGIsyITJbBXEuuRaR7ig=; b=Q0RU73NIuCjluIXa4ZH+9AQScmEExGNHcqrD72xJLTTguu/YTVG+gx3jcu6sDYyCj1 zL324gFgE+jBZkN9EXpHTlNr6nbLGZaXe1uHDi4wyYyRFezu8Nuz7E+ccyEU3E1cUoyy mmFZfc8Yfsq2VT0SsbZTbBDhIHHwBEswZOk1UUNtqA86wgdZiOs0Y7ABpjclCuGW7WAg PI25EGiNlM+tngEit490v20dmYCcz4lFIDHbcQ1bfg5EXIJtFc+rcjvF6K1/J4lyGN2h gW7TnLZkfF3UxxMvdxoGJ68WdrL2mY2wNqGd4xUFIv3vGuF7q0NuZ3k2zie8J9yEgE8N GXXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150433; x=1735755233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DntmeBaXtuyXrfh+kAwMzaleGIsyITJbBXEuuRaR7ig=; b=NmzjYTmEs7Nz+FOh9pXgero0TSEjoMpy2Y9FxomKa+GiXDHj0TfO5GxNFSPqUzWYmN h6diCS03yWbKvpTThqXml5JstIFjIEo46JmBCUVOe+adcRi6X6jJc0nEsP019sAXO3tt 75aoF//G9uQ70PIRUMYjeQTZktG0z/ws1h4YIj/XuvMrPQfUxAvHg1kCFX9RKMPOHmS7 +Tym9sfyQ/FEtZ+y9AiL1w+l9TrTijbV6Ql9eWMzZFG4hJyqekwr9NX9aIb3OMhfWVEO hQvHSpQM0EbjcbJh8hk/RR0h60BYq0BxReBRrmcQGn+lkm3QZMJHlILVSBvw+3cpCsHE 1afQ== X-Forwarded-Encrypted: i=1; AJvYcCW0DAPDDmbNpVgcS40gdeJGXRd05T3W5uHSaSy1Fza5ekPssZf1uTqCz9TY9Sb7ZswUbNzINsw+Qfo=@vger.kernel.org, AJvYcCW718HDvMKHeZNaqNDkRCPfky4DD7DQfKu8pfcKGcs8utSTKlINEFDTcuWVFHi2yKspdgbPEu9z2RyQDGeg@vger.kernel.org X-Gm-Message-State: AOJu0YwawwQTVsGD83PvyeJAxf71zDGonigH26Ry7sxbcdpZ0hsykscQ xDZYAGUlI8fj0e3W/Z9/aN6cdomxc7zzL1XFCge596d9/0nqnEoZ X-Gm-Gg: ASbGncvHKymZxYhKjE2cLg45S7S+U3MZy9k4w7V5D1zhavJWYpEcuEu1Gx1tQ3zloi4 hnMd2YCojzqp4NklOSm0SzVZt1lb/2Wj++58FRPxNyvcmZeuKyWxbaebB8RVYRuNpaWNducr58G 6XyJAAJsb6FwDzuWb/aOlQVhGgi3qIsMLxxhKLIci7FEDChPPiWsFmgHaIpq0Ew+uTOz2b/9NTH dfzwqniC4RVfA1MejxnJBfkiDLe31E/sy5uPTlB5XuHQXepzNwv4txs3Up21oHT277eY6jop1jI Nl2kPCDE5qxnAjBd4Ko7J4VQTSLbWV9nWzM= X-Google-Smtp-Source: AGHT+IGq0pvTdzYhZbweSz1XNaJDd3dwLOIhmWuk63bQp2xmDngDQ79mUO7aqaVwPHDM1pQ57DzlaA== X-Received: by 2002:a05:6402:5246:b0:5d2:d72a:7803 with SMTP id 4fb4d7f45d1cf-5d81dd83c73mr7324385a12.4.1735150433312; Wed, 25 Dec 2024 10:13:53 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:52 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 4/7] iio: accel: adxl345: introduce interrupt handling Date: Wed, 25 Dec 2024 18:13:35 +0000 Message-Id: <20241225181338.69672-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the possibility to claim an interrupt. Init the state structure with an interrupt line obtained from the DT. The adxl345 can use two different interrupt lines for event handling. Only one is used. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 27d70a1f0..134e72540 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -7,6 +7,7 @@ * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf */ +#include #include #include #include @@ -17,9 +18,15 @@ #include "adxl345.h" +#define ADXL345_INT_NONE 0xff +#define ADXL345_INT1 0 +#define ADXL345_INT2 1 + struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; + int irq; + u8 intio; }; #define ADXL345_CHANNEL(index, axis) { \ @@ -262,6 +269,15 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, if (ret < 0) return ret; + st->intio = ADXL345_INT1; + st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); + if (st->irq < 0) { + st->intio = ADXL345_INT2; + st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); + if (st->irq < 0) + st->intio = ADXL345_INT_NONE; + } + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(adxl345_core_probe, IIO_ADXL345); From patchwork Wed Dec 25 18:13:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920844 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8CFE1CCEEC; Wed, 25 Dec 2024 18:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150439; cv=none; b=kUpc2Zze758DXQbfVJqmxkiy2tycFxm3L8IqsZVXcDyt1NDeAHmtjQexv3rdNvZn1X7lbV5iayVfCbnR2jQLtyeqpGrmjwNhXh/xrIrgaE9xLIj56cpI0b0Yw+ipi9sm8TOtsfdvrzjq4xwGkvgKeMzDspUxQgsCwXFNk7SQrnY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150439; c=relaxed/simple; bh=UBP+XEB54+kJlSKCmzmGUC96jClchIpxCRoyT7H3i5Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ESbNMkr1AQ03/lMyTYz8NhS2X2iQYw2KVcDVUSrx4bI3qSj4q0ug3MhApOXqAokuoPV9mIDBC8uAvFU/3HRPGxg3VdxbZCGtfxAQHdENI9YtmbpBabKP3702ZQxocD2a6CobjKtZkhUiMOLUpdk+sSmFSjNInRA+DKn5wcqf2uc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CFq0+yQ0; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CFq0+yQ0" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-5d3cd821c60so1074484a12.3; Wed, 25 Dec 2024 10:13:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150436; x=1735755236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=965nGCTrHAcWPGbVo5B4WZKkBPA60/xdYIjri6d4Rd8=; b=CFq0+yQ050gdCQGGEk/ZWkHkdF0iun+atHr6p7e9UZY/9ObK9xOqVgfwkossfNSY3/ WZgwCnFHQjUsrwhC3XJnON/KTdXsyrK5i9xwburmNlS0rg8BIC/YoxUvVh4dkOdd7rWH qNkqKzWWu+r8tc88FTcpWpqhmtaP0CcqCBr4ysBrJt+uxVtQ+UJUL+qZzvrnpXOufd+Q DH/YYxnYItyIlfbq4eaq5KiiOdSE+WJb054GRLYP4+Ye+Nc0ja5SPdme9SbCeUUM3tJ1 /mU/jsvdMMBBvkCS2vy04bVONU1sG1dKcvJdf4lzdgi2oT0/0AtR0U8irdUmOCFQbgOD geaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150436; x=1735755236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=965nGCTrHAcWPGbVo5B4WZKkBPA60/xdYIjri6d4Rd8=; b=Gw4cXXYUfSEOV9qJAOdwk2c6ugu2z3zTy7JxGWiovZcBNj8oPZ6RE78pdw/5pwW92v wjIsWb095435WRxPP3Te95pVsqQPvsiHes2xn3PxJmNIEQdEf6PE6MefePLPKAFshvys wn17Bc/wAf5t2onHGynATVPIk/rBwfYoK/jam4n+HSLKZMchaIuiMJx7Rmg82irY8G8D h6g8vvqGerNes6Zro8jI5eFBauWGYWD4IpYXapY3ErFXMmtdUUTxg1PvF/LMuZJS5Pyp WeSJiepqkXO0Vlmj760mKaze7RWoTw+HIzmqjeUs6aWv/V+OjBL3ax7VrWysh1X36pJJ BRVg== X-Forwarded-Encrypted: i=1; AJvYcCW1K4eZFYQQ7PUMMDV3bmym6xLOVuwhmuCpuNePMnoh3/lN2uUSEV1RUKSsrhief1eZxxCFBdAErXY=@vger.kernel.org, AJvYcCW6EZvFe6qcPuMyQpWMY1RO9nHO+KSwenncmcKXLX6E1XQjtM9Zhyg7zD78RcQHLqJhfHerqX7xnbpSezt0@vger.kernel.org X-Gm-Message-State: AOJu0YzEz3x6Gf03YRjQA7sFZ6Fla8VOqiE8ZcSA1d/sQ78RnzJFAKUB vtN2i89GA3ApdQ0kBSwOzSj+kc4H+A/MvvzHOcE7ADYoTugKQ9F9 X-Gm-Gg: ASbGncuMmXEyU2xCOBU/GeMQx04j/U8JYCqGFCOg+2OClMUarpttVmyw8t9ACJr3Y4O yWXld+8GZJP1HIikpYelIaqrur+5CC4w8LV54N/95ovObE9oPLq8fdYPv0XxrUzpluxGIgKJ9Ri kcVv6SCtSTa/IZV/SqeVC3CTg5oJ4buiIHiOt/FQrWS1Dp9aL/4OYfr27ZG4LLC8G5dXgmRrU7A IrwstcPzcKdJf6o7Fq7a+QWj7YHNlPlJVgBwXVk80Qj9fWkh4G67TSVO7A+955WPGxMNH/+0lh5 qmFS1CmYOXjZCbBiiTgfExWvA2v1SSFuO2E= X-Google-Smtp-Source: AGHT+IEIH/+X+6n3lqk92gTsUZz0db8l+wPwkfKP0Q0O4SeQYuWSVG0Fnuex963FPWdv8YjL5zvNQw== X-Received: by 2002:a05:6402:2695:b0:5d0:eb6b:1a31 with SMTP id 4fb4d7f45d1cf-5d81ddacfa5mr6260036a12.5.1735150435807; Wed, 25 Dec 2024 10:13:55 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:54 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 5/7] iio: accel: adxl345: initialize FIFO delay value for SPI Date: Wed, 25 Dec 2024 18:13:36 +0000 Message-Id: <20241225181338.69672-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the possibility to delay FIFO access when SPI is used. According to the datasheet this is needed for the adxl345. When initialization happens over SPI the need for delay is to be signalized, and the delay will be used. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 1 + drivers/iio/accel/adxl345_core.c | 11 +++++++++++ drivers/iio/accel/adxl345_i2c.c | 2 +- drivers/iio/accel/adxl345_spi.c | 7 +++++-- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index 3d5c8719d..6f39f16d3 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -62,6 +62,7 @@ struct adxl345_chip_info { }; int adxl345_core_probe(struct device *dev, struct regmap *regmap, + bool fifo_delay_default, int (*setup)(struct device*, struct regmap*)); #endif /* _ADXL345_H_ */ diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 134e72540..987a0fe03 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -25,6 +25,7 @@ struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; + bool fifo_delay; /* delay: delay is needed for SPI */ int irq; u8 intio; }; @@ -196,12 +197,21 @@ static const struct iio_info adxl345_info = { * adxl345_core_probe() - Probe and setup for the accelerometer. * @dev: Driver model representation of the device * @regmap: Regmap instance for the device + * @fifo_delay_default: Using FIFO with SPI needs delay * @setup: Setup routine to be executed right before the standard device * setup * + * For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS + * pin to ensure a total delay of 5 us; otherwise, the delay is not sufficient. + * The total delay necessary for 5 MHz operation is at most 3.4 us. This is not + * a concern when using I2C mode because the communication rate is low enough + * to ensure a sufficient delay between FIFO reads. + * Ref: "Retrieving Data from FIFO", p. 21 of 36, Data Sheet ADXL345 Rev. G + * * Return: 0 on success, negative errno on error */ int adxl345_core_probe(struct device *dev, struct regmap *regmap, + bool fifo_delay_default, int (*setup)(struct device*, struct regmap*)) { struct adxl345_state *st; @@ -222,6 +232,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st->info = device_get_match_data(dev); if (!st->info) return -ENODEV; + st->fifo_delay = fifo_delay_default; indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; diff --git a/drivers/iio/accel/adxl345_i2c.c b/drivers/iio/accel/adxl345_i2c.c index e550bc078..eb3e0aadf 100644 --- a/drivers/iio/accel/adxl345_i2c.c +++ b/drivers/iio/accel/adxl345_i2c.c @@ -27,7 +27,7 @@ static int adxl345_i2c_probe(struct i2c_client *client) if (IS_ERR(regmap)) return dev_err_probe(&client->dev, PTR_ERR(regmap), "Error initializing regmap\n"); - return adxl345_core_probe(&client->dev, regmap, NULL); + return adxl345_core_probe(&client->dev, regmap, false, NULL); } static const struct adxl345_chip_info adxl345_i2c_info = { diff --git a/drivers/iio/accel/adxl345_spi.c b/drivers/iio/accel/adxl345_spi.c index 61fd9a6f5..e03915ece 100644 --- a/drivers/iio/accel/adxl345_spi.c +++ b/drivers/iio/accel/adxl345_spi.c @@ -12,6 +12,7 @@ #include "adxl345.h" #define ADXL345_MAX_SPI_FREQ_HZ 5000000 +#define ADXL345_MAX_FREQ_NO_FIFO_DELAY 1500000 static const struct regmap_config adxl345_spi_regmap_config = { .reg_bits = 8, @@ -28,6 +29,7 @@ static int adxl345_spi_setup(struct device *dev, struct regmap *regmap) static int adxl345_spi_probe(struct spi_device *spi) { struct regmap *regmap; + bool needs_delay; /* Bail out if max_speed_hz exceeds 5 MHz */ if (spi->max_speed_hz > ADXL345_MAX_SPI_FREQ_HZ) @@ -38,10 +40,11 @@ static int adxl345_spi_probe(struct spi_device *spi) if (IS_ERR(regmap)) return dev_err_probe(&spi->dev, PTR_ERR(regmap), "Error initializing regmap\n"); + needs_delay = spi->max_speed_hz > ADXL345_MAX_FREQ_NO_FIFO_DELAY; if (spi->mode & SPI_3WIRE) - return adxl345_core_probe(&spi->dev, regmap, adxl345_spi_setup); + return adxl345_core_probe(&spi->dev, regmap, needs_delay, adxl345_spi_setup); else - return adxl345_core_probe(&spi->dev, regmap, NULL); + return adxl345_core_probe(&spi->dev, regmap, needs_delay, NULL); } static const struct adxl345_chip_info adxl345_spi_info = { From patchwork Wed Dec 25 18:13:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920845 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FB761C5494; Wed, 25 Dec 2024 18:14:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150442; cv=none; b=cncESGxkTO+5WnMAsRad3ZPjxnbhaxkZF5ORwV+eINKwQH59pEML6pix2O+Q4fGXd14EEV+S9gE9LAC+HGGTfyDtrLKDf6WHILIHtJjfkS3zcBw24zbfFuZObIS5/+Lqas1o0+Ls/TMejk6j+dKpT9YErsWWkie/fEACPYuIuvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150442; c=relaxed/simple; bh=Le/s+SyHKXyroOA9DhfCDkTEe+IMGKHxxr5HmAv219s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=plzIcSpebaM8GU1NyJdjLK+rB70LdUYd0vd7JrKacWS5z19SA4ZIRINEUWXrFRWZJaG8zDLSiSeIJR9tBP+fFyLSfuPRnPbtyd5j+djmsxYZRXYPEYVW+r0OChCkg8ngB3q1NIFm0hH0WhUeeMy+w5O07zkCdmOLgucV1OrS6Z8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EP0LiSgL; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EP0LiSgL" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5d3c0bd1cc4so930494a12.0; Wed, 25 Dec 2024 10:13:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150438; x=1735755238; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5JjEA038y3TmejJYPJ6Nj2xcYH8VqNwNz8pPtNDltxo=; b=EP0LiSgLqPBqX681J4s3gwG4RkttSQIs7+aoCK86cAS5ZXnygzJwcJu/2W94gE8X4e x1IFqKVRhshSNDGqbSue95EWDJNTJ8S9f5Aa+q29Fkerpw2iLiECE/0LBgVMY0Oh6HyM FK9o6R4NeXbojCd6/W411wLO7oyaHBVQkEJ6f3uWMSWHRXL6ZqKjFTPIHkowW4SlMOCD kNzM/ElGduFeLwIPDaa+fDJedBXyCCEEaT45+lIeAjsT2CZm6Yw+BM7odyO7JH5L6wBt yCzGeQKkTADREGfqztYtkqzdUAnsc+8NLV0EePFYB3N/QSIdtJfEdqIuQiCyka/Fysc/ plJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150438; x=1735755238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5JjEA038y3TmejJYPJ6Nj2xcYH8VqNwNz8pPtNDltxo=; b=oyFP1oCT4N8J5WAO+tC//O1cciQ/ai3zJuAJoZ1GjmJHBtn/nOubNAuu19tndRDpv0 NBWLeHqNnmFrO3evM2O6kkmVes5L4C8OWc4cpt9/MuCqeNDV18nsC9AVQt6dAomGLAoK B4qvOuEHxUd+0iLvJR5IBUsd2IcptwGTk66Ltot6P91srZl8FhA0u0egLA1lugwfMUeS uCLFZSi+eWgPWCMjjuHMZ3qF6F2xztTuNBIgoPKUQOqvA2GW2uc48hpjrcKb8bFvPr5M LXPC3v2pFxy6FJdoGV7IvupxzECTdn/xSY9Gd0g8622BgYpUfn2/yWowBlHifjWodGHP h63A== X-Forwarded-Encrypted: i=1; AJvYcCVqkTSKZPFWMZcf6X5fC22eGmbsTVhbbP/ZBPq3bl8AyOQ6R28IycYxu2UFNNlG5hAsQ5y39jmMCTo=@vger.kernel.org, AJvYcCXgxUXBoPmFiTodQlWgJChSQa+JhvFmuGg5dX6uG9BazrISIU8bCm1xGLy2yrwkMUIlHVT+w3ZqWKtEgq8d@vger.kernel.org X-Gm-Message-State: AOJu0YyXQqhRa4z2w7lHBphWB+MoNcAB20mNJPF2pflNbyOr5S+cTwNY ffELOANSgMdONj+ZFP7Ipt4KubyuDtfcxgdecch77rzqw2uQBBcU X-Gm-Gg: ASbGncvmXzvkeGw3rz90FeGRVVth+WmFVpLwiF5+tsHdfwK4prAO10NAWM3D2KpOLMJ a5yGYVsOYcrFMM6CSxRRfTBnak4DED5JT9k0B/W57EobnMrkm+OkLXShI/+qcJ+5TGAhIYn714u Ym2mqki5cxuAWVkliTTghTryEDNF8iLp/Ycn0rJcDQMMqk4jSLLJOuJC8KXXP7niMR/g+czaGhq BkKing82jN4mjeGYEkeW5m9T8S311NixSMSPjQBS1dufPYaTgJdzKD3A5aEyVUvGf6Vo3djobHT fEJ3DIwhSK+iB5oo4m24S3n4bbjQMrYYQ+g= X-Google-Smtp-Source: AGHT+IHh8KDmr9RmZfwnOzqqGGsI7oDawjlA1jghXwQyseqCCdd+WxE3ldimpzTJEAffjYy9KHhLnQ== X-Received: by 2002:a05:6402:13cf:b0:5d3:d4cf:feba with SMTP id 4fb4d7f45d1cf-5d81de078a3mr6906509a12.7.1735150438324; Wed, 25 Dec 2024 10:13:58 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:57 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 6/7] iio: accel: adxl345: add FIFO with watermark events Date: Wed, 25 Dec 2024 18:13:37 +0000 Message-Id: <20241225181338.69672-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a basic setup for FIFO with configurable watermark. Add a handler for watermark interrupt events and extend the channel for the scan_index needed for the iio channel. The sensor is configurable to use a FIFO_BYPASSED mode or a FIFO_STREAM mode. For the FIFO_STREAM mode now a watermark can be configured, or disabled by setting 0. Further features require a working FIFO setup. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 27 ++- drivers/iio/accel/adxl345_core.c | 305 ++++++++++++++++++++++++++++++- 2 files changed, 321 insertions(+), 11 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index 6f39f16d3..bf9e86cff 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -15,18 +15,32 @@ #define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) #define ADXL345_REG_BW_RATE 0x2C #define ADXL345_REG_POWER_CTL 0x2D +#define ADXL345_REG_INT_ENABLE 0x2E +#define ADXL345_REG_INT_MAP 0x2F +#define ADXL345_REG_INT_SOURCE 0x30 +#define ADXL345_REG_INT_SOURCE_MSK 0xFF #define ADXL345_REG_DATA_FORMAT 0x31 -#define ADXL345_REG_DATAX0 0x32 -#define ADXL345_REG_DATAY0 0x34 -#define ADXL345_REG_DATAZ0 0x36 -#define ADXL345_REG_DATA_AXIS(index) \ - (ADXL345_REG_DATAX0 + (index) * sizeof(__le16)) +#define ADXL345_REG_XYZ_BASE 0x32 +#define ADXL345_REG_DATA_AXIS(index) \ + (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) +#define ADXL345_REG_FIFO_CTL 0x38 +#define ADXL345_REG_FIFO_STATUS 0x39 +#define ADXL345_REG_FIFO_STATUS_MSK 0x3F + +#define ADXL345_FIFO_CTL_SAMPLES(x) FIELD_PREP(GENMASK(4, 0), x) +/* 0: INT1, 1: INT2 */ +#define ADXL345_FIFO_CTL_TRIGGER(x) FIELD_PREP(BIT(5), x) +#define ADXL345_FIFO_CTL_MODE(x) FIELD_PREP(GENMASK(7, 6), x) + +#define ADXL345_INT_DATA_READY BIT(7) +#define ADXL345_INT_WATERMARK BIT(1) +#define ADXL345_INT_OVERRUN BIT(0) #define ADXL345_BW_RATE GENMASK(3, 0) #define ADXL345_BASE_RATE_NANO_HZ 97656250LL -#define ADXL345_POWER_CTL_MEASURE BIT(3) #define ADXL345_POWER_CTL_STANDBY 0x00 +#define ADXL345_POWER_CTL_MEASURE BIT(3) #define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */ #define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */ @@ -40,6 +54,7 @@ #define ADXL345_DATA_FORMAT_16G 3 #define ADXL345_DEVID 0xE5 +#define ADXL345_FIFO_SIZE 32 /* * In full-resolution mode, scale factor is maintained at ~4 mg/LSB diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 987a0fe03..738960298 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -15,9 +15,17 @@ #include #include +#include +#include #include "adxl345.h" +#define ADXL345_FIFO_BYPASS 0 +#define ADXL345_FIFO_FIFO 1 +#define ADXL345_FIFO_STREAM 2 + +#define ADXL345_DIRS 3 + #define ADXL345_INT_NONE 0xff #define ADXL345_INT1 0 #define ADXL345_INT2 1 @@ -28,25 +36,66 @@ struct adxl345_state { bool fifo_delay; /* delay: delay is needed for SPI */ int irq; u8 intio; + u8 int_map; + u8 watermark; + u8 fifo_mode; + __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); }; -#define ADXL345_CHANNEL(index, axis) { \ +#define ADXL345_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .modified = 1, \ .channel2 = IIO_MOD_##axis, \ - .address = index, \ + .address = (reg), \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_CALIBBIAS), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = (index), \ + .scan_type = { \ + .sign = 's', \ + .realbits = 13, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ } +enum adxl345_chans { + chan_x, chan_y, chan_z, +}; + static const struct iio_chan_spec adxl345_channels[] = { - ADXL345_CHANNEL(0, X), - ADXL345_CHANNEL(1, Y), - ADXL345_CHANNEL(2, Z), + ADXL345_CHANNEL(0, chan_x, X), + ADXL345_CHANNEL(1, chan_y, Y), + ADXL345_CHANNEL(2, chan_z, Z), }; +static const unsigned long adxl345_scan_masks[] = { + BIT(chan_x) | BIT(chan_y) | BIT(chan_z), + 0 +}; + +static int adxl345_set_interrupts(struct adxl345_state *st) +{ + int ret; + unsigned int int_enable = st->int_map; + unsigned int int_map; + + /* + * Any bits set to 0 in the INT map register send their respective + * interrupts to the INT1 pin, whereas bits set to 1 send their respective + * interrupts to the INT2 pin. The intio shall convert this accordingly. + */ + int_map = FIELD_GET(ADXL345_REG_INT_SOURCE_MSK, + st->intio ? st->int_map : ~st->int_map); + + ret = regmap_write(st->regmap, ADXL345_REG_INT_MAP, int_map); + if (ret) + return ret; + + return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, int_enable); +} + static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -132,6 +181,24 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int value) +{ + struct adxl345_state *st = iio_priv(indio_dev); + unsigned int fifo_mask = 0x1F; + int ret; + + value = min(value, ADXL345_FIFO_SIZE - 1); + + ret = regmap_update_bits(st->regmap, ADXL345_REG_FIFO_CTL, fifo_mask, value); + if (ret) + return ret; + + st->watermark = value; + st->int_map |= ADXL345_INT_WATERMARK; + + return 0; +} + static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long mask) @@ -186,11 +253,217 @@ static const struct attribute_group adxl345_attrs_group = { .attrs = adxl345_attrs, }; +static int adxl345_set_fifo(struct adxl345_state *st) +{ + int ret; + + /* FIFO should only be configured while in standby mode */ + ret = adxl345_set_measure_en(st, false); + if (ret < 0) + return ret; + + ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, + ADXL345_FIFO_CTL_SAMPLES(st->watermark) | + ADXL345_FIFO_CTL_TRIGGER(st->intio) | + ADXL345_FIFO_CTL_MODE(st->fifo_mode)); + if (ret < 0) + return ret; + + return adxl345_set_measure_en(st, true); +} + +/** + * adxl345_get_samples() - Read number of FIFO entries. + * @st: The initialized state instance of this driver. + * + * The sensor does not support treating any axis individually, or exclude them + * from measuring. + * + * Return: negative error, or value. + */ +static int adxl345_get_samples(struct adxl345_state *st) +{ + unsigned int regval = 0; + int ret; + + ret = regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, ®val); + if (ret < 0) + return ret; + + return FIELD_GET(ADXL345_REG_FIFO_STATUS_MSK, regval); +} + +/** + * adxl345_fifo_transfer() - Read samples number of elements. + * @st: The instance of the state object of this sensor. + * @samples: The number of lines in the FIFO referred to as fifo_entry. + * + * It is recommended that a multiple-byte read of all registers be performed to + * prevent a change in data between reads of sequential registers. That is to + * read out the data registers X0, X1, Y0, Y1, Z0, Z1, i.e. 6 bytes at once. + * + * Return: 0 or error value. + */ +static int adxl345_fifo_transfer(struct adxl345_state *st, int samples) +{ + size_t count; + int i, ret = 0; + + /* count is the 3x the fifo_buf element size, hence 6B */ + count = sizeof(st->fifo_buf[0]) * ADXL345_DIRS; + for (i = 0; i < samples; i++) { + /* read 3x 2 byte elements from base address into next fifo_buf position */ + ret = regmap_bulk_read(st->regmap, ADXL345_REG_XYZ_BASE, + st->fifo_buf + (i * count / 2), count); + if (ret < 0) + return ret; + + /* + * To ensure that the FIFO has completely popped, there must be at least 5 + * us between the end of reading the data registers, signified by the + * transition to register 0x38 from 0x37 or the CS pin going high, and the + * start of new reads of the FIFO or reading the FIFO_STATUS register. For + * SPI operation at 1.5 MHz or lower, the register addressing portion of the + * transmission is sufficient delay to ensure the FIFO has completely + * popped. It is necessary for SPI operation greater than 1.5 MHz to + * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us + * at 5 MHz operation. + */ + if (st->fifo_delay && samples > 1) + udelay(3); + } + return ret; +} + +/** + * adxl345_fifo_reset() - Empty the FIFO in error condition. + * @st: The instance to the state object of the sensor. + * + * Read all elements of the FIFO. Reading the interrupt source register + * resets the sensor. + */ +static void adxl345_fifo_reset(struct adxl345_state *st) +{ + int regval; + int samples; + + adxl345_set_measure_en(st, false); + + samples = adxl345_get_samples(st); + if (samples > 0) + adxl345_fifo_transfer(st, samples); + + regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); + + adxl345_set_measure_en(st, true); +} + +static int adxl345_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int ret; + + ret = adxl345_set_interrupts(st); + if (ret < 0) + return ret; + + st->fifo_mode = ADXL345_FIFO_STREAM; + return adxl345_set_fifo(st); +} + +static int adxl345_buffer_predisable(struct iio_dev *indio_dev) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int ret; + + st->fifo_mode = ADXL345_FIFO_BYPASS; + ret = adxl345_set_fifo(st); + if (ret < 0) + return ret; + + st->int_map = 0x00; + return adxl345_set_interrupts(st); +} + +static const struct iio_buffer_setup_ops adxl345_buffer_ops = { + .postenable = adxl345_buffer_postenable, + .predisable = adxl345_buffer_predisable, +}; + +static int adxl345_get_status(struct adxl345_state *st) +{ + int ret; + unsigned int regval; + + ret = regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); + if (ret < 0) + return ret; + + return FIELD_GET(ADXL345_REG_INT_SOURCE_MSK, regval); +} + +static int adxl345_fifo_push(struct iio_dev *indio_dev, + int samples) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int i, ret; + + if (samples <= 0) + return -EINVAL; + + ret = adxl345_fifo_transfer(st, samples); + if (ret) + return ret; + + for (i = 0; i < ADXL345_DIRS * samples; i += ADXL345_DIRS) + iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); + + return 0; +} + +/** + * adxl345_irq_handler() - Handle irqs of the ADXL345. + * @irq: The irq being handled. + * @p: The struct iio_device pointer for the device. + * + * Return: The interrupt was handled. + */ +static irqreturn_t adxl345_irq_handler(int irq, void *p) +{ + struct iio_dev *indio_dev = p; + struct adxl345_state *st = iio_priv(indio_dev); + int int_stat; + int samples; + + int_stat = adxl345_get_status(st); + if (int_stat <= 0) + return IRQ_NONE; + + if (int_stat & ADXL345_INT_OVERRUN) + goto err; + + if (int_stat & ADXL345_INT_WATERMARK) { + samples = adxl345_get_samples(st); + if (samples < 0) + goto err; + + if (adxl345_fifo_push(indio_dev, samples) < 0) + goto err; + } + return IRQ_HANDLED; + +err: + adxl345_fifo_reset(st); + + return IRQ_HANDLED; +} + static const struct iio_info adxl345_info = { .attrs = &adxl345_attrs_group, .read_raw = adxl345_read_raw, .write_raw = adxl345_write_raw, .write_raw_get_fmt = adxl345_write_raw_get_fmt, + .hwfifo_set_watermark = adxl345_set_watermark, }; /** @@ -221,6 +494,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, ADXL345_DATA_FORMAT_JUSTIFY | ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); + u8 fifo_ctl; int ret; indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); @@ -239,6 +513,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = adxl345_channels; indio_dev->num_channels = ARRAY_SIZE(adxl345_channels); + indio_dev->available_scan_masks = adxl345_scan_masks; if (setup) { /* Perform optional initial bus specific configuration */ @@ -289,6 +564,26 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st->intio = ADXL345_INT_NONE; } + if (st->intio != ADXL345_INT_NONE) { + /* FIFO_STREAM mode is going to be activated later */ + ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &adxl345_buffer_ops); + if (ret) + return ret; + + ret = devm_request_threaded_irq(dev, st->irq, NULL, + &adxl345_irq_handler, + IRQF_SHARED | IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return ret; + } else { + /* FIFO_BYPASS mode */ + fifo_ctl = ADXL345_FIFO_CTL_MODE(ADXL345_FIFO_BYPASS); + ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); + if (ret < 0) + return ret; + } + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(adxl345_core_probe, IIO_ADXL345); From patchwork Wed Dec 25 18:13:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13920846 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 770841CEEB4; Wed, 25 Dec 2024 18:14:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150444; cv=none; b=neBRcY19mNS/Kfh6Oz5dw9NbEC5S9H5iIixQnemcTPNeS7+osxKwMJGqJBg0RpN3K+46bGDAww3G/I/iJrrHTkopOyE+0Pczsg2/duBWEbN43VP1T8rrS38egzsnW+zcerMS5azK9JWbV9GWbm1YapR4UPVnJfEIMO6Byh+/+RE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735150444; c=relaxed/simple; bh=s/2Sud8tbTn3DV/gVz7omCuTc6DCCbix5hAZkUvCcyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qB8mdzyLcelgSaL+jQybk6w7Fa+wTNDUPeUnHvl7+cFo3uX1jcZy+oOLjoXuyKmlK4qxNP+vP/28ZuyDaQUotLjllZy1zCUHc7i1VgGDdwAHph0vjpn6vcj6xDe7XMU1lyXSVP+ggKgq3S4V28al1QzspNYnzqLNRSxgyiAUY0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NERIU9vK; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NERIU9vK" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-aab73e995b5so108986666b.0; Wed, 25 Dec 2024 10:14:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735150441; x=1735755241; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CYq2MT/kLJ5VNDS2ggKYbL2pEgZu56efpig6dGEeYSQ=; b=NERIU9vK3wYVexb1CbTAwY/MQ3lo71xY+OPovy144ncCQPwTzqgBck4QwcKGIlInYA 4GwwcIG9vPBuDe3YV9MMfhs3BjJSb3yu3YqTV0dpVh3SUskRRQR0jURAnlapyMGkl3W7 cCmbjdQ1W7dBKv7GEUYL6nUob6N4548aYOIIXHARDziT1AS94MLAXHq5wZJ1SpVIHUwT B+CfSPvq9nkvXTvjsPSYYRYmUPeGHPIio6v5eadqZIJd9aCZoCEZX++gladM+Zmpw1XG 1/huU4toV4XZDzdNpvsO0OWRMjG7wVIfgDuHBUbu+jvoDVFDX9e3tZal379XSurTqqec kgTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735150441; x=1735755241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CYq2MT/kLJ5VNDS2ggKYbL2pEgZu56efpig6dGEeYSQ=; b=gfAGbfEMqos6zqH82sLhucdQyWwaURTHv3WjD7PzDMnUpWcULrhp1khDw5v11xC6Gr 56IGrGhd8fa8PLiMZpaguRHPhUM5qGHl8kAO45la4yBUM5FhTTy2yXlotOE5vtFuex08 3w0Ovbn0NvDZ6Ues+pRf78Nl9C23Gt0/BlwInu0M9gyHG1qEJPOrYyd/gRi5UD9I9ea6 kgmWivZPQ/xBhTxqHJ5Z5FDjdmQCXypmTNWPwRBljaGnYV8+BMLpfEEphnjZQLplduky DMWuqRWN45B/8i+PAnljHHFLam5Iw6fBTIgPtrw5jvTGZIHcA0QllMjtXUraKaKQvx3u YIwg== X-Forwarded-Encrypted: i=1; AJvYcCUdKR63hCHHk8eJqBQ/mqxucAyBdXIMwJxKrkUG7t1/Vmf7kzhhCZ5CWpITKo4Ic+SsMciBONLWaSw=@vger.kernel.org, AJvYcCVO7w06Q+L6lEKQvIKFo/WYvWuoFzqWSKQnYprbOgcfe3qdiptuqTgMA5eCRlXK2LRjI9QYdyYufQhSTVm9@vger.kernel.org X-Gm-Message-State: AOJu0YzTXKaVkk34Fn7KeTAFTR6YBzJbh7mJF3HP0DqYNay5BDdLsRxG EQiQArKgnL4FRTnTZQOXmO93CRZyg3ZVnlpA1ICWs4CwQl9RSTUY X-Gm-Gg: ASbGnctfFX+y6rcd7m9pBB1c9qpd0l4SPZh6JhkFo3SykX+vJ54ZkelVimmliaSl5RM ouCrZgADVw3qqTFFhNXRk+zSCXMbSuSf3i0eFZawIILUa5anxg5NhwsaJHGomnzNxCrUtWh5LYo A23X2vJYav1RnT7u+B1lHdtpuCcU99nHMatheM9gnlQGqxvIO96kG1JLUBV0T+IegZq+8JQbsiK vSA4xQ/xpc7h8K0mzMElGrLWbC2BbssV8huTh4UinqLZG/mCKRtIE2Xj4vxdK0jQlMO40L8orC2 BuBNrPWWANfkR+iV7SqyOdocyyLrTgsSac4= X-Google-Smtp-Source: AGHT+IF6H0bMBaPLluCSQabzlTudYAwuj5SbVP2NOXXbbHTsdrugpv+mucLR3NL6+vnLMnQ/uoBu3w== X-Received: by 2002:a05:6402:5109:b0:5d0:bd3b:b9a9 with SMTP id 4fb4d7f45d1cf-5d81de1c38cmr7396409a12.8.1735150440821; Wed, 25 Dec 2024 10:14:00 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701ca31sm7721141a12.88.2024.12.25.10.13.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Dec 2024 10:13:59 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 7/7] iio: accel: adxl345: complete the list of defines Date: Wed, 25 Dec 2024 18:13:38 +0000 Message-Id: <20241225181338.69672-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241225181338.69672-1-l.rubusch@gmail.com> References: <20241225181338.69672-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Having interrupts events and FIFO available allows to evaluate the sensor events. Cover the list of interrupt based sensor events. Keep them in the header file for readability. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 57 +++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index bf9e86cff..df3977bda 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -9,10 +9,35 @@ #define _ADXL345_H_ #define ADXL345_REG_DEVID 0x00 +#define ADXL345_REG_THRESH_TAP 0x1D #define ADXL345_REG_OFSX 0x1E #define ADXL345_REG_OFSY 0x1F #define ADXL345_REG_OFSZ 0x20 #define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) + +/* Tap duration */ +#define ADXL345_REG_DUR 0x21 +/* Tap latency */ +#define ADXL345_REG_LATENT 0x22 +/* Tap window */ +#define ADXL345_REG_WINDOW 0x23 +/* Activity threshold */ +#define ADXL345_REG_THRESH_ACT 0x24 +/* Inactivity threshold */ +#define ADXL345_REG_THRESH_INACT 0x25 +/* Inactivity time */ +#define ADXL345_REG_TIME_INACT 0x26 +/* Axis enable control for activity and inactivity detection */ +#define ADXL345_REG_ACT_INACT_CTRL 0x27 +/* Free-fall threshold */ +#define ADXL345_REG_THRESH_FF 0x28 +/* Free-fall time */ +#define ADXL345_REG_TIME_FF 0x29 +/* Axis control for single tap or double tap */ +#define ADXL345_REG_TAP_AXIS 0x2A +/* Source of single tap or double tap */ +#define ADXL345_REG_ACT_TAP_STATUS 0x2B +/* Data rate and power mode control */ #define ADXL345_REG_BW_RATE 0x2C #define ADXL345_REG_POWER_CTL 0x2D #define ADXL345_REG_INT_ENABLE 0x2E @@ -34,20 +59,40 @@ #define ADXL345_FIFO_CTL_MODE(x) FIELD_PREP(GENMASK(7, 6), x) #define ADXL345_INT_DATA_READY BIT(7) +#define ADXL345_INT_SINGLE_TAP BIT(6) +#define ADXL345_INT_DOUBLE_TAP BIT(5) +#define ADXL345_INT_ACTIVITY BIT(4) +#define ADXL345_INT_INACTIVITY BIT(3) +#define ADXL345_INT_FREE_FALL BIT(2) #define ADXL345_INT_WATERMARK BIT(1) #define ADXL345_INT_OVERRUN BIT(0) + +#define ADXL345_S_TAP_MSK ADXL345_INT_SINGLE_TAP +#define ADXL345_D_TAP_MSK ADXL345_INT_DOUBLE_TAP + +/* + * BW_RATE bits - Bandwidth and output data rate. The default value is + * 0x0A, which translates to a 100 Hz output data rate + */ #define ADXL345_BW_RATE GENMASK(3, 0) +#define ADXL345_BW_LOW_POWER BIT(4) #define ADXL345_BASE_RATE_NANO_HZ 97656250LL #define ADXL345_POWER_CTL_STANDBY 0x00 +#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0) +#define ADXL345_POWER_CTL_SLEEP BIT(2) #define ADXL345_POWER_CTL_MEASURE BIT(3) +#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4) +#define ADXL345_POWER_CTL_LINK BIT(5) -#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */ -#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */ -#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */ -#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */ -#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */ - +/* Set the g range */ +#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) +/* Data is left justified */ +#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) +/* Up to 13-bits resolution */ +#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) +#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) +#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) #define ADXL345_DATA_FORMAT_2G 0 #define ADXL345_DATA_FORMAT_4G 1 #define ADXL345_DATA_FORMAT_8G 2