From patchwork Thu Dec 26 04:58:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13920978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54C23E77188 for ; Thu, 26 Dec 2024 05:11:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yZRP9EHYiDMQSE40KS4tBLSjVo3dw24UwSYUpDAW6ko=; b=JeZlnUAtBD1Y+EditQG1CYHvkA i9/y+7iFTKcYno5atg1nhnZn52jYmz8hfjtraYUTukxSDkc33EVQNVdXfjMJOxfSwh3GwyGnsoO7b 3le1Dwb72pjhF/0JR29ApvXiMARIsFN4XVo8+HMrGrVr+SBpoYcYrGvD+m9jPch5m5mPuFfFxS1lB Y3wltfvYORwGuEqWloADaF01VbiF0p/N+t++VYA5E1yjnx3QTsEyhF9i99qTW903MNRdS81OYDFsq NJBpE8ATQLKmvKoHKC/8jx3jgRlg0bxW8vw8WEKRF9NVpds+45QHVVQH6Ah9SR/O3h3E1yIKPNQSJ yKFu8QyQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQg9K-0000000F8OT-1X6U; Thu, 26 Dec 2024 05:11:06 +0000 Received: from out-173.mta0.migadu.com ([91.218.175.173]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQg7K-0000000F7vh-03VZ for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:09:03 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189739; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yZRP9EHYiDMQSE40KS4tBLSjVo3dw24UwSYUpDAW6ko=; b=F+SNPbVh4FdD9yMy1bAbihcAIbPtkt2JBR5WmXnwwuKaAOgpJCkHP5DeoQLyYfTCFWxtQU 0pzScr+1qMK315KnWelMxeL2unZjvukBMFM0No3D4SItsfW4fxkimOGpGBqBsDg2rzdeTl k+VHNc0ImSufNn5nQhvveMQ3tlIej/rqIvSmxZdu+HZ1XTBbH9eI41Cc0+hoyZdru9ZaIE 2e9gjOmiTbDaEyixvKhXX8b9YjTZIYB+gzXLLxNMaYqQp/Xjy6RBN3PxK7xmkTP1wv4aPo KUFWj7a0zRLuNSYWlb8cpoQ3zl701Gsk+AMEG9+jCDFgf2txg+Rxvk+km3EtjQ== From: Val Packett To: Cc: Fabien Parent , Rob Herring , Lee Jones , Dmitry Torokhov , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Val Packett , Javier Carrasco , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 1/9] dt-bindings: mfd: mt6397: Add bindings for MT6392 PMIC Date: Thu, 26 Dec 2024 01:58:01 -0300 Message-ID: <20241226050205.30241-2-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_210902_193717_164BC3B1 X-CRM114-Status: UNSURE ( 8.04 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Add the currently supported bindings for the MT6392 PMIC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring Acked-for-MFD-by: Lee Jones --- Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 86451f151a6ae..73103922978f7 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -38,6 +38,7 @@ properties: - mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332. - mediatek,mt6358 - mediatek,mt6359 + - mediatek,mt6392 - mediatek,mt6397 - items: - enum: @@ -66,6 +67,7 @@ properties: - mediatek,mt6323-rtc - mediatek,mt6331-rtc - mediatek,mt6358-rtc + - mediatek,mt6392-rtc - mediatek,mt6397-rtc - items: - enum: From patchwork Thu Dec 26 04:58:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13920979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D98AAE7718F for ; Thu, 26 Dec 2024 05:11:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wEHn5u5CBSS63bXiRM0JWdDZPFIQiqFgCShleupUKQI=; b=cyUFZX7+bs9JMvVelBaMknv1MP qU7C8LnMz5z2LFC71beYTGYLeocUsIn0zVedusJTrEb8lMhkMED5YFYX6afNy89MeIlOpFdw0KEJA 20vX5Ugx2MRi1j3rdnRBdP5BAvsT0k4hMr+KnER1RlAof37DwBp6VVal5FiXc0CmLjWtJwxSg522q R0JF8fTthRFu7jy2kdmjpetFqfz78XYFVyhkeV7OlNmC+zHZtj1gMOuPZaIIE6sw17oIXem+wXPuJ xKAOc6G+GJEcz84Z0hLrDf2Y2Bl0SCyejAp3kh9TlVIUfkUqZLqcHcYmpFpju42vkvHs+QNmLxV/c 6bwCWo5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQg9K-0000000F8Ot-42Un; Thu, 26 Dec 2024 05:11:06 +0000 Received: from out-185.mta0.migadu.com ([91.218.175.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQg7l-0000000F80Q-1OeH for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:09:30 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189766; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wEHn5u5CBSS63bXiRM0JWdDZPFIQiqFgCShleupUKQI=; b=tUPp2ZCg9ofEQXvHbGoT85kEwn21T20dnx+bwZ6mLn80nrZKY0To/866ayoBMx1+Mkv7N4 1dFAWz6Vvi0rYySu8cqnWOd7glewOuCxcDnJ3rDlyvW1IcVHDv/s9irW7PN+i+7hFdY5sF +RpFcUEyY0Qg1dyghoQ/0qWwnSF7iMWCCKqpduN3gH8UmhnycykCCkRAJjrc3/QpUancI9 z+kQerAwunDmWjeXWxW/Tcf6sjSjNUlHoN7N5kMN+tYvNFZtKUDYcQJl6uD7r9G5TM2dx6 yo1/wLXUVDmfC2/b2Hc39xMfbQfhTTt1gXtzRat6tX2HCIg5LrmltBS19iYGoQ== From: Val Packett To: Cc: Fabien Parent , Rob Herring , Dmitry Torokhov , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Val Packett , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 2/9] dt-bindings: regulator: add support for MT6392 Date: Thu, 26 Dec 2024 01:58:02 -0300 Message-ID: <20241226050205.30241-3-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_210929_534286_ECD607F0 X-CRM114-Status: UNSURE ( 7.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Add binding documentation of the regulator for MT6392 SoCs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 73103922978f7..f047844782c4d 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -92,6 +92,7 @@ properties: - mediatek,mt6323-regulator - mediatek,mt6358-regulator - mediatek,mt6359-regulator + - mediatek,mt6392-regulator - mediatek,mt6397-regulator - items: - enum: From patchwork Thu Dec 26 04:58:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13920980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC1E7E7718D for ; Thu, 26 Dec 2024 05:12:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0D5npsDI8iXbhIUUM/dj63aVNlFAoEQXooWigDRnPe0=; b=SMMgpTiKe+H4mKrkdo8E+CONUz jzrl3D1wdxoA4RJsdAKXKT/I/kkkFVLJWDuUK/wVJF6fol/DstJB7OLjiGR1GxGabyKgBgNUxgcr8 dSSISd8Gam/ojzhUcyhcWdEpXX72x3NGJNpJhFViqUp3yIA9eo9zyh/XODVoh/Am1tvM6NEUP34kH ByO4X2Uj9XXXU7+H59M4vKQOdvwPkjE7kMzN8WsLbk5et4sFSlxFnPwdIn/m/1WGQJ/OrqoYsewfZ B+krDFc6KyP+sH6pGOzZeuUCsaB08NpKWuA9PubYVxKOKasJ/ydpETqAzzP1/+Qrn+LZx/Gt2kBUd ecIzMUyw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQgAV-0000000F8k8-08aa; Thu, 26 Dec 2024 05:12:19 +0000 Received: from out-170.mta0.migadu.com ([2001:41d0:1004:224b::aa]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQg8G-0000000F88C-1Bsd for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:10:01 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189796; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0D5npsDI8iXbhIUUM/dj63aVNlFAoEQXooWigDRnPe0=; b=nTTDPQRbmBi6Huy14ecpoysSPY0QU5vsc3yBgLkMs7zTd9fhU/gp+OlhYuE3S1sV21tuYf db+UVEBrLbCW2Zb2N6YHhzRUdNDxag8NG6lrlkZ6jCxrR/gOotdLS8F2+MoDbeAdfK78UY gYgLh/mYxQyNrAdi+XfR4rWhBTKEAvAl4eaU02k5asVAasR1OnqqgXmj4HPekrnfbv8py8 F2S3SYbwrBeRn+Fx0VqHiFjpa29vzDLTXBvTdIyRik6u2WQTCi9tnepRVWOh4bUSfwnoBG 53roAP82tp5LtkqV0XjreU2JomJAxbjLv/Ecm/hbjVHK4eXRyoxPgo0RcIJxHg== From: Val Packett To: Cc: Fabien Parent , Rob Herring , Dmitry Torokhov , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Val Packett , Javier Carrasco , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 3/9] dt-bindings: input: mtk-pmic-keys: add MT6392 binding definition Date: Thu, 26 Dec 2024 01:58:03 -0300 Message-ID: <20241226050205.30241-4-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211000_472927_04BEF1D1 X-CRM114-Status: UNSURE ( 7.27 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Add the binding documentation of the mtk-pmic-keys for the MT6392 PMICs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index 60f09caa0e4c7..5da4fbce33970 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6359-keys + - mediatek,mt6392-keys - mediatek,mt6397-keys power-off-time-sec: true From patchwork Thu Dec 26 04:58:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13920981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29D2EE77188 for ; Thu, 26 Dec 2024 05:13:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=q0xySs+0TTRuFXLCn4V7fbhC5s72qrpfEbcaWQ+SM00=; b=cRX8cw34MMlW69+Y/gja/SuYlw qRFng4id72k30tiq891J0SK58VLA3w2fU9IZ/DrwB+ubW3IFTu3uOZ3C5Ccq4yrabpKv8eLyf1VlA w3qMSfF40G8Ui7uZ6KuCFnQdKJt/yxDrkeHlJT+5btJswyMUMG7eKRO9K+Mfv2pEjTqXJuWPyP7oL LQ9JPKkPLYah1Od7jslcSobOA+WtAt2jLma7dmN0FCaKpVvMxl62lMEfB8StolfTCfZazGNEcAwZA /DH6BgjqlZ5aB3yOTcYh7IDHca40K49+O5Yxx3yhGn0NPBBjO1PcVtmCIsIEFsRj4lPoYmMVXjZng P0dgS9mw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQgBt-0000000F970-0mdQ; Thu, 26 Dec 2024 05:13:45 +0000 Received: from out-184.mta0.migadu.com ([91.218.175.184]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQg8i-0000000F8FT-0mbb; Thu, 26 Dec 2024 05:10:30 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189824; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q0xySs+0TTRuFXLCn4V7fbhC5s72qrpfEbcaWQ+SM00=; b=BmasDV4uFwZ9KBWb8oT96gUFbUQa/+xMUYwN2NxYvEay0sJPLKx6uW33hzbkjFOOA/+rjp rfdggialjVqyV4ZCk0Miq+D9wz1gRgdMZ2DKEXeo/DbzpZADgsQswbDQHDnSjQe72SJS5+ ly/rYuG27C4Lgx1mxKefGrf26MbdK3JlUGjoheTT4hVwkOeFKjbdtKhIqDeDXMB+GJIvvB +MOmyaJSee1D4iAzVf0A1tImjoXT4QmiZF7ZJK0tu+K7aLSAvYl1Qz488Xwe025QnFSnPJ DLoUb/K7HB8Chk4DqbEOFqP6gIEyW/BnkOTm9F1JEaODr8qbYNg64pJOOos68w== From: Val Packett To: Cc: Fabien Parent , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Val Packett , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 4/9] mfd: mt6397: Add support for MT6392 pmic Date: Thu, 26 Dec 2024 01:58:04 -0300 Message-ID: <20241226050205.30241-5-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211028_694069_1EA3E6CF X-CRM114-Status: GOOD ( 18.13 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Update the MT6397 MFD driver to support the MT6392 PMIC. Signed-off-by: Fabien Parent --- drivers/mfd/mt6397-core.c | 43 +++ drivers/mfd/mt6397-irq.c | 8 + include/linux/mfd/mt6392/core.h | 42 +++ include/linux/mfd/mt6392/registers.h | 487 +++++++++++++++++++++++++++ include/linux/mfd/mt6397/core.h | 1 + 5 files changed, 581 insertions(+) create mode 100644 include/linux/mfd/mt6392/core.h create mode 100644 include/linux/mfd/mt6392/registers.h diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 0e5d59ae064a6..54d655668ad8c 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include #define MT6323_RTC_BASE 0x8000 @@ -39,6 +41,9 @@ #define MT6358_RTC_BASE 0x0588 #define MT6358_RTC_SIZE 0x3c +#define MT6392_RTC_BASE 0x8000 +#define MT6392_RTC_SIZE 0x3e + #define MT6397_RTC_BASE 0xe000 #define MT6397_RTC_SIZE 0x3e @@ -65,6 +70,11 @@ static const struct resource mt6358_rtc_resources[] = { DEFINE_RES_IRQ(MT6358_IRQ_RTC), }; +static const struct resource mt6392_rtc_resources[] = { + DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE), + DEFINE_RES_IRQ(MT6392_IRQ_RTC), +}; + static const struct resource mt6397_rtc_resources[] = { DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE), DEFINE_RES_IRQ(MT6397_IRQ_RTC), @@ -108,6 +118,11 @@ static const struct resource mt6331_keys_resources[] = { DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"), }; +static const struct resource mt6392_keys_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6392_IRQ_PWRKEY, "powerkey"), + DEFINE_RES_IRQ_NAMED(MT6392_IRQ_FCHRKEY, "homekey"), +}; + static const struct resource mt6397_keys_resources[] = { DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"), DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"), @@ -241,6 +256,23 @@ static const struct mfd_cell mt6359_devs[] = { }, }; +static const struct mfd_cell mt6392_devs[] = { + { + .name = "mt6397-rtc", + .num_resources = ARRAY_SIZE(mt6392_rtc_resources), + .resources = mt6392_rtc_resources, + .of_compatible = "mediatek,mt6392-rtc", + }, { + .name = "mt6392-regulator", + .of_compatible = "mediatek,mt6392-regulator", + }, { + .name = "mtk-pmic-keys", + .num_resources = ARRAY_SIZE(mt6392_keys_resources), + .resources = mt6392_keys_resources, + .of_compatible = "mediatek,mt6392-keys" + }, +}; + static const struct mfd_cell mt6397_devs[] = { { .name = "mt6397-rtc", @@ -323,6 +355,14 @@ static const struct chip_data mt6359_core = { .irq_init = mt6358_irq_init, }; +static const struct chip_data mt6392_core = { + .cid_addr = MT6392_CID, + .cid_shift = 0, + .cells = mt6392_devs, + .cell_size = ARRAY_SIZE(mt6392_devs), + .irq_init = mt6397_irq_init, +}; + static const struct chip_data mt6397_core = { .cid_addr = MT6397_CID, .cid_shift = 0, @@ -404,6 +444,9 @@ static const struct of_device_id mt6397_of_match[] = { }, { .compatible = "mediatek,mt6359", .data = &mt6359_core, + }, { + .compatible = "mediatek,mt6392", + .data = &mt6392_core, }, { .compatible = "mediatek,mt6397", .data = &mt6397_core, diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c index 1310665200ede..25b16293e3937 100644 --- a/drivers/mfd/mt6397-irq.c +++ b/drivers/mfd/mt6397-irq.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include @@ -203,6 +205,12 @@ int mt6397_irq_init(struct mt6397_chip *chip) chip->int_status[0] = MT6397_INT_STATUS0; chip->int_status[1] = MT6397_INT_STATUS1; break; + case MT6392_CHIP_ID: + chip->int_con[0] = MT6392_INT_CON0; + chip->int_con[1] = MT6392_INT_CON1; + chip->int_status[0] = MT6392_INT_STATUS0; + chip->int_status[1] = MT6392_INT_STATUS1; + break; default: dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id); diff --git a/include/linux/mfd/mt6392/core.h b/include/linux/mfd/mt6392/core.h new file mode 100644 index 0000000000000..4780dab4da929 --- /dev/null +++ b/include/linux/mfd/mt6392/core.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __MFD_MT6392_CORE_H__ +#define __MFD_MT6392_CORE_H__ + +enum mt6392_irq_numbers { + MT6392_IRQ_SPKL_AB = 0, + MT6392_IRQ_SPKL, + MT6392_IRQ_BAT_L, + MT6392_IRQ_BAT_H, + MT6392_IRQ_WATCHDOG, + MT6392_IRQ_PWRKEY, + MT6392_IRQ_THR_L, + MT6392_IRQ_THR_H, + MT6392_IRQ_VBATON_UNDET, + MT6392_IRQ_BVALID_DET, + MT6392_IRQ_CHRDET, + MT6392_IRQ_OV, + MT6392_IRQ_LDO = 16, + MT6392_IRQ_FCHRKEY, + MT6392_IRQ_RELEASE_PWRKEY, + MT6392_IRQ_RELEASE_FCHRKEY, + MT6392_IRQ_RTC, + MT6392_IRQ_VPROC, + MT6392_IRQ_VSYS, + MT6392_IRQ_VCORE, + MT6392_IRQ_TYPE_C_CC, + MT6392_IRQ_TYPEC_H_MAX, + MT6392_IRQ_TYPEC_H_MIN, + MT6392_IRQ_TYPEC_L_MAX, + MT6392_IRQ_TYPEC_L_MIN, + MT6392_IRQ_THR_MAX, + MT6392_IRQ_THR_MIN, + MT6392_IRQ_NAG_C_DLTV, + MT6392_IRQ_NR, +}; + +#endif /* __MFD_MT6392_CORE_H__ */ diff --git a/include/linux/mfd/mt6392/registers.h b/include/linux/mfd/mt6392/registers.h new file mode 100644 index 0000000000000..4f3a6db830d1e --- /dev/null +++ b/include/linux/mfd/mt6392/registers.h @@ -0,0 +1,487 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __MFD_MT6392_REGISTERS_H__ +#define __MFD_MT6392_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6392_CHR_CON0 0x0000 +#define MT6392_CHR_CON1 0x0002 +#define MT6392_CHR_CON2 0x0004 +#define MT6392_CHR_CON3 0x0006 +#define MT6392_CHR_CON4 0x0008 +#define MT6392_CHR_CON5 0x000A +#define MT6392_CHR_CON6 0x000C +#define MT6392_CHR_CON7 0x000E +#define MT6392_CHR_CON8 0x0010 +#define MT6392_CHR_CON9 0x0012 +#define MT6392_CHR_CON10 0x0014 +#define MT6392_CHR_CON11 0x0016 +#define MT6392_CHR_CON12 0x0018 +#define MT6392_CHR_CON13 0x001A +#define MT6392_CHR_CON14 0x001C +#define MT6392_CHR_CON15 0x001E +#define MT6392_CHR_CON16 0x0020 +#define MT6392_CHR_CON17 0x0022 +#define MT6392_CHR_CON18 0x0024 +#define MT6392_CHR_CON19 0x0026 +#define MT6392_CHR_CON20 0x0028 +#define MT6392_CHR_CON21 0x002A +#define MT6392_CHR_CON22 0x002C +#define MT6392_CHR_CON23 0x002E +#define MT6392_CHR_CON24 0x0030 +#define MT6392_CHR_CON25 0x0032 +#define MT6392_CHR_CON26 0x0034 +#define MT6392_CHR_CON27 0x0036 +#define MT6392_CHR_CON28 0x0038 +#define MT6392_CHR_CON29 0x003A +#define MT6392_STRUP_CON0 0x003C +#define MT6392_STRUP_CON2 0x003E +#define MT6392_STRUP_CON3 0x0040 +#define MT6392_STRUP_CON4 0x0042 +#define MT6392_STRUP_CON5 0x0044 +#define MT6392_STRUP_CON6 0x0046 +#define MT6392_STRUP_CON7 0x0048 +#define MT6392_STRUP_CON8 0x004A +#define MT6392_STRUP_CON9 0x004C +#define MT6392_STRUP_CON10 0x004E +#define MT6392_STRUP_CON11 0x0050 +#define MT6392_SPK_CON0 0x0052 +#define MT6392_SPK_CON1 0x0054 +#define MT6392_SPK_CON2 0x0056 +#define MT6392_SPK_CON6 0x005E +#define MT6392_SPK_CON7 0x0060 +#define MT6392_SPK_CON8 0x0062 +#define MT6392_SPK_CON9 0x0064 +#define MT6392_SPK_CON10 0x0066 +#define MT6392_SPK_CON11 0x0068 +#define MT6392_SPK_CON12 0x006A +#define MT6392_STRUP_CON12 0x006E +#define MT6392_STRUP_CON13 0x0070 +#define MT6392_STRUP_CON14 0x0072 +#define MT6392_STRUP_CON15 0x0074 +#define MT6392_STRUP_CON16 0x0076 +#define MT6392_STRUP_CON17 0x0078 +#define MT6392_STRUP_CON18 0x007A +#define MT6392_STRUP_CON19 0x007C +#define MT6392_STRUP_CON20 0x007E +#define MT6392_CID 0x0100 +#define MT6392_TOP_CKPDN0 0x0102 +#define MT6392_TOP_CKPDN0_SET 0x0104 +#define MT6392_TOP_CKPDN0_CLR 0x0106 +#define MT6392_TOP_CKPDN1 0x0108 +#define MT6392_TOP_CKPDN1_SET 0x010A +#define MT6392_TOP_CKPDN1_CLR 0x010C +#define MT6392_TOP_CKPDN2 0x010E +#define MT6392_TOP_CKPDN2_SET 0x0110 +#define MT6392_TOP_CKPDN2_CLR 0x0112 +#define MT6392_TOP_RST_CON 0x0114 +#define MT6392_TOP_RST_CON_SET 0x0116 +#define MT6392_TOP_RST_CON_CLR 0x0118 +#define MT6392_TOP_RST_MISC 0x011A +#define MT6392_TOP_RST_MISC_SET 0x011C +#define MT6392_TOP_RST_MISC_CLR 0x011E +#define MT6392_TOP_CKCON0 0x0120 +#define MT6392_TOP_CKCON0_SET 0x0122 +#define MT6392_TOP_CKCON0_CLR 0x0124 +#define MT6392_TOP_CKCON1 0x0126 +#define MT6392_TOP_CKCON1_SET 0x0128 +#define MT6392_TOP_CKCON1_CLR 0x012A +#define MT6392_TOP_CKTST0 0x012C +#define MT6392_TOP_CKTST1 0x012E +#define MT6392_TOP_CKTST2 0x0130 +#define MT6392_TEST_OUT 0x0132 +#define MT6392_TEST_CON0 0x0134 +#define MT6392_TEST_CON1 0x0136 +#define MT6392_EN_STATUS0 0x0138 +#define MT6392_EN_STATUS1 0x013A +#define MT6392_OCSTATUS0 0x013C +#define MT6392_OCSTATUS1 0x013E +#define MT6392_PGSTATUS 0x0140 +#define MT6392_CHRSTATUS 0x0142 +#define MT6392_TDSEL_CON 0x0144 +#define MT6392_RDSEL_CON 0x0146 +#define MT6392_SMT_CON0 0x0148 +#define MT6392_SMT_CON1 0x014A +#define MT6392_DRV_CON0 0x0152 +#define MT6392_DRV_CON1 0x0154 +#define MT6392_INT_CON0 0x0160 +#define MT6392_INT_CON0_SET 0x0162 +#define MT6392_INT_CON0_CLR 0x0164 +#define MT6392_INT_CON1 0x0166 +#define MT6392_INT_CON1_SET 0x0168 +#define MT6392_INT_CON1_CLR 0x016A +#define MT6392_INT_MISC_CON 0x016C +#define MT6392_INT_MISC_CON_SET 0x016E +#define MT6392_INT_MISC_CON_CLR 0x0170 +#define MT6392_INT_STATUS0 0x0172 +#define MT6392_INT_STATUS1 0x0174 +#define MT6392_OC_GEAR_0 0x0176 +#define MT6392_OC_GEAR_1 0x0178 +#define MT6392_OC_GEAR_2 0x017A +#define MT6392_OC_CTL_VPROC 0x017C +#define MT6392_OC_CTL_VSYS 0x017E +#define MT6392_OC_CTL_VCORE 0x0180 +#define MT6392_FQMTR_CON0 0x0182 +#define MT6392_FQMTR_CON1 0x0184 +#define MT6392_FQMTR_CON2 0x0186 +#define MT6392_RG_SPI_CON 0x0188 +#define MT6392_DEW_DIO_EN 0x018A +#define MT6392_DEW_READ_TEST 0x018C +#define MT6392_DEW_WRITE_TEST 0x018E +#define MT6392_DEW_CRC_SWRST 0x0190 +#define MT6392_DEW_CRC_EN 0x0192 +#define MT6392_DEW_CRC_VAL 0x0194 +#define MT6392_DEW_DBG_MON_SEL 0x0196 +#define MT6392_DEW_CIPHER_KEY_SEL 0x0198 +#define MT6392_DEW_CIPHER_IV_SEL 0x019A +#define MT6392_DEW_CIPHER_EN 0x019C +#define MT6392_DEW_CIPHER_RDY 0x019E +#define MT6392_DEW_CIPHER_MODE 0x01A0 +#define MT6392_DEW_CIPHER_SWRST 0x01A2 +#define MT6392_DEW_RDDMY_NO 0x01A4 +#define MT6392_DEW_RDATA_DLY_SEL 0x01A6 +#define MT6392_CLK_TRIM_CON0 0x01A8 +#define MT6392_BUCK_CON0 0x0200 +#define MT6392_BUCK_CON1 0x0202 +#define MT6392_BUCK_CON2 0x0204 +#define MT6392_BUCK_CON3 0x0206 +#define MT6392_BUCK_CON4 0x0208 +#define MT6392_BUCK_CON5 0x020A +#define MT6392_VPROC_CON0 0x020C +#define MT6392_VPROC_CON1 0x020E +#define MT6392_VPROC_CON2 0x0210 +#define MT6392_VPROC_CON3 0x0212 +#define MT6392_VPROC_CON4 0x0214 +#define MT6392_VPROC_CON5 0x0216 +#define MT6392_VPROC_CON7 0x021A +#define MT6392_VPROC_CON8 0x021C +#define MT6392_VPROC_CON9 0x021E +#define MT6392_VPROC_CON10 0x0220 +#define MT6392_VPROC_CON11 0x0222 +#define MT6392_VPROC_CON12 0x0224 +#define MT6392_VPROC_CON13 0x0226 +#define MT6392_VPROC_CON14 0x0228 +#define MT6392_VPROC_CON15 0x022A +#define MT6392_VPROC_CON18 0x0230 +#define MT6392_VSYS_CON0 0x0232 +#define MT6392_VSYS_CON1 0x0234 +#define MT6392_VSYS_CON2 0x0236 +#define MT6392_VSYS_CON3 0x0238 +#define MT6392_VSYS_CON4 0x023A +#define MT6392_VSYS_CON5 0x023C +#define MT6392_VSYS_CON7 0x0240 +#define MT6392_VSYS_CON8 0x0242 +#define MT6392_VSYS_CON9 0x0244 +#define MT6392_VSYS_CON10 0x0246 +#define MT6392_VSYS_CON11 0x0248 +#define MT6392_VSYS_CON12 0x024A +#define MT6392_VSYS_CON13 0x024C +#define MT6392_VSYS_CON14 0x024E +#define MT6392_VSYS_CON15 0x0250 +#define MT6392_VSYS_CON18 0x0256 +#define MT6392_BUCK_OC_CON0 0x0258 +#define MT6392_BUCK_OC_CON1 0x025A +#define MT6392_BUCK_OC_CON2 0x025C +#define MT6392_BUCK_OC_CON3 0x025E +#define MT6392_BUCK_OC_CON4 0x0260 +#define MT6392_BUCK_OC_VPROC_CON0 0x0262 +#define MT6392_BUCK_OC_VCORE_CON0 0x0264 +#define MT6392_BUCK_OC_VSYS_CON0 0x0266 +#define MT6392_BUCK_ANA_MON_CON0 0x0268 +#define MT6392_BUCK_EFUSE_OC_CON0 0x026A +#define MT6392_VCORE_CON0 0x0300 +#define MT6392_VCORE_CON1 0x0302 +#define MT6392_VCORE_CON2 0x0304 +#define MT6392_VCORE_CON3 0x0306 +#define MT6392_VCORE_CON4 0x0308 +#define MT6392_VCORE_CON5 0x030A +#define MT6392_VCORE_CON7 0x030E +#define MT6392_VCORE_CON8 0x0310 +#define MT6392_VCORE_CON9 0x0312 +#define MT6392_VCORE_CON10 0x0314 +#define MT6392_VCORE_CON11 0x0316 +#define MT6392_VCORE_CON12 0x0318 +#define MT6392_VCORE_CON13 0x031A +#define MT6392_VCORE_CON14 0x031C +#define MT6392_VCORE_CON15 0x031E +#define MT6392_VCORE_CON18 0x0324 +#define MT6392_BUCK_K_CON0 0x032A +#define MT6392_BUCK_K_CON1 0x032C +#define MT6392_BUCK_K_CON2 0x032E +#define MT6392_ANALDO_CON0 0x0400 +#define MT6392_ANALDO_CON1 0x0402 +#define MT6392_ANALDO_CON2 0x0404 +#define MT6392_ANALDO_CON3 0x0406 +#define MT6392_ANALDO_CON4 0x0408 +#define MT6392_ANALDO_CON6 0x040C +#define MT6392_ANALDO_CON7 0x040E +#define MT6392_ANALDO_CON8 0x0410 +#define MT6392_ANALDO_CON10 0x0412 +#define MT6392_ANALDO_CON15 0x0414 +#define MT6392_ANALDO_CON16 0x0416 +#define MT6392_ANALDO_CON17 0x0418 +#define MT6392_ANALDO_CON21 0x0420 +#define MT6392_ANALDO_CON22 0x0422 +#define MT6392_ANALDO_CON23 0x0424 +#define MT6392_ANALDO_CON24 0x0426 +#define MT6392_ANALDO_CON25 0x0428 +#define MT6392_ANALDO_CON26 0x042A +#define MT6392_ANALDO_CON27 0x042C +#define MT6392_ANALDO_CON28 0x042E +#define MT6392_ANALDO_CON29 0x0430 +#define MT6392_DIGLDO_CON0 0x0500 +#define MT6392_DIGLDO_CON2 0x0502 +#define MT6392_DIGLDO_CON3 0x0504 +#define MT6392_DIGLDO_CON5 0x0506 +#define MT6392_DIGLDO_CON6 0x0508 +#define MT6392_DIGLDO_CON7 0x050A +#define MT6392_DIGLDO_CON8 0x050C +#define MT6392_DIGLDO_CON10 0x0510 +#define MT6392_DIGLDO_CON11 0x0512 +#define MT6392_DIGLDO_CON12 0x0514 +#define MT6392_DIGLDO_CON15 0x051A +#define MT6392_DIGLDO_CON20 0x0524 +#define MT6392_DIGLDO_CON21 0x0526 +#define MT6392_DIGLDO_CON23 0x0528 +#define MT6392_DIGLDO_CON24 0x052A +#define MT6392_DIGLDO_CON26 0x052C +#define MT6392_DIGLDO_CON27 0x052E +#define MT6392_DIGLDO_CON28 0x0530 +#define MT6392_DIGLDO_CON29 0x0532 +#define MT6392_DIGLDO_CON30 0x0534 +#define MT6392_DIGLDO_CON31 0x0536 +#define MT6392_DIGLDO_CON32 0x0538 +#define MT6392_DIGLDO_CON33 0x053A +#define MT6392_DIGLDO_CON36 0x0540 +#define MT6392_DIGLDO_CON41 0x0546 +#define MT6392_DIGLDO_CON44 0x054C +#define MT6392_DIGLDO_CON47 0x0552 +#define MT6392_DIGLDO_CON48 0x0554 +#define MT6392_DIGLDO_CON49 0x0556 +#define MT6392_DIGLDO_CON50 0x0558 +#define MT6392_DIGLDO_CON51 0x055A +#define MT6392_DIGLDO_CON52 0x055C +#define MT6392_DIGLDO_CON53 0x055E +#define MT6392_DIGLDO_CON54 0x0560 +#define MT6392_DIGLDO_CON55 0x0562 +#define MT6392_DIGLDO_CON56 0x0564 +#define MT6392_DIGLDO_CON57 0x0566 +#define MT6392_DIGLDO_CON58 0x0568 +#define MT6392_DIGLDO_CON59 0x056A +#define MT6392_DIGLDO_CON60 0x056C +#define MT6392_DIGLDO_CON61 0x056E +#define MT6392_DIGLDO_CON62 0x0570 +#define MT6392_DIGLDO_CON63 0x0572 +#define MT6392_EFUSE_CON0 0x0600 +#define MT6392_EFUSE_CON1 0x0602 +#define MT6392_EFUSE_CON2 0x0604 +#define MT6392_EFUSE_CON3 0x0606 +#define MT6392_EFUSE_CON4 0x0608 +#define MT6392_EFUSE_CON5 0x060A +#define MT6392_EFUSE_CON6 0x060C +#define MT6392_EFUSE_VAL_0_15 0x060E +#define MT6392_EFUSE_VAL_16_31 0x0610 +#define MT6392_EFUSE_VAL_32_47 0x0612 +#define MT6392_EFUSE_VAL_48_63 0x0614 +#define MT6392_EFUSE_VAL_64_79 0x0616 +#define MT6392_EFUSE_VAL_80_95 0x0618 +#define MT6392_EFUSE_VAL_96_111 0x061A +#define MT6392_EFUSE_VAL_112_127 0x061C +#define MT6392_EFUSE_VAL_128_143 0x061E +#define MT6392_EFUSE_VAL_144_159 0x0620 +#define MT6392_EFUSE_VAL_160_175 0x0622 +#define MT6392_EFUSE_VAL_176_191 0x0624 +#define MT6392_EFUSE_VAL_192_207 0x0626 +#define MT6392_EFUSE_VAL_208_223 0x0628 +#define MT6392_EFUSE_VAL_224_239 0x062A +#define MT6392_EFUSE_VAL_240_255 0x062C +#define MT6392_EFUSE_VAL_256_271 0x062E +#define MT6392_EFUSE_VAL_272_287 0x0630 +#define MT6392_EFUSE_VAL_288_303 0x0632 +#define MT6392_EFUSE_VAL_304_319 0x0634 +#define MT6392_EFUSE_VAL_320_335 0x0636 +#define MT6392_EFUSE_VAL_336_351 0x0638 +#define MT6392_EFUSE_VAL_352_367 0x063A +#define MT6392_EFUSE_VAL_368_383 0x063C +#define MT6392_EFUSE_VAL_384_399 0x063E +#define MT6392_EFUSE_VAL_400_415 0x0640 +#define MT6392_EFUSE_VAL_416_431 0x0642 +#define MT6392_RTC_MIX_CON0 0x0644 +#define MT6392_RTC_MIX_CON1 0x0646 +#define MT6392_EFUSE_VAL_432_447 0x0648 +#define MT6392_EFUSE_VAL_448_463 0x064A +#define MT6392_EFUSE_VAL_464_479 0x064C +#define MT6392_EFUSE_VAL_480_495 0x064E +#define MT6392_EFUSE_VAL_496_511 0x0650 +#define MT6392_EFUSE_DOUT_0_15 0x0652 +#define MT6392_EFUSE_DOUT_16_31 0x0654 +#define MT6392_EFUSE_DOUT_32_47 0x0656 +#define MT6392_EFUSE_DOUT_48_63 0x0658 +#define MT6392_EFUSE_DOUT_64_79 0x065A +#define MT6392_EFUSE_DOUT_80_95 0x065C +#define MT6392_EFUSE_DOUT_96_111 0x065E +#define MT6392_EFUSE_DOUT_112_127 0x0660 +#define MT6392_EFUSE_DOUT_128_143 0x0662 +#define MT6392_EFUSE_DOUT_144_159 0x0664 +#define MT6392_EFUSE_DOUT_160_175 0x0666 +#define MT6392_EFUSE_DOUT_176_191 0x0668 +#define MT6392_EFUSE_DOUT_192_207 0x066A +#define MT6392_EFUSE_DOUT_208_223 0x066C +#define MT6392_EFUSE_DOUT_224_239 0x066E +#define MT6392_EFUSE_DOUT_240_255 0x0670 +#define MT6392_EFUSE_DOUT_256_271 0x0672 +#define MT6392_EFUSE_DOUT_272_287 0x0674 +#define MT6392_EFUSE_DOUT_288_303 0x0676 +#define MT6392_EFUSE_DOUT_304_319 0x0678 +#define MT6392_EFUSE_DOUT_320_335 0x067A +#define MT6392_EFUSE_DOUT_336_351 0x067C +#define MT6392_EFUSE_DOUT_352_367 0x067E +#define MT6392_EFUSE_DOUT_368_383 0x0680 +#define MT6392_EFUSE_DOUT_384_399 0x0682 +#define MT6392_EFUSE_DOUT_400_415 0x0684 +#define MT6392_EFUSE_DOUT_416_431 0x0686 +#define MT6392_EFUSE_DOUT_432_447 0x0688 +#define MT6392_EFUSE_DOUT_448_463 0x068A +#define MT6392_EFUSE_DOUT_464_479 0x068C +#define MT6392_EFUSE_DOUT_480_495 0x068E +#define MT6392_EFUSE_DOUT_496_511 0x0690 +#define MT6392_EFUSE_CON7 0x0692 +#define MT6392_EFUSE_CON8 0x0694 +#define MT6392_EFUSE_CON9 0x0696 +#define MT6392_AUXADC_ADC0 0x0700 +#define MT6392_AUXADC_ADC1 0x0702 +#define MT6392_AUXADC_ADC2 0x0704 +#define MT6392_AUXADC_ADC3 0x0706 +#define MT6392_AUXADC_ADC4 0x0708 +#define MT6392_AUXADC_ADC5 0x070A +#define MT6392_AUXADC_ADC6 0x070C +#define MT6392_AUXADC_ADC7 0x070E +#define MT6392_AUXADC_ADC8 0x0710 +#define MT6392_AUXADC_ADC9 0x0712 +#define MT6392_AUXADC_ADC10 0x0714 +#define MT6392_AUXADC_ADC11 0x0716 +#define MT6392_AUXADC_ADC12 0x0718 +#define MT6392_AUXADC_ADC13 0x071A +#define MT6392_AUXADC_ADC14 0x071C +#define MT6392_AUXADC_ADC15 0x071E +#define MT6392_AUXADC_ADC16 0x0720 +#define MT6392_AUXADC_ADC17 0x0722 +#define MT6392_AUXADC_ADC18 0x0724 +#define MT6392_AUXADC_ADC19 0x0726 +#define MT6392_AUXADC_ADC20 0x0728 +#define MT6392_AUXADC_ADC21 0x072A +#define MT6392_AUXADC_ADC22 0x072C +#define MT6392_AUXADC_STA0 0x072E +#define MT6392_AUXADC_STA1 0x0730 +#define MT6392_AUXADC_RQST0 0x0732 +#define MT6392_AUXADC_RQST0_SET 0x0734 +#define MT6392_AUXADC_RQST0_CLR 0x0736 +#define MT6392_AUXADC_CON0 0x0738 +#define MT6392_AUXADC_CON0_SET 0x073A +#define MT6392_AUXADC_CON0_CLR 0x073C +#define MT6392_AUXADC_CON1 0x073E +#define MT6392_AUXADC_CON2 0x0740 +#define MT6392_AUXADC_CON3 0x0742 +#define MT6392_AUXADC_CON4 0x0744 +#define MT6392_AUXADC_CON5 0x0746 +#define MT6392_AUXADC_CON6 0x0748 +#define MT6392_AUXADC_CON7 0x074A +#define MT6392_AUXADC_CON8 0x074C +#define MT6392_AUXADC_CON9 0x074E +#define MT6392_AUXADC_CON10 0x0750 +#define MT6392_AUXADC_CON11 0x0752 +#define MT6392_AUXADC_CON12 0x0754 +#define MT6392_AUXADC_CON13 0x0756 +#define MT6392_AUXADC_CON14 0x0758 +#define MT6392_AUXADC_CON15 0x075A +#define MT6392_AUXADC_CON16 0x075C +#define MT6392_AUXADC_AUTORPT0 0x075E +#define MT6392_AUXADC_LBAT0 0x0760 +#define MT6392_AUXADC_LBAT1 0x0762 +#define MT6392_AUXADC_LBAT2 0x0764 +#define MT6392_AUXADC_LBAT3 0x0766 +#define MT6392_AUXADC_LBAT4 0x0768 +#define MT6392_AUXADC_LBAT5 0x076A +#define MT6392_AUXADC_LBAT6 0x076C +#define MT6392_AUXADC_THR0 0x076E +#define MT6392_AUXADC_THR1 0x0770 +#define MT6392_AUXADC_THR2 0x0772 +#define MT6392_AUXADC_THR3 0x0774 +#define MT6392_AUXADC_THR4 0x0776 +#define MT6392_AUXADC_THR5 0x0778 +#define MT6392_AUXADC_THR6 0x077A +#define MT6392_AUXADC_EFUSE0 0x077C +#define MT6392_AUXADC_EFUSE1 0x077E +#define MT6392_AUXADC_EFUSE2 0x0780 +#define MT6392_AUXADC_EFUSE3 0x0782 +#define MT6392_AUXADC_EFUSE4 0x0784 +#define MT6392_AUXADC_EFUSE5 0x0786 +#define MT6392_AUXADC_NAG_0 0x0788 +#define MT6392_AUXADC_NAG_1 0x078A +#define MT6392_AUXADC_NAG_2 0x078C +#define MT6392_AUXADC_NAG_3 0x078E +#define MT6392_AUXADC_NAG_4 0x0790 +#define MT6392_AUXADC_NAG_5 0x0792 +#define MT6392_AUXADC_NAG_6 0x0794 +#define MT6392_AUXADC_NAG_7 0x0796 +#define MT6392_AUXADC_NAG_8 0x0798 +#define MT6392_AUXADC_TYPEC_H_1 0x079A +#define MT6392_AUXADC_TYPEC_H_2 0x079C +#define MT6392_AUXADC_TYPEC_H_3 0x079E +#define MT6392_AUXADC_TYPEC_H_4 0x07A0 +#define MT6392_AUXADC_TYPEC_H_5 0x07A2 +#define MT6392_AUXADC_TYPEC_H_6 0x07A4 +#define MT6392_AUXADC_TYPEC_H_7 0x07A6 +#define MT6392_AUXADC_TYPEC_L_1 0x07A8 +#define MT6392_AUXADC_TYPEC_L_2 0x07AA +#define MT6392_AUXADC_TYPEC_L_3 0x07AC +#define MT6392_AUXADC_TYPEC_L_4 0x07AE +#define MT6392_AUXADC_TYPEC_L_5 0x07B0 +#define MT6392_AUXADC_TYPEC_L_6 0x07B2 +#define MT6392_AUXADC_TYPEC_L_7 0x07B4 +#define MT6392_AUXADC_NAG_9 0x07B6 +#define MT6392_TYPE_C_PHY_RG_0 0x0800 +#define MT6392_TYPE_C_PHY_RG_CC_RESERVE_CSR 0x0802 +#define MT6392_TYPE_C_VCMP_CTRL 0x0804 +#define MT6392_TYPE_C_CTRL 0x0806 +#define MT6392_TYPE_C_CC_SW_CTRL 0x080a +#define MT6392_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL 0x080c +#define MT6392_TYPE_C_CC_VOL_DEBOUNCE_CNT_VAL 0x080e +#define MT6392_TYPE_C_DRP_SRC_CNT_VAL_0 0x0810 +#define MT6392_TYPE_C_DRP_SNK_CNT_VAL_0 0x0814 +#define MT6392_TYPE_C_DRP_TRY_CNT_VAL_0 0x0818 +#define MT6392_TYPE_C_CC_SRC_DEFAULT_DAC_VAL 0x0820 +#define MT6392_TYPE_C_CC_SRC_15_DAC_VAL 0x0822 +#define MT6392_TYPE_C_CC_SRC_30_DAC_VAL 0x0824 +#define MT6392_TYPE_C_CC_SNK_DAC_VAL_0 0x0828 +#define MT6392_TYPE_C_CC_SNK_DAC_VAL_1 0x082a +#define MT6392_TYPE_C_INTR_EN_0 0x0830 +#define MT6392_TYPE_C_INTR_EN_2 0x0834 +#define MT6392_TYPE_C_INTR_0 0x0838 +#define MT6392_TYPE_C_INTR_2 0x083C +#define MT6392_TYPE_C_CC_STATUS 0x0840 +#define MT6392_TYPE_C_PWR_STATUS 0x0842 +#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_0 0x0844 +#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_1 0x0846 +#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_0 0x0848 +#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_1 0x084a +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_0 0x0860 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_0 0x0864 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_1 0x0866 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_1 0x0868 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_2 0x086c +#define MT6392_TYPE_C_CC_DAC_CALI_CTRL 0x0870 +#define MT6392_TYPE_C_CC_DAC_CALI_RESULT 0x0872 +#define MT6392_TYPE_C_DEBUG_PORT_SELECT_0 0x0880 +#define MT6392_TYPE_C_DEBUG_PORT_SELECT_1 0x0882 +#define MT6392_TYPE_C_DEBUG_MODE_SELECT 0x0884 +#define MT6392_TYPE_C_DEBUG_OUT_READ_0 0x0888 +#define MT6392_TYPE_C_DEBUG_OUT_READ_1 0x088a +#define MT6392_TYPE_C_SW_DEBUG_PORT_0 0x088c +#define MT6392_TYPE_C_SW_DEBUG_PORT_1 0x088e + +#endif /* __MFD_MT6392_REGISTERS_H__ */ diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h index b774c3a4bb62e..d665d07770658 100644 --- a/include/linux/mfd/mt6397/core.h +++ b/include/linux/mfd/mt6397/core.h @@ -20,6 +20,7 @@ enum chip_id { MT6359_CHIP_ID = 0x59, MT6366_CHIP_ID = 0x66, MT6391_CHIP_ID = 0x91, + MT6392_CHIP_ID = 0x92, MT6397_CHIP_ID = 0x97, }; From patchwork Thu Dec 26 04:58:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13921017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3619E77188 for ; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189852; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FCtQxe3UgNrzJxC3+A7Z9vKRxu+sFJgDjgkXCte8ayo=; b=AIpwEMYNmwUWc7IACElrVCsrDkBXvGOVUA6Y/XlseKJ10jyMnKQVnOeDZ7PP8HHUKk3O7E GsQEo+oAJa2q+MAAlwM9AVAcO0VyIfGjGzw+2Q2F7PcEQkqavnrLeuLioE1KNLGuB1ZrLw c4BhT7EgRURwH9N6HoBJGbACifMOjoR05HntRCdJ5dDDWQ74qQUFsMatVra5/JInJfPy3b 6ElOZS+Xn1W3EDlt/OytZUFlOZBONyyp3dAc7a3z8xZP+QsFY6hqPEcGhnCIjm/WYhWY6O yRZaVozrIQgIRhaTnC5cGQ4ZjHy3pb9TkHvjB1apOVSPqRYo+UVsIokr2NGtkA== From: Val Packett To: Cc: Val Packett , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Fabien Parent , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 5/9] soc: mediatek: mtk-pmic-wrap: add compatible for MT6392 PMIC Date: Thu, 26 Dec 2024 01:58:05 -0300 Message-ID: <20241226050205.30241-6-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211054_485766_E6DEA240 X-CRM114-Status: UNSURE ( 8.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The MT6392 PMIC is equivalent to the MT6323 in terms of pwrap. Add the compatible to use the same configuration. Signed-off-by: Val Packett --- drivers/soc/mediatek/mtk-pmic-wrap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 9fdc0ef792026..59611ef0b144f 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -2249,6 +2249,7 @@ static const struct pwrap_slv_type pmic_mt6397 = { static const struct of_device_id of_slave_match_tbl[] = { { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, + { .compatible = "mediatek,mt6392", .data = &pmic_mt6323 }, { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, From patchwork Thu Dec 26 04:58:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13921018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8455E77188 for ; Thu, 26 Dec 2024 05:16:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XGAj8H7cKrmNfmD47jo6S3J7DaoOWvnIDq/gEQ4vakQ=; b=CATcucCi/WKhs//bNl1O+w0oEo ePhVImP3wJ08OAO2E4B7kOq5doxlJLpXHspAccIaZOklAARjl4wjCy8mq/MvcdtdVOo02/9li5Ck4 IgV9PqkIrlRMaMkKdpY+4Z5ukotMIJbDHxCDN5jvKVYGf6EIxxNwCNvnqgM/gY9M+MN+6Y5U8gBdH ulc9OElYup4SlgyBK0KNZwVtMwzxGG9DuXJ1Fm4OqtHJEDq/qY+YKUlHAjB10xigK3K6GS4rEYgMP afLBU1dizE+IEVsJLx/A4kBo3HKJhyFgv54cJkJTkLtDYv6yUgI6kMTpiCjvMUpwGdaWtwSYzfoKy KlIKutuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQgEI-0000000F9wF-3Qwo; Thu, 26 Dec 2024 05:16:14 +0000 Received: from out-186.mta0.migadu.com ([2001:41d0:1004:224b::ba]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQg9a-0000000F8V1-30hb for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:11:24 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189879; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XGAj8H7cKrmNfmD47jo6S3J7DaoOWvnIDq/gEQ4vakQ=; b=NnjBrcZ5Escmykbm2nmgbfwdW/NmcrUoO0ZA1LAHPKstacNk56qLrZ1Zs8ddA4p7TU2BFo qyVExXU7ZnWs89i+acs9jwZE/XTskkhkI7ImyK/rsw28GH6bPqLsO6XyBAhZ+cFJlSwBpw h2jmqGAhiztE8GnEvx/JNZ6HDOVIAj/nyb8YJQ/Fh84Eh/NBCV9mH7v/DRfVx0xgA1GEuG 4jQuHA3uF9X4EeMFYvxWzsjtMNTwJmpZQ7EUas0IiC6+GHeGz5LDtseqx7vhM042LYjQJM wpUYHi1zJy39cLQt6XCY+S1T7zZER+P95Anip6nABJqQ3VCRR/K59bc6OKnQbA== From: Val Packett To: Cc: Fabien Parent , Val Packett , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 6/9] regulator: mt6392: Add support for MT6392 regulator Date: Thu, 26 Dec 2024 01:58:06 -0300 Message-ID: <20241226050205.30241-7-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211123_047900_DA9F2936 X-CRM114-Status: GOOD ( 19.63 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent The MT6392 is a regulator found on boards based on the MediaTek MT8167, MT8516, and probably other SoCs. It is a so called PMIC and connects as a slave to a SoC using SPI, wrapped inside PWRAP. Signed-off-by: Fabien Parent Co-developed-by: Val Packett Signed-off-by: Val Packett --- [Val: added missing mt6392_set_buck_vosel_reg function] drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6392-regulator.c | 484 +++++++++++++++++++++ include/linux/regulator/mt6392-regulator.h | 40 ++ 4 files changed, 534 insertions(+) create mode 100644 drivers/regulator/mt6392-regulator.c create mode 100644 include/linux/regulator/mt6392-regulator.h diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 39297f7d81771..99ae2bba569fb 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -933,6 +933,15 @@ config REGULATOR_MT6380 This driver supports the control of different power rails of device through regulator interface. +config REGULATOR_MT6392 + tristate "MediaTek MT6392 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6392 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6397 tristate "MediaTek MT6397 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 3d5a803dce8a0..231b0a9b72cd2 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -111,6 +111,7 @@ obj-$(CONFIG_REGULATOR_MT6359) += mt6359-regulator.o obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o obj-$(CONFIG_REGULATOR_MT6370) += mt6370-regulator.o obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o +obj-$(CONFIG_REGULATOR_MT6392) += mt6392-regulator.o obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o obj-$(CONFIG_REGULATOR_MTK_DVFSRC) += mtk-dvfsrc-regulator.o obj-$(CONFIG_REGULATOR_QCOM_LABIBB) += qcom-labibb-regulator.o diff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt6392-regulator.c new file mode 100644 index 0000000000000..11696c4f3bfab --- /dev/null +++ b/drivers/regulator/mt6392-regulator.c @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. +// Copyright (c) 2020 BayLibre, SAS. +// Author: Chen Zhong +// Author: Fabien Parent +// +// Based on mt6397-regulator.c + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6392_BUCK_MODE_AUTO 0 +#define MT6392_BUCK_MODE_FORCE_PWM 1 +#define MT6392_LDO_MODE_NORMAL 0 +#define MT6392_LDO_MODE_LP 1 + +/* + * MT6392 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6392_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6392_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl, \ + _modeset_reg, _modeset_mask) \ +[MT6392_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6392_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6392_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .qi = BIT(13), \ + .vselon_reg = voselon, \ + .vselctrl_reg = vosel_ctrl, \ + .vselctrl_mask = BIT(1), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6392_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask, _modeset_reg, _modeset_mask) \ +[MT6392_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6392_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6392_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .qi = BIT(15), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6392_LDO_LINEAR(match, vreg, min, max, step, volt_ranges, \ + enreg, enbit, vosel, vosel_mask, _modeset_reg, \ + _modeset_mask) \ +[MT6392_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6392_volt_ldo_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6392_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .qi = BIT(15), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6392_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask) \ +[MT6392_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6392_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6392_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .qi = BIT(15), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = _modeset_mask, \ +} + +#define MT6392_REG_FIXED_NO_MODE(match, vreg, enreg, enbit, volt) \ +[MT6392_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6392_volt_fixed_no_mode_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6392_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .qi = BIT(15), \ +} + +static const struct linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500), +}; + +static const u32 ldo_volt_table1[] = { + 1800000, 1900000, 2000000, 2200000, +}; + +static const struct linear_range ldo_volt_range2[] = { + REGULATOR_LINEAR_RANGE(3300000, 0, 3, 100000), +}; + +static const u32 ldo_volt_table3[] = { + 1800000, 3300000, +}; + +static const u32 ldo_volt_table4[] = { + 3000000, 3300000, +}; + +static const u32 ldo_volt_table5[] = { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000, +}; + +static const u32 ldo_volt_table6[] = { + 1240000, 1390000, +}; + +static const u32 ldo_volt_table7[] = { + 1200000, 1300000, 1500000, 1800000, +}; + +static const u32 ldo_volt_table8[] = { + 1800000, 2000000, +}; + +static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + int ret, val = 0; + struct mt6392_regulator_info *info = rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_FAST: + val = MT6392_BUCK_MODE_FORCE_PWM; + break; + case REGULATOR_MODE_NORMAL: + val = MT6392_BUCK_MODE_AUTO; + break; + default: + return -EINVAL; + } + + val <<= ffs(info->modeset_mask) - 1; + + ret = regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &= info->modeset_mask; + val >>= ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode = REGULATOR_MODE_FAST; + else + mode = REGULATOR_MODE_NORMAL; + + return mode; +} + +static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + int ret, val = 0; + struct mt6392_regulator_info *info = rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val = MT6392_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val = MT6392_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<= ffs(info->modeset_mask) - 1; + + ret = regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &= info->modeset_mask; + val >>= ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode = REGULATOR_MODE_STANDBY; + else + mode = REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6392_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6392_buck_set_mode, + .get_mode = mt6392_buck_get_mode, +}; + +static const struct regulator_ops mt6392_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6392_ldo_set_mode, + .get_mode = mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_ldo_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6392_ldo_set_mode, + .get_mode = mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_mode = mt6392_ldo_set_mode, + .get_mode = mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_no_mode_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +}; + +/* The array is indexed by id(MT6392_ID_XXX) */ +static struct mt6392_regulator_info mt6392_regulators[] = { + MT6392_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250, + buck_volt_range1, MT6392_VPROC_CON7, MT6392_VPROC_CON9, 0x7f, + MT6392_VPROC_CON10, MT6392_VPROC_CON5, MT6392_VPROC_CON2, + 0x100), + MT6392_BUCK("buck_vsys", VSYS, 1400000, 2987500, 12500, + buck_volt_range2, MT6392_VSYS_CON7, MT6392_VSYS_CON9, 0x7f, + MT6392_VSYS_CON10, MT6392_VSYS_CON5, MT6392_VSYS_CON2, 0x100), + MT6392_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, + buck_volt_range1, MT6392_VCORE_CON7, MT6392_VCORE_CON9, 0x7f, + MT6392_VCORE_CON10, MT6392_VCORE_CON5, MT6392_VCORE_CON2, + 0x100), + MT6392_REG_FIXED("ldo_vxo22", VXO22, MT6392_ANALDO_CON1, 10, 2200000, + MT6392_ANALDO_CON1, 0x2), + MT6392_LDO("ldo_vaud22", VAUD22, ldo_volt_table1, + MT6392_ANALDO_CON2, 14, MT6392_ANALDO_CON8, 0x60, + MT6392_ANALDO_CON2, 0x2), + MT6392_REG_FIXED_NO_MODE("ldo_vcama", VCAMA, MT6392_ANALDO_CON4, 15, + 2800000), + MT6392_REG_FIXED("ldo_vaud28", VAUD28, MT6392_ANALDO_CON23, 14, 2800000, + MT6392_ANALDO_CON23, 0x2), + MT6392_REG_FIXED("ldo_vadc18", VADC18, MT6392_ANALDO_CON25, 14, 1800000, + MT6392_ANALDO_CON25, 0x2), + MT6392_LDO_LINEAR("ldo_vcn35", VCN35, 3300000, 3600000, 100000, + ldo_volt_range2, MT6392_ANALDO_CON21, 12, MT6392_ANALDO_CON16, + 0xC, MT6392_ANALDO_CON21, 0x2), + MT6392_REG_FIXED("ldo_vio28", VIO28, MT6392_DIGLDO_CON0, 14, 2800000, + MT6392_DIGLDO_CON0, 0x2), + MT6392_REG_FIXED("ldo_vusb", VUSB, MT6392_DIGLDO_CON2, 14, 3300000, + MT6392_DIGLDO_CON2, 0x2), + MT6392_LDO("ldo_vmc", VMC, ldo_volt_table3, + MT6392_DIGLDO_CON3, 12, MT6392_DIGLDO_CON24, 0x10, + MT6392_DIGLDO_CON3, 0x2), + MT6392_LDO("ldo_vmch", VMCH, ldo_volt_table4, + MT6392_DIGLDO_CON5, 14, MT6392_DIGLDO_CON26, 0x80, + MT6392_DIGLDO_CON5, 0x2), + MT6392_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table4, + MT6392_DIGLDO_CON6, 14, MT6392_DIGLDO_CON27, 0x80, + MT6392_DIGLDO_CON6, 0x2), + MT6392_LDO("ldo_vgp1", VGP1, ldo_volt_table5, + MT6392_DIGLDO_CON7, 15, MT6392_DIGLDO_CON28, 0xE0, + MT6392_DIGLDO_CON7, 0x2), + MT6392_LDO("ldo_vgp2", VGP2, ldo_volt_table5, + MT6392_DIGLDO_CON8, 15, MT6392_DIGLDO_CON29, 0xE0, + MT6392_DIGLDO_CON8, 0x2), + MT6392_REG_FIXED("ldo_vcn18", VCN18, MT6392_DIGLDO_CON11, 14, 1800000, + MT6392_DIGLDO_CON11, 0x2), + MT6392_LDO("ldo_vcamaf", VCAMAF, ldo_volt_table5, + MT6392_DIGLDO_CON31, 15, MT6392_DIGLDO_CON32, 0xE0, + MT6392_DIGLDO_CON31, 0x2), + MT6392_LDO("ldo_vm", VM, ldo_volt_table6, + MT6392_DIGLDO_CON47, 14, MT6392_DIGLDO_CON48, 0x30, + MT6392_DIGLDO_CON47, 0x2), + MT6392_REG_FIXED("ldo_vio18", VIO18, MT6392_DIGLDO_CON49, 14, 1800000, + MT6392_DIGLDO_CON49, 0x2), + MT6392_LDO("ldo_vcamd", VCAMD, ldo_volt_table7, + MT6392_DIGLDO_CON51, 14, MT6392_DIGLDO_CON52, 0x60, + MT6392_DIGLDO_CON51, 0x2), + MT6392_REG_FIXED("ldo_vcamio", VCAMIO, MT6392_DIGLDO_CON53, 14, 1800000, + MT6392_DIGLDO_CON53, 0x2), + MT6392_REG_FIXED("ldo_vm25", VM25, MT6392_DIGLDO_CON55, 14, 2500000, + MT6392_DIGLDO_CON55, 0x2), + MT6392_LDO("ldo_vefuse", VEFUSE, ldo_volt_table8, + MT6392_DIGLDO_CON57, 14, MT6392_DIGLDO_CON58, 0x10, + MT6392_DIGLDO_CON57, 0x2), +}; + +static int mt6392_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i = 0; i < MT6392_MAX_REGULATOR; i++) { + if (mt6392_regulators[i].vselctrl_reg) { + if (regmap_read(mt6392->regmap, + mt6392_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6392_regulators[i].vselctrl_mask) { + mt6392_regulators[i].desc.vsel_reg = + mt6392_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6392_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + + /* Query buck controller to select activated voltage register part */ + if (mt6392_set_buck_vosel_reg(pdev)) + return -EIO; + + for (i = 0; i < MT6392_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; + config.driver_data = &mt6392_regulators[i]; + config.regmap = mt6392->regmap; + + rdev = devm_regulator_register(&pdev->dev, + &mt6392_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6392_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6392_platform_ids[] = { + {"mt6392-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6392_platform_ids); + +static struct platform_driver mt6392_regulator_driver = { + .driver = { + .name = "mt6392-regulator", + }, + .probe = mt6392_regulator_probe, + .id_table = mt6392_platform_ids, +}; + +module_platform_driver(mt6392_regulator_driver); + +MODULE_AUTHOR("Chen Zhong "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6392 PMIC"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/regulator/mt6392-regulator.h new file mode 100644 index 0000000000000..dfcbcacb5ad43 --- /dev/null +++ b/include/linux/regulator/mt6392-regulator.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __LINUX_REGULATOR_MT6392_H +#define __LINUX_REGULATOR_MT6392_H + +enum { + MT6392_ID_VPROC = 0, + MT6392_ID_VSYS, + MT6392_ID_VCORE, + MT6392_ID_VXO22, + MT6392_ID_VAUD22, + MT6392_ID_VCAMA, + MT6392_ID_VAUD28, + MT6392_ID_VADC18, + MT6392_ID_VCN35, + MT6392_ID_VIO28, + MT6392_ID_VUSB = 10, + MT6392_ID_VMC, + MT6392_ID_VMCH, + MT6392_ID_VEMC3V3, + MT6392_ID_VGP1, + MT6392_ID_VGP2, + MT6392_ID_VCN18, + MT6392_ID_VCAMAF, + MT6392_ID_VM, + MT6392_ID_VIO18, + MT6392_ID_VCAMD, + MT6392_ID_VCAMIO, + MT6392_ID_VM25, + MT6392_ID_VEFUSE, + MT6392_ID_RG_MAX, +}; + +#define MT6392_MAX_REGULATOR MT6392_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6392_H */ From patchwork Thu Dec 26 04:58:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13921019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0EA7E77188 for ; Thu, 26 Dec 2024 05:17:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vwQ4N1e+TBjnM5P/3WcPIc4WkvpX1QuMyXV+3IuUEkA=; b=HF/UMzc/6a3/fg1lesfmcdgGnQ WiPv6QJAT52OFMGEspsIdnnxF10rMX/fW+fZW363Tt5ihqZ1tmjiH9gZeC5RN+ugLUI4053iWk3mm PuYEFUoaPdj+9ksnYIiMkTs9LzjledKnRsBFdzasGdnU9Qu9TUBdS8W6BIPbMvYinr0Nn2q0AhHj8 XoMgVYqUR6hlyc4wOSEY7/hBdqOv6rF7tt6cuphqE+uVl/LPBXvthWWtVgzJSjxfClZmQnGHAWnqL hcOfhelUgCD+I8v/i29DNBTpGZWE4+1XJE5BkxnzqNw6Brr3R3GJI9kPrdoJHS78GG47aCNhYvcsw bCPWfJ/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQgFT-0000000FAO4-3gDB; Thu, 26 Dec 2024 05:17:27 +0000 Received: from out-183.mta0.migadu.com ([91.218.175.183]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQgA1-0000000F8bl-0njM for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:11:50 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vwQ4N1e+TBjnM5P/3WcPIc4WkvpX1QuMyXV+3IuUEkA=; b=fPkCdAQ/vP86/E35KgJIAWs1gu/guAcpRuxfTWJn5tNwJ7CCcAUJ0Cbts08Bk0vsfgLbR3 z9WhpBpo2Wp2QWQP6ixhx2U4DyA2xsePwxYpVvEeS5IhOIXS6vGq0v3yTSQ96U+0NGRLKt L+TmhvpPqKoZNOa6/tr4N7PwJs8Kdi1ODdp13rZYYSMGxg8j0SYRgslr7KyeVCFEfY/dP+ 028JqnX46gNCjCjVwLn0VAoXXKVnZO2UwfEEy4DOLQbLLmZYDy7F1LDdp6AHHj/MeQfEa6 f9shY0qwbm5G0TAlQyAwU6G7+bUIdoXSZw5l4bE1azmhL4wFRyHCFpzGoD276Q== From: Val Packett To: Cc: Val Packett , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Fabien Parent , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 7/9] input: keyboard: mtk-pmic-keys: add MT6392 support Date: Thu, 26 Dec 2024 01:58:07 -0300 Message-ID: <20241226050205.30241-8-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211149_376995_A5DCD962 X-CRM114-Status: UNSURE ( 9.29 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add support for the MT6392 PMIC to the keys driver. Signed-off-by: Val Packett --- drivers/input/keyboard/mtk-pmic-keys.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c index 5ad6be9141603..94fa0f316edc6 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -67,6 +68,17 @@ static const struct mtk_pmic_regs mt6397_regs = { .rst_lprst_mask = MTK_PMIC_RST_DU_MASK, }; +static const struct mtk_pmic_regs mt6392_regs = { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6392_CHRSTATUS, + 0x2, MT6392_INT_MISC_CON, 0x10, MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6392_CHRSTATUS, + 0x4, MT6392_INT_MISC_CON, 0x8, MTK_PMIC_HOMEKEY_RST), + .pmic_rst_reg = MT6392_TOP_RST_MISC, + .rst_lprst_mask = MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6323_regs = { .keys_regs[MTK_PMIC_PWRKEY_INDEX] = MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS, @@ -284,6 +296,9 @@ static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = { { .compatible = "mediatek,mt6397-keys", .data = &mt6397_regs, + }, { + .compatible = "mediatek,mt6392-keys", + .data = &mt6392_regs, }, { .compatible = "mediatek,mt6323-keys", .data = &mt6323_regs, From patchwork Thu Dec 26 04:58:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13921020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FE24E77188 for ; Thu, 26 Dec 2024 05:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=V6NLCR17ypGViL9bUhW6xSOEVx68tYcdJbQF8eDMwQY=; b=SK6F36qvELQ3isfkmv3kNT7zXw TmQVed8OabCu8yVU0y3GWXIuRnbnnVJjlXs9oDeKpDGjAvC1xfkv6tytQX24/+LGINVy7Isy4RTO/ ZWJjWjaMtaQa3+JVHFxamyl8zZseCECOpTy33EbMUAEkAYt3tOjIC0VmUSQTsAVLBAuZLVzvV2P1O 8PS+7e9G28Wsqumrhqq7P9E6rXoJEK9rZ/Tv1YVxuh1mxgAErWGarE5vuB4Ij6MD0AmCwpRX6RqU6 2SR7bBCZv6E2zC49hkg3kvxIzz+t6DWsIg6hey2HBwCjf5NJCFoosRKtgZV/RyPU/5DEPnFilRzdW 1MPmfOeg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQgGf-0000000FAro-1ydc; Thu, 26 Dec 2024 05:18:41 +0000 Received: from out-171.mta0.migadu.com ([2001:41d0:1004:224b::ab]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQgAT-0000000F8if-2BTy for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:12:23 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189934; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=V6NLCR17ypGViL9bUhW6xSOEVx68tYcdJbQF8eDMwQY=; b=OT78zrncr4RxpM6kx5sjFnU7Q45/uRXsN8Nk0KSi0HzOuZNcEnHOzsiZumi4FPEJB4DSVv C5A6Mq30CtDBpauWXhVabQWbEK0XxqPGO2F2aCUvyy/b09mxgErtd1lPGZT4pLly3Qlseb a2mQHuB85khQBOlwyAW1H8xjo312/uPi00zMbTu2zXc4szznBZ/d3YFeXv5bwMfgd0jnxk NNzflsT8sAhofPI8H4mpmfv8TZlmwuz3QWjVZtGedKO+aqW5bljn+qYVprC5xa5j4iTBzF GSKJrYaZ0/3XNgbvdH7Sfrv1y+on2pMDVHAaBpvtlF6liRGkK7/9dDDi3fv8MQ== From: Val Packett To: Cc: Val Packett , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Fabien Parent , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 8/9] rtc: mt6397: add compatible for MT6392 PMIC Date: Thu, 26 Dec 2024 01:58:08 -0300 Message-ID: <20241226050205.30241-9-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211217_708363_628190AF X-CRM114-Status: UNSURE ( 9.31 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add a compatible, using the same data as the MT6397. Signed-off-by: Val Packett --- drivers/rtc/rtc-mt6397.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c index 152699219a2b9..6fe5bff6cf442 100644 --- a/drivers/rtc/rtc-mt6397.c +++ b/drivers/rtc/rtc-mt6397.c @@ -333,6 +333,7 @@ static const struct mtk_rtc_data mt6397_rtc_data = { static const struct of_device_id mt6397_rtc_of_match[] = { { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, + { .compatible = "mediatek,mt6392-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data }, { } }; From patchwork Thu Dec 26 04:58:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13921032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BECBE77188 for ; Thu, 26 Dec 2024 05:19:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=upNmjojrv0EXOaMqSxtSK3czavePDk/4Zz+86baEfqk=; b=XpUu+OPQxPstP63Zp6QwPsQxI0 6NJjgUdAWsxRUDT5wzUFjfO+Oazkw9DXulY9J7gK6cc6I1lUpyOgaPArB/zqcWtKmbxp6INROfAy7 yY61HvSBEkju4cM5Fo4NItF21IQ81q2fDmOhsw2uJ85W3QRkXGiP3vxAFjJpszsD3kNy+uEGKY61w BbHVo49Uzi9c8JeDFyXlywQC9AhtmBhNDf3RK+WDpjtAUMhB07lJBatT7QZ2KKesbyScMCDON3kJm sglTEiyWgXH449kQkuPzqjvia7RetjYvS3AjL3M4Yaj3egfrhTExEp1ZN8FcwwM/HgTia5+3hyyQp H/StBTfQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tQgHr-0000000FBKp-2Q9T; Thu, 26 Dec 2024 05:19:55 +0000 Received: from out-184.mta0.migadu.com ([91.218.175.184]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tQgAt-0000000F8s9-1nmQ for linux-mediatek@lists.infradead.org; Thu, 26 Dec 2024 05:12:44 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189961; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=upNmjojrv0EXOaMqSxtSK3czavePDk/4Zz+86baEfqk=; b=kM45QCbANPdqx+bNe2Sj8x0De/9ILo/3HbUYMOguKQ/xzFsOpqscGERCDU0NZrxoPpw7kC x8mZE29t7nP/CX3vVzk6qQQ0/plDHWQzSCL3niE5IqX7cMPvpZd57UXBMYg6SLOEjCgAm9 ipRuZvojOjXRc6VxAXgl/jOPKIu+yMJdgLPJFXVJbP/MorZtx5JYwl9ZwZxDtSYzfZoBJM VO/twzik51fSWUjCvavzoNjTYMXAjCeKpDNqxKIWHwfEikyiWEZtAjvDoMu+HSVKIeQixS Owu++K2g52JZpd0UqNGDwjEB6Np8phw0CpIOUg06A+LQaDAMNGS7+8cHLGCkgg== From: Val Packett To: Cc: Val Packett , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Fabien Parent , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 9/9] arm64: dts: mt6392: add mt6392 PMIC dtsi Date: Thu, 26 Dec 2024 01:58:09 -0300 Message-ID: <20241226050205.30241-10-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241225_211243_627438_B317E4FC X-CRM114-Status: GOOD ( 10.81 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add the dts to be included by all boards using the MT6392 PMIC. Signed-off-by: Val Packett --- arch/arm64/boot/dts/mediatek/mt6392.dtsi | 232 +++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6392.dtsi b/arch/arm64/boot/dts/mediatek/mt6392.dtsi new file mode 100644 index 0000000000000..a7c65dbb043c1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6392.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2024 Val Packett + */ + +#include + +&pwrap { + pmic: mt6392 { + compatible = "mediatek,mt6392"; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "mediatek,mt6392-regulator"; + + mt6392_vproc_reg: buck_vproc { + regulator-name = "buck_vproc"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vsys_reg: buck_vsys { + regulator-name = "buck_vsys"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <2987500>; + regulator-ramp-delay = <25000>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcore_reg: buck_vcore { + regulator-name = "buck_vcore"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vxo22_reg: ldo_vxo22 { + regulator-name = "ldo_vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vaud22_reg: ldo_vaud22 { + regulator-name = "ldo_vaud22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcama_reg: ldo_vcama { + regulator-name = "ldo_vcama"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vaud28_reg: ldo_vaud28 { + regulator-name = "ldo_vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vadc18_reg: ldo_vadc18 { + regulator-name = "ldo_vadc18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcn35_reg: ldo_vcn35 { + regulator-name = "ldo_vcn35"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vio28_reg: ldo_vio28 { + regulator-name = "ldo_vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vusb_reg: ldo_vusb { + regulator-name = "ldo_vusb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vmc_reg: ldo_vmc { + regulator-name = "ldo_vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-boot-on; + }; + + mt6392_vmch_reg: ldo_vmch { + regulator-name = "ldo_vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-boot-on; + }; + + mt6392_vemc3v3_reg: ldo_vemc3v3 { + regulator-name = "ldo_vemc3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-boot-on; + }; + + mt6392_vgp1_reg: ldo_vgp1 { + regulator-name = "ldo_vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vgp2_reg: ldo_vgp2 { + regulator-name = "ldo_vgp2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vcn18_reg: ldo_vcn18 { + regulator-name = "ldo_vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vcamaf_reg: ldo_vcamaf { + regulator-name = "ldo_vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vm_reg: ldo_vm { + regulator-name = "ldo_vm"; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1390000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vio18_reg: ldo_vio18 { + regulator-name = "ldo_vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcamd_reg: ldo_vcamd { + regulator-name = "ldo_vcamd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vcamio_reg: ldo_vcamio { + regulator-name = "ldo_vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vm25_reg: ldo_vm25 { + regulator-name = "ldo_vm25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vefuse_reg: ldo_vefuse { + regulator-name = "ldo_vefuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6392-rtc"; + }; + + keys { + compatible = "mediatek,mt6392-keys"; + + key-power { + linux,keycodes = ; + wakeup-source; + }; + + key-home { + linux,keycodes = ; + wakeup-source; + }; + }; + }; +};