From patchwork Fri Dec 27 16:56:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0E8FE7718F for ; Fri, 27 Dec 2024 16:59:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0D3K2ln9Lb+MNQxN4twGUjq+Zn0uEKE9IsRwsBI/jVw=; b=h+AujSwx8kafHH44kkjOiu8W9h GK66A7fikLB+Swu5Bz0G6jsdv98nQoYQTOPPxsIq8+gbS6RFlnhnUNZ1xWgLfZqzDv6E7lrx5wJEd tGx/tmMBRQQmC8P9vi49CRHTVbHj3NsmmVWrB5VOFmdu06P43n7QevAQqi3MfRXix+oDwIkE5/fAr cVRCwZalNiMjN5AXcGn37VtNbxkJSZsore2WnDLF8ONua04ysodypbjkI2v1ahVYERn1/1F0Z+RhO huIezCc/bmnKm7iCw9JeAgZiuI9UEUwhxHCf3Zlzu15S6z2Td5bl6oURxQ8DfZuLKc+pV6857ld5j dcuZ1SqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDgj-00000000f1u-19A2; Fri, 27 Dec 2024 16:59:49 +0000 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDeR-00000000eSD-11aB for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:28 +0000 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-aa69077b93fso1069401266b.0 for ; Fri, 27 Dec 2024 08:57:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318645; x=1735923445; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0D3K2ln9Lb+MNQxN4twGUjq+Zn0uEKE9IsRwsBI/jVw=; b=MyblfW0wsCkqffJ7cHahDvFKkKENtcQC0RSVMoZ0IXfCmH8pj7EQRCFoAqLD1YoFcP v4XCSnhKbL42FMqzExdFjS087kTH0NTW9svk+w97RNW3cbHhLz5rHI+rKsw+FuQZtHuD 9+d1DqwWOvi9L/Td1Yz+G90k/aTnT+JCiUwnM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318645; x=1735923445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0D3K2ln9Lb+MNQxN4twGUjq+Zn0uEKE9IsRwsBI/jVw=; b=Ha0UP+d27Q0tQ2tIdLdLp6Zdy96r7kPc/u/jkDj3TJBNVu2tkznHpnYATq5kvwOSoR g17gDWIurVGq1Fs9wU03y6yR3w2c8ETsJiRON1DGtlACbrKqODDjWnahCgCmyDVc2f/Y 3dT/GdtFqXiJ6vw8RwD5XuW47LdIaIrwcc9Ib9OTIoHm0EfdVJC19Xwd7AKTfIdaUuwf nrDCjx5HmNVym3Z5Mic9ZqSR7rbKiJxxvNIVjh6obGLYqfgRw/6aE/I6XK/0yEtkkEj1 gZO73lBDJFBLDXDQYifyMg0dqJ7LMccmseQiM6OMVPCmkn6eTSFgQYekmQmM4yG+N24z mQEg== X-Forwarded-Encrypted: i=1; AJvYcCVkgQX5UGnrevuvsxq1dW3qAUm8X+r0vUwrzdGJksnn+CG6gwkK7N3ZZjLc/4JHK62WsvMXXzHpbmlUUsPdcn9L@lists.infradead.org X-Gm-Message-State: AOJu0Yw70yZw5qS4Gf5b2rWY1gNaVryLGFcB1EGh2lDj8eCDFreu86FU zaKUlZJ8bsVWE4+KG+USr4YLftXVpzGD58HDCWoNQwwpe+gyaCXkK9GaXDwxkQA= X-Gm-Gg: ASbGncuFu6n5IVu30cb1elNmQoVNEqM01qvn/y/5q00+OM5ZiaLd4MXoiYIAbssdCgq 7B7cwKdUH/WKpDNL6vjw9KNMbl+J2pzWHM71MFCqx5iQEAFM6SUCevEE8CT6TQQQvLW/9eLFwrW qlYrNvovFqXDslfqKqbP/ZO1qEGdAGiE8b4C+M/LxOrRLqBEnn3qDcRF5VT65iWzJUc9RZhatyW a58ozG8tXRMFM7aoUQN2zFptaqfoloncKa/rnfOz6bxIFww6Nyi3PV7w6YRM+cDo/bh+Gt3yF+z RvTS9IYu3GPyLHWbQF9XKw== X-Google-Smtp-Source: AGHT+IF2wAZiZXOhSk5ioYTNrzhfdCszg+K/Yp9x5T8NwwqXN7bzl3LV9Ed9BE9UWV7Fx+sow9CFjQ== X-Received: by 2002:a17:906:c106:b0:aa6:7cae:db98 with SMTP id a640c23a62f3a-aac2d447333mr2312573666b.10.1735318645446; Fri, 27 Dec 2024 08:57:25 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:24 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 01/23] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Date: Fri, 27 Dec 2024 17:56:04 +0100 Message-ID: <20241227165719.3902388-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085727_285211_1B2807D8 X-CRM114-Status: GOOD ( 11.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's add the IMX8MM_VIDEO_PLL[_*] definitions to be consistent with the RM and avoid misunderstandings. The IMX8MM_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski --- (no changes since v6) Changes in v6: - Add 'Acked-by' tag of Krzysztof Kozlowski Changes in v5: - New include/dt-bindings/clock/imx8mm-clock.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 1f768b2eeb1a..102d8a6cdb55 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -16,7 +16,8 @@ #define IMX8MM_CLK_EXT4 7 #define IMX8MM_AUDIO_PLL1_REF_SEL 8 #define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_VIDEO_PLL_REF_SEL 10 +#define IMX8MM_VIDEO_PLL1_REF_SEL IMX8MM_VIDEO_PLL_REF_SEL #define IMX8MM_DRAM_PLL_REF_SEL 11 #define IMX8MM_GPU_PLL_REF_SEL 12 #define IMX8MM_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MM_SYS_PLL3_REF_SEL 17 #define IMX8MM_AUDIO_PLL1 18 #define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_VIDEO_PLL 20 +#define IMX8MM_VIDEO_PLL1 IMX8MM_VIDEO_PLL #define IMX8MM_DRAM_PLL 21 #define IMX8MM_GPU_PLL 22 #define IMX8MM_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MM_SYS_PLL3 27 #define IMX8MM_AUDIO_PLL1_BYPASS 28 #define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_VIDEO_PLL_BYPASS 30 +#define IMX8MM_VIDEO_PLL1_BYPASS IMX8MM_VIDEO_PLL_BYPASS #define IMX8MM_DRAM_PLL_BYPASS 31 #define IMX8MM_GPU_PLL_BYPASS 32 #define IMX8MM_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MM_SYS_PLL3_BYPASS 37 #define IMX8MM_AUDIO_PLL1_OUT 38 #define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_VIDEO_PLL_OUT 40 +#define IMX8MM_VIDEO_PLL1_OUT IMX8MM_VIDEO_PLL_OUT #define IMX8MM_DRAM_PLL_OUT 41 #define IMX8MM_GPU_PLL_OUT 42 #define IMX8MM_VPU_PLL_OUT 43 From patchwork Fri Dec 27 16:56:05 2024 Content-Type: text/plain; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:26 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 02/23] clk: imx8mm: rename video_pll1 to video_pll Date: Fri, 27 Dec 2024 17:56:05 +0100 Message-ID: <20241227165719.3902388-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085729_557251_691B4367 X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- The patch, which simply replaces video_pll1 with video_pll, highlights many warnings raised by checkpatch.pl. These are not generated by the changes made but are inherited from how the module was originally written. Fixing them would have meant "obscuring" the actual changes introduced. Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v5: - Split the patch dropping the dt-bindings changes. Changes in v4: - New drivers/clk/imx/clk-imx8mm.c | 102 +++++++++++++++++------------------ 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..8a1fc7e17ba2 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -28,7 +28,7 @@ static u32 share_count_nand; static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; @@ -42,22 +42,22 @@ static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; static const char *imx8mm_vpu_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", }; static const char *imx8mm_gpu3d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; static const char *imx8mm_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; static const char *imx8mm_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",}; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "sys_pll1_100m",}; static const char *imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; + "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; static const char *imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; @@ -72,28 +72,28 @@ static const char *imx8mm_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pl "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; static const char *imx8mm_disp_rtrm_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; + "audio_pll1_out", "video_pll_out", "clk_ext2", "clk_ext3", }; static const char *imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; static const char *imx8mm_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; static const char *imx8mm_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; static const char *imx8mm_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; static const char *imx8mm_noc_apb_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", }; static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", - "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; + "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; static const char *imx8mm_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; + "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; static const char *imx8mm_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", }; @@ -108,10 +108,10 @@ static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8 "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", }; static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", }; static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", }; static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; @@ -122,47 +122,47 @@ static const char *imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_p static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; -static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; -static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; -static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; -static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; -static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; -static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; -static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; -static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; -static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; -static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; static const char *imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", - "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; + "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", }; static const char *imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "video_pll1_out", }; + "clk_ext3", "clk_ext4", "video_pll_out", }; static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", - "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; + "sys_pll2_500m", "video_pll_out", "audio_pll2_out", }; static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", - "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", }; + "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", }; static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; @@ -174,16 +174,16 @@ static const char *imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; static const char *imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char *imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char *imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char *imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char *imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; @@ -213,19 +213,19 @@ static const char *imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; static const char *imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m", - "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; + "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -234,31 +234,31 @@ static const char *imx8mm_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_ou "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; static const char *imx8mm_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; static const char *imx8mm_csi1_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_csi1_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; static const char *imx8mm_csi2_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", }; static const char *imx8mm_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; @@ -286,9 +286,9 @@ static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", } static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", }; static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", }; + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -327,7 +327,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -336,7 +336,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MM_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll); hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); @@ -348,7 +348,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) /* PLL bypass out */ hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MM_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MM_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); @@ -358,7 +358,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) /* PLL out gate */ hws[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:29 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 03/23] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Date: Fri, 27 Dec 2024 17:56:06 +0100 Message-ID: <20241227165719.3902388-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085731_269113_FF93C05A X-CRM114-Status: GOOD ( 11.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's add the IMX8MP_VIDEO_PLL[_*] definitions to be consistent with the RM and avoid misunderstandings. The IMX8MP_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski --- (no changes since v6) Changes in v6: - Add 'Acked-by' tag of Krzysztof Kozlowski Changes in v5: - New include/dt-bindings/clock/imx8mp-clock.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 7da4243984b2..3235d7de3b62 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -16,7 +16,8 @@ #define IMX8MP_CLK_EXT4 7 #define IMX8MP_AUDIO_PLL1_REF_SEL 8 #define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +#define IMX8MP_VIDEO_PLL_REF_SEL 10 +#define IMX8MP_VIDEO_PLL1_REF_SEL IMX8MP_VIDEO_PLL_REF_SEL #define IMX8MP_DRAM_PLL_REF_SEL 11 #define IMX8MP_GPU_PLL_REF_SEL 12 #define IMX8MP_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MP_SYS_PLL3_REF_SEL 17 #define IMX8MP_AUDIO_PLL1 18 #define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 +#define IMX8MP_VIDEO_PLL 20 +#define IMX8MP_VIDEO_PLL1 IMX8MP_VIDEO_PLL #define IMX8MP_DRAM_PLL 21 #define IMX8MP_GPU_PLL 22 #define IMX8MP_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MP_SYS_PLL3 27 #define IMX8MP_AUDIO_PLL1_BYPASS 28 #define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 +#define IMX8MP_VIDEO_PLL_BYPASS 30 +#define IMX8MP_VIDEO_PLL1_BYPASS IMX8MP_VIDEO_PLL_BYPASS #define IMX8MP_DRAM_PLL_BYPASS 31 #define IMX8MP_GPU_PLL_BYPASS 32 #define IMX8MP_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MP_SYS_PLL3_BYPASS 37 #define IMX8MP_AUDIO_PLL1_OUT 38 #define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 +#define IMX8MP_VIDEO_PLL_OUT 40 +#define IMX8MP_VIDEO_PLL1_OUT IMX8MP_VIDEO_PLL_OUT #define IMX8MP_DRAM_PLL_OUT 41 #define IMX8MP_GPU_PLL_OUT 42 #define IMX8MP_VPU_PLL_OUT 43 From patchwork Fri Dec 27 16:56:07 2024 Content-Type: text/plain; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:30 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 04/23] clk: imx8mp: rename video_pll1 to video_pll Date: Fri, 27 Dec 2024 17:56:07 +0100 Message-ID: <20241227165719.3902388-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085732_571555_0945837D X-CRM114-Status: GOOD ( 11.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- The patch, which simply replaces video_pll1 with video_pll, highlights many warnings raised by checkpatch.pl. These are not generated by the changes made but are inherited from how the module was originally written. Fixing them would have meant "obscuring" the actual changes introduced. Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v5: - Split the patch dropping the dt-bindings changes. Changes in v4: - New drivers/clk/imx/clk-imx8mp.c | 118 +++++++++++++++++------------------ 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..e96460534e7d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -23,7 +23,7 @@ static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; @@ -40,27 +40,27 @@ static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out" static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; static const char * const imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", @@ -72,11 +72,11 @@ static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m" static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -96,35 +96,35 @@ static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", static const char * const imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", @@ -159,56 +159,56 @@ static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_200m", }; static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; static const char * const imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; static const char * const imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; static const char * const imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -223,19 +223,19 @@ static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", @@ -276,42 +276,42 @@ static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; static const char * const imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; static const char * const imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; static const char * const imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; static const char * const imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; static const char * const imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; static const char * const imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", @@ -328,19 +328,19 @@ static const char * const imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800 static const char * const imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k" }; + "video_pll_out", "osc_32k" }; static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; static const char * const imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -349,26 +349,26 @@ static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s static const char * const imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; -static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", +static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -392,12 +392,12 @@ static const char * const imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll3_out", "audio_pll1_out", }; static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; -static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", +static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -440,7 +440,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -451,7 +451,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll); hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll); + hws[IMX8MP_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", anatop_base + 0x28, &imx_1443x_pll); hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll); hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll); @@ -462,7 +462,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MP_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); @@ -473,7 +473,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13); hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13); - hws[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13); + hws[IMX8MP_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", anatop_base + 0x28, 13); hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13); hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11); hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11); From patchwork Fri Dec 27 16:56:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6CBEE7718B for ; Fri, 27 Dec 2024 17:04:44 +0000 (UTC) DKIM-Signature: v=1; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:32 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 05/23] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Date: Fri, 27 Dec 2024 17:56:08 +0100 Message-ID: <20241227165719.3902388-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085734_517902_6FBAA402 X-CRM114-Status: GOOD ( 13.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Though adding clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the anatop module uses the input oscillators to generate various PLLs. In turn, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Furthermore, as agreed in [1], this change represents the first step toward the implementation of the anatop driver. Currently, in fact, there is no dedicated anatop driver, but the CCM driver parses the anatop node and registers the PLLs it produces. [1] https://lore.kernel.org/imx/20241106090549.3684963-1-dario.binacchi@amarulasolutions.com/ Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - Improve commit message - Merge it with patch 10, 11, and 12: - 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop - 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop - 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop Changes in v4: - New .../bindings/clock/fsl,imx8m-anatop.yaml | 53 ++++++++++++++- include/dt-bindings/clock/imx8mm-clock.h | 64 +++++++++++++++++ include/dt-bindings/clock/imx8mn-clock.h | 64 +++++++++++++++++ include/dt-bindings/clock/imx8mp-clock.h | 68 +++++++++++++++++++ 4 files changed, 248 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..f439b0a94ce2 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -30,22 +30,73 @@ properties: interrupts: maxItems: 1 + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + '#clock-cells': const: 1 required: - compatible - reg + - clocks + - clock-names - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-anatop + then: + properties: + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: osc_32k + - const: osc_24m + additionalProperties: false examples: - | - anatop: clock-controller@30360000 { + clock-controller@30360000 { compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>; + clock-names = "osc_32k", "osc_24m"; + }; + + - | + clock-controller@30360000 { + compatible = "fsl,imx8mq-anatop"; + reg = <0x30360000 0x10000>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names = "ckil", "osc_25m", "osc_27m"; }; ... diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 102d8a6cdb55..017c06e48430 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -287,4 +287,68 @@ #define IMX8MM_CLK_END 258 +#define IMX8MM_ANATOP_CLK_DUMMY 0 +#define IMX8MM_ANATOP_CLK_32K 1 +#define IMX8MM_ANATOP_CLK_24M 2 +#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MM_ANATOP_AUDIO_PLL1 11 +#define IMX8MM_ANATOP_AUDIO_PLL2 12 +#define IMX8MM_ANATOP_VIDEO_PLL 13 +#define IMX8MM_ANATOP_DRAM_PLL 14 +#define IMX8MM_ANATOP_GPU_PLL 15 +#define IMX8MM_ANATOP_VPU_PLL 16 +#define IMX8MM_ANATOP_ARM_PLL 17 +#define IMX8MM_ANATOP_SYS_PLL1 18 +#define IMX8MM_ANATOP_SYS_PLL2 19 +#define IMX8MM_ANATOP_SYS_PLL3 20 +#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26 +#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MM_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MM_ANATOP_GPU_PLL_OUT 33 +#define IMX8MM_ANATOP_VPU_PLL_OUT 34 +#define IMX8MM_ANATOP_ARM_PLL_OUT 35 +#define IMX8MM_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MM_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MM_ANATOP_SYS_PLL1_40M 38 +#define IMX8MM_ANATOP_SYS_PLL1_80M 39 +#define IMX8MM_ANATOP_SYS_PLL1_100M 40 +#define IMX8MM_ANATOP_SYS_PLL1_133M 41 +#define IMX8MM_ANATOP_SYS_PLL1_160M 42 +#define IMX8MM_ANATOP_SYS_PLL1_200M 43 +#define IMX8MM_ANATOP_SYS_PLL1_266M 44 +#define IMX8MM_ANATOP_SYS_PLL1_400M 45 +#define IMX8MM_ANATOP_SYS_PLL1_800M 46 +#define IMX8MM_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MM_ANATOP_SYS_PLL2_50M 48 +#define IMX8MM_ANATOP_SYS_PLL2_100M 49 +#define IMX8MM_ANATOP_SYS_PLL2_125M 50 +#define IMX8MM_ANATOP_SYS_PLL2_166M 51 +#define IMX8MM_ANATOP_SYS_PLL2_200M 52 +#define IMX8MM_ANATOP_SYS_PLL2_250M 53 +#define IMX8MM_ANATOP_SYS_PLL2_333M 54 +#define IMX8MM_ANATOP_SYS_PLL2_500M 55 +#define IMX8MM_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MM_ANATOP_CLK_CLKOUT1 59 +#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MM_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 04809edab33c..b2fa73803d45 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -267,4 +267,68 @@ #define IMX8MN_CLK_END 235 +#define IMX8MN_ANATOP_CLK_DUMMY 0 +#define IMX8MN_ANATOP_CLK_32K 1 +#define IMX8MN_ANATOP_CLK_24M 2 +#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8 +#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MN_ANATOP_AUDIO_PLL1 11 +#define IMX8MN_ANATOP_AUDIO_PLL2 12 +#define IMX8MN_ANATOP_VIDEO_PLL 13 +#define IMX8MN_ANATOP_DRAM_PLL 14 +#define IMX8MN_ANATOP_GPU_PLL 15 +#define IMX8MN_ANATOP_M7_ALT_PLL 16 +#define IMX8MN_ANATOP_ARM_PLL 17 +#define IMX8MN_ANATOP_SYS_PLL1 18 +#define IMX8MN_ANATOP_SYS_PLL2 19 +#define IMX8MN_ANATOP_SYS_PLL3 20 +#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26 +#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MN_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MN_ANATOP_GPU_PLL_OUT 33 +#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34 +#define IMX8MN_ANATOP_ARM_PLL_OUT 35 +#define IMX8MN_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MN_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MN_ANATOP_SYS_PLL1_40M 38 +#define IMX8MN_ANATOP_SYS_PLL1_80M 39 +#define IMX8MN_ANATOP_SYS_PLL1_100M 40 +#define IMX8MN_ANATOP_SYS_PLL1_133M 41 +#define IMX8MN_ANATOP_SYS_PLL1_160M 42 +#define IMX8MN_ANATOP_SYS_PLL1_200M 43 +#define IMX8MN_ANATOP_SYS_PLL1_266M 44 +#define IMX8MN_ANATOP_SYS_PLL1_400M 45 +#define IMX8MN_ANATOP_SYS_PLL1_800M 46 +#define IMX8MN_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MN_ANATOP_SYS_PLL2_50M 48 +#define IMX8MN_ANATOP_SYS_PLL2_100M 49 +#define IMX8MN_ANATOP_SYS_PLL2_125M 50 +#define IMX8MN_ANATOP_SYS_PLL2_166M 51 +#define IMX8MN_ANATOP_SYS_PLL2_200M 52 +#define IMX8MN_ANATOP_SYS_PLL2_250M 53 +#define IMX8MN_ANATOP_SYS_PLL2_333M 54 +#define IMX8MN_ANATOP_SYS_PLL2_500M 55 +#define IMX8MN_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MN_ANATOP_CLK_CLKOUT1 59 +#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MN_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3235d7de3b62..8c076225fd9e 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -402,4 +402,72 @@ #define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_ANATOP_CLK_DUMMY 0 +#define IMX8MP_ANATOP_CLK_24M 1 +#define IMX8MP_ANATOP_CLK_32K 2 +#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10 +#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11 +#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12 +#define IMX8MP_ANATOP_AUDIO_PLL1 13 +#define IMX8MP_ANATOP_AUDIO_PLL2 14 +#define IMX8MP_ANATOP_VIDEO_PLL 15 +#define IMX8MP_ANATOP_DRAM_PLL 16 +#define IMX8MP_ANATOP_GPU_PLL 17 +#define IMX8MP_ANATOP_VPU_PLL 18 +#define IMX8MP_ANATOP_ARM_PLL 19 +#define IMX8MP_ANATOP_SYS_PLL1 20 +#define IMX8MP_ANATOP_SYS_PLL2 21 +#define IMX8MP_ANATOP_SYS_PLL3 22 +#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23 +#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24 +#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25 +#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26 +#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27 +#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28 +#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29 +#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30 +#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31 +#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32 +#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33 +#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34 +#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35 +#define IMX8MP_ANATOP_DRAM_PLL_OUT 36 +#define IMX8MP_ANATOP_GPU_PLL_OUT 37 +#define IMX8MP_ANATOP_VPU_PLL_OUT 38 +#define IMX8MP_ANATOP_ARM_PLL_OUT 39 +#define IMX8MP_ANATOP_SYS_PLL3_OUT 40 +#define IMX8MP_ANATOP_SYS_PLL1_OUT 41 +#define IMX8MP_ANATOP_SYS_PLL1_40M 42 +#define IMX8MP_ANATOP_SYS_PLL1_80M 43 +#define IMX8MP_ANATOP_SYS_PLL1_100M 44 +#define IMX8MP_ANATOP_SYS_PLL1_133M 45 +#define IMX8MP_ANATOP_SYS_PLL1_160M 46 +#define IMX8MP_ANATOP_SYS_PLL1_200M 47 +#define IMX8MP_ANATOP_SYS_PLL1_266M 48 +#define IMX8MP_ANATOP_SYS_PLL1_400M 49 +#define IMX8MP_ANATOP_SYS_PLL1_800M 50 +#define IMX8MP_ANATOP_SYS_PLL2_OUT 51 +#define IMX8MP_ANATOP_SYS_PLL2_50M 52 +#define IMX8MP_ANATOP_SYS_PLL2_100M 53 +#define IMX8MP_ANATOP_SYS_PLL2_125M 54 +#define IMX8MP_ANATOP_SYS_PLL2_166M 55 +#define IMX8MP_ANATOP_SYS_PLL2_200M 56 +#define IMX8MP_ANATOP_SYS_PLL2_250M 57 +#define IMX8MP_ANATOP_SYS_PLL2_333M 58 +#define IMX8MP_ANATOP_SYS_PLL2_500M 59 +#define IMX8MP_ANATOP_SYS_PLL2_1000M 60 +#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61 +#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62 +#define IMX8MP_ANATOP_CLK_CLKOUT1 63 +#define IMX8MP_ANATOP_CLK_CLKOUT2_SEL 64 +#define IMX8MP_ANATOP_CLK_CLKOUT2_DIV 65 +#define IMX8MP_ANATOP_CLK_CLKOUT2 66 + #endif From patchwork Fri Dec 27 16:56:09 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:33 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 06/23] arm64: dts: imx8mm: add anatop clocks Date: Fri, 27 Dec 2024 17:56:09 +0100 Message-ID: <20241227165719.3902388-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085735_606102_947BCEB0 X-CRM114-Status: UNSURE ( 9.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add clocks to anatop node. Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 4de3bf22902b..597041a05073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -600,6 +600,8 @@ anatop: clock-controller@30360000 { compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>; + clock-names = "osc_32k", "osc_24m"; }; snvs: snvs@30370000 { From patchwork Fri Dec 27 16:56:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85F96E7718B for ; Fri, 27 Dec 2024 17:07:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=Q0kT23imNUcxWTKc1HgPIOq2O/ H5r/wG6KsmBumPdrwO+xAVwivT8gIe20J4g95Rp+g2daYmNsQcUbuf9dvbA4R3lMYW1pv0ld3ehW3 M+q/TxiT0ZWZgEhxfGM1awDyJQ0IzMQH8VTMv6qupY8uzvDgMYU2XMUa0UBsHfwV2ESnmhEwtjOho KpCnUc32PAVgT6G1qRlRG7D9pxI2v2JHmOvyOtYmJ/qW5S/DfAcIlAulIfWBVI7HZDTgEC6zQgZo2 wW7O3GjTl16AgxTqdHI9wAZ9HLxH7Y69/SdoUOV9snXUFmBo6tRTn/ihUXoyfJ+qGlBlWV+VBtAzY fScsarHQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDnZ-00000000gIf-0ti1; Fri, 27 Dec 2024 17:06:53 +0000 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDea-00000000eUP-3ZEh for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:38 +0000 Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-aa6997f33e4so1263913766b.3 for ; Fri, 27 Dec 2024 08:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318655; x=1735923455; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=UTJiQ5/tEqYNoboy5YYe+EoJEOKw8j8aZIYr8XMjJR26vV3MDRsmaQT6+bMZji5Pc3 drUugYLz+2ulm55/zY2+fHW1LYT5BBRiNIbHDLZpKSKE/jJECWlna9XT+qkVT0uqc93t OIl2iUrF48Wzw0EsG5JuqO0XWnhLZWTIEACvs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318655; x=1735923455; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=UQJyIe7TQO5kdXy3CxKegGX99mx4RLh1v3WiRsWBXIgZef3fppiQtcdRcBhA4hnPKN XJs7cUuuHmwCBo/gyU2Cny30UaaKrSnDHYGj9gGsDsUBsNP/8EfVuKyCVfAwPlt5Jo93 i39F2mj49sLWcx1ytkk0rI7PpH8XWtbiwccz2sKErR65mjihClzPVihTLMEJSBuVD5QZ AV6+egFWSARteoFJt7rhqNmlETJ04n4dnCMfImc4M+l6Hc7cb8zmN++5aTfe5+DMLPd1 C5rN3J472VrqVOH5cmoR9GeaCRlorWV3OwmPxWq8AnDUBHrO2GOZDxg74TGqL08Fpjba t0Lg== X-Forwarded-Encrypted: i=1; AJvYcCX/O19Hfmr6b6roCCoVmBoUvgzjnghTTcJU57k9UTm+Hp0sOK8oCK8+ZN8nZHjEHd3KdeEEDRZEwJplTivv+q1x@lists.infradead.org X-Gm-Message-State: AOJu0YzYUvXYKdhleOYkLFq/Wy+PqbxzdpDwGvPWTj9wETwZY/Qr9EHL ibMohBIRQ6sB9VQ/2l8mAJ1MBj+cx2YCvT6IV9GWVY7/6ZYNzDqC8/OqzWjGrjQ= X-Gm-Gg: ASbGnctD6RH3WjXnDSEcLd9UTFT03o4hfDfPr5Of4fhiW3OqcniR2vm+Fg87iYNaBst iDiwBgkDaod1C06Jd4M1ZKlOscHYnNrfhxQXdo1az6kNL/efiCjsw1npUOgpkx4czQIEJ6FTvQc FcSEkPyqUNe1lEjoju/heO/eFAeEthyRPqLtP/cnZTMPtmknhKxz713fxD0xe3v4QDm2XmNrakb AAMQnxfLNlY7aRTtTXVod74Qxo5VhvEYlDdMGnfB2NDgAR9Urr/nCPGEadCcSlSr1rKq4e/arKH 94uj8/ESiuEVSJYPx1rpMQ== X-Google-Smtp-Source: AGHT+IE0OOORdYEPfw3l5TavUkTwemsNNoEqAVu6kBH4Ag8emI9J3IoeOvq1nphdPOb5Rod0D0CmkQ== X-Received: by 2002:a17:907:d9f:b0:aac:619:7ed8 with SMTP id a640c23a62f3a-aac28748b30mr2647750766b.7.1735318655550; Fri, 27 Dec 2024 08:57:35 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:35 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 07/23] arm64: dts: imx8mn: add anatop clocks Date: Fri, 27 Dec 2024 17:56:10 +0100 Message-ID: <20241227165719.3902388-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085736_883126_FC01661B X-CRM114-Status: UNSURE ( 8.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a5f9cfb46e5d..49be492b5687 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -606,6 +606,8 @@ anatop: clock-controller@30360000 { compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>; + clock-names = "osc_32k", "osc_24m"; }; snvs: snvs@30370000 { From patchwork Fri Dec 27 16:56:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30F95E7718B for ; Fri, 27 Dec 2024 17:08:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=gRga5FEsM2ptDWbajZC4c3U6Jo WCiGVeIZb0Hf3ZwXja9FE2sgbL2xxXTraK2InGtzMJV3/lyC5eeNIZwMwotsMAE7FkLc+pEiH+O5a IjsM8wdokn7b7k/RNJnOjXgu0LMJD7ESKvdM5g4n9qe6S7GIVWUtX22VfWdpSBWN8h/d8/E//7Gb0 IZ012nb0vincAvwBSwaWl7BD34hMmmqgIvETxxv0TotDNLZc8aRjva7Mf3zfW70cY3omZDV8n4D7p Q8knUb3JQdoVbM1E0cOCaEpWsVBfvnR9ckNaEP40y/6h9msTxVOA5KFqLNgTYkmymt9emE9PhjPz1 EKdJz2qw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDoh-00000000gS4-3pbD; Fri, 27 Dec 2024 17:08:03 +0000 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDec-00000000eUw-1Rad for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:39 +0000 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-aa689a37dd4so1083966566b.3 for ; Fri, 27 Dec 2024 08:57:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318657; x=1735923457; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=NNvwJcbvsdsW1vAyRB0yezCvAebkJCU4a5dQcRsORkz1/i+MeEGwAu9W/xFZ9V8clV 9nSGw6+y8rtWhcBHFEAT9pKeiC5xPRzC3MaVk+QBx/MZMCy5JtInbz1e2Vsbtp+7oUnf 1KsaivocS9Bph87uFsyGm4rKcKVpAl2NQ+/XE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318657; x=1735923457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=fo0uj2Zp0ZRIH0yl8MFlWVhrKTHvmyZh/y5b8x0UeXyP6Kh3oeXL4gr63p0r/bxplt imGTPBLZqTm0yVoEkSN5wJLT4buO3niyk4YnNY2N/aZdvK1sDOZxH/JYsEFVULW5qw3v tSYT0sHAi3wmLVhzQseI2i0yYcLPNPJseRf3krRmkv0/EciyClQdnLYfNdrynVm1em5/ pvwtX1rTv3B9vOjhazTbKN5uCP7yUg3qfepHBntC3YYMNp6986Dy22byu5W7tv4LzNJa L/QHRtJoEFUYP3u3JWJ9P7ToCkxrMULRL3qSJQXFfKmi8FAx+IBh8aw5RKvbyTz5eiKt nhJw== X-Forwarded-Encrypted: i=1; AJvYcCXuOSDLBVV+5r31PZzfXyLwA5ZEhy+f6eUzpdGSJv3GCv6sw0ED0ogIwNXj6cuTQVg6hPBrIqpihQdrxsiFKChX@lists.infradead.org X-Gm-Message-State: AOJu0Yyq7ksC1DzuZBfo4gSleuezgHEbC6us9nRlGSeV0ptO7X40McyH mLhPOlAy9ccYPFEgvPpNAjJn7lCcf0dSUt0/MfysFPkERyz/TffPVgBFq1+ew70= X-Gm-Gg: ASbGnctWODGgLte1VrUpoF0IcN3vY+M+OKKILvOELeD3EacboQ97i7+841C0I+cYK20 oNK1AGAgnPVdnsEMSgDKEk5UM1EEyXIj6TekKxdQ8JBTO8briCpQ0fHt1ob20s0Pl6topPnePhe ftyBGsjHZseZ2ksn4pYh1qnza+LMPiXjHsCz2B2tsjoLZt1mXhZ66+MgQcCxn0JH6Kss+/b0Usy X7lKzSh2dOERDg0ZhrmilzUj5xWCCdgfb4ksOvj0i22pAs4P4eLOfowQs3l/TNUmfeWJmAFmOIq YpNFOI5BgXrEL0I1u6fJZQ== X-Google-Smtp-Source: AGHT+IHqEpKvPrvAcl6AfnqPR2zMpwbkTUBZZsaRlEKFV18gzQEhapMBi6kOkudHyHxl8CuL5KGNTg== X-Received: by 2002:a17:907:7f92:b0:aa6:a87e:f2e1 with SMTP id a640c23a62f3a-aac3378ef88mr2400967166b.56.1735318656917; Fri, 27 Dec 2024 08:57:36 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:36 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 08/23] arm64: dts: imx8mp: add anatop clocks Date: Fri, 27 Dec 2024 17:56:11 +0100 Message-ID: <20241227165719.3902388-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085738_382925_CB45AA2F X-CRM114-Status: UNSURE ( 8.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e0d3b8cba221..0b928e173f29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -709,6 +709,8 @@ anatop: clock-controller@30360000 { compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>; + clock-names = "osc_32k", "osc_24m"; }; snvs: snvs@30370000 { From patchwork Fri Dec 27 16:56:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DD03E7718B for ; Fri, 27 Dec 2024 17:09:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=O46mVrhUbkwMk9E3tK7w8tfG5y sacrOCFWdjLgUgjz+kRVG/KRwLpMOSRD/7MJENBn2Sh4P2tSbo0Ldp4898hg8QI8geowkV+nZvtHs YF4pk8t5ePXR76B2R627yhZpWEVvyMIYGQk4HM/oPse4NuU8ppBE4aSLZzLQA5jjgVUx+K5E1XwcU NibHW6Ps6sU7eSrmmnfVOAOqhsVQeeZlgEIjd933ScVHTB9zseO34ylc/uhvjymwyiS18xhoByuKl u8OBTNW38KX/vXi9EW/SqqFm85fW51bQ7lupmUy7O5VQJ2LosEqI4joreFD2n2o8gtMGrnqhzmRyD cHPFTPNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDpq-00000000gaI-2WBP; Fri, 27 Dec 2024 17:09:14 +0000 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDed-00000000eVZ-399Y for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:40 +0000 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-5d3cf094768so11803491a12.0 for ; Fri, 27 Dec 2024 08:57:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318658; x=1735923458; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=kZvH+mjq3yDnJs+163Bj0Q9oP+4rdDLp0jLmBqKgW/8v7hY+M/CNwN0laj0xgcrL1s KACmo6KEOY/pXF9V+zj/IhVM2E2wSxtHpd0vCYDb9TtKqyxZxavPT5xV+NpriijFTSTB +zaj+cCTb230pRCkBsTToH0gac14KQImAFInU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318658; x=1735923458; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=byr4f7iG66a5HD+jyKdYP56iZr+2CWa7W8IfP1CV6S1ibszbkBjXWTpHv0kUAYtaiM p0MrmOU/+GugMyfnqOmIu03jmQaFNUsIQYjAZRTqPrpdEC01I5+Jt90/M2XNs1yfMZqh 1xnAYB2mQtQOYJwb8Q9Q0aLgyuAG4DjDcXFZ+n7Pttp1MQeip1jsRZCPxywQMPeJ+bX0 ZycObhLFRF5hk6W4wVboAbzRHPILxUiWLZZjEgqvDjJPBub6BWiO1tsYeNdlkAGjvGCK xygFKVS+Zlf576OiXRnfvNzV7MgaS0rWy/PQ2tSgfP6s60Ya83SXXX9hiqsI01PSlgvN OjDw== X-Forwarded-Encrypted: i=1; AJvYcCVeY9pVuX7Wu3iskdqODoUokoz32TLvqbQNyEFrYnTzKKvcn+UZMOAAtNbkurx+wuPMVeuIDdLeQCnxvyaUeE+8@lists.infradead.org X-Gm-Message-State: AOJu0Yy97Tdbab2/Oj27+ccLsXnLRc4Qb7pAGIPQ5zpOa5tOGocQPfOu sgMUTfhXpMEvaPHLsxlfQwfWhADuFlyZUolXhxtAwyPC++4N6z2vwqfKvnDyxFI= X-Gm-Gg: ASbGnctHJQTUjTkST4T08mLti7cZMwhws3ebmlSeqsQh6ZB8gNpd1+VAaVjuOcBE3tG Uj7LtR8hm2v9OLf1H21MCo1qtzBxnYGeOIQd1fho5sgolbVfmNSDYOaqHUsCJFDTcCMLIv4khpT IdHZfWoijPVhWLWQK0nVQyBKe9QGW30T5+vVYMPWxyJ7CtOR1epJR0zh9vPHybMjhyZ5XOG712r pZVFXBbCceL0YCf0/VlMX4joxlssFf0KUsS+HbH948Ju3ce1z0dE6hh2gFjEBZJWvBioQC/ndna kmPCoXikEhoW176Mo7+GAg== X-Google-Smtp-Source: AGHT+IEU39RTa9ECIPzQT71oAG8YXlNy7WaA4azCq4x0ZK+7kYxrqzuYsejzC7Lx7FeHEAwhQoFPPA== X-Received: by 2002:a05:6402:1ed3:b0:5d2:73b0:81ef with SMTP id 4fb4d7f45d1cf-5d81ddfdb67mr28928804a12.22.1735318658268; Fri, 27 Dec 2024 08:57:38 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:37 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 09/23] arm64: dts: imx8mq: add anatop clocks Date: Fri, 27 Dec 2024 17:56:12 +0100 Message-ID: <20241227165719.3902388-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085739_781326_528EFB37 X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d51de8d899b2..1d1424a136f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -817,6 +817,8 @@ anatop: clock-controller@30360000 { reg = <0x30360000 0x10000>; interrupts = ; #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names = "ckil", "osc_25m", "osc_27m"; }; snvs: snvs@30370000 { From patchwork Fri Dec 27 16:56:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0776DE7718B for ; Fri, 27 Dec 2024 17:10:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=EXkTXrVS+/nRJltLKdRuy9fqF8vJTsINCmAjWzhQ/Xw=; b=dPkN4Cw+rlSSCF5fdp50qqWh54 oRsvsDy/fqkq3ZiME0D4Cmpbno0g63lIV8BkTFzyCSUF2wIIbJqsvAdNMYR3yOG/kGObXkVIIZ26b mXd6Vlr3taXsVgNCJAouYmeb62eo5r/QUGoIcWUY7wiExeC9l9J9hynA9tfOBPij+fy7YtxkJiv4t 69UTkPjsyNNcMMVvRdVub+asHM3T9t9Pd5dYIrsxhelWOlz747s+AB/CFIQp/Ff21NY2RMlgEp4ND zu9JOJQljA4OKkTsOz5Od9/RneRsjDCVc24hgcGv0dJi+abjHtDIawKaGtaSEVc0r8YcLAvQSS90C +Gn892XA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDqy-00000000gg5-1OSZ; Fri, 27 Dec 2024 17:10:24 +0000 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDef-00000000eVy-2MvB for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:42 +0000 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-aaec111762bso914468666b.2 for ; Fri, 27 Dec 2024 08:57:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318660; x=1735923460; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EXkTXrVS+/nRJltLKdRuy9fqF8vJTsINCmAjWzhQ/Xw=; b=dTesJtmdH6O6ooNs9+0YO++RzVFb79FnNBgJJ03ShHkb2uGPVAvbBypMBes6rfz7IH QgbiHEhaMPz2ANmRt8HqIWwZdv8qdaMXeR3BZiul4FsF42KEbqwjbU7t34HKZzLksUGZ 3waciBCsGJfzlD8FhGEXXGLUPFQpFctfMFB+s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318660; x=1735923460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EXkTXrVS+/nRJltLKdRuy9fqF8vJTsINCmAjWzhQ/Xw=; b=MxfCZgEve8SaAAjASbwtQYEabaNh8z3Hx1Oez0UtigVqVWKApkE9iytPyUOqvVsoDj MTBNGN4DkyJeBcXoxlo5bkkh+AL3Mlxv4fFbgnZjKuk3eU7gbtkcbcgmDROTxECjqvEQ rNxiil82/m5pmDhFFw/X16Ofe8BO8Ubbrm8PjmbNmZIjwtE2L9W7TdlvtXWd/HcBj+s9 d8EpsMMbfUvX4HZt87KdSGF+JV+3kzleok552emdkpCO3+DFJ/OwFolSZ0wbVjXwRtmn s5m+Ehlq/P5WPRLwoosTQo68PXn4MYGpBuPAYuEItWKZxkXNdVFqShGd9ktp8/9IQIYr x4qQ== X-Forwarded-Encrypted: i=1; AJvYcCUeGTcBGm1UvT3G88HrWaKbvxMEL66/Zm1ks5/2RBJmNt5UxYLZt1nsLVhpxTYmHUnLp0XSxHaMxTSYOxtLw76p@lists.infradead.org X-Gm-Message-State: AOJu0Yzc2zgKipcMgHbxh2Cn87Su0CXUdUlqcH+oaTQjuY4JwjApv6XK N+SLBIypUB5Lw/Y3NyIwFSQn8eyKvn6GT/6BwtojL0H44kO3IMpv5rOo/TminK0= X-Gm-Gg: ASbGncv0H7CBYgpj0jyzJH/l8Kh7jOPgGSSahYrtl/keoIp5n/XUnAEBpXnVWmRZCBh QURM8G+jxw/u1UbSw4HH9kLELnhWULD1NXt7G7ew8MGWrUsw4xMqnEzENrSdsuklVHY0WyJEV4Z aAMQdJBh1gbhZ0FmXD3SeKFbhLdZbP2ELW1ghUDZ7gKcYeUDMzZeGs71ssLUzjX8GGqVut1RhKh 9sVX/ruIRwzJIN+0Q1bT4QpyC0cySQWZWhtg1QV7b9IlIlojhZ9J6FeBQwIZL6ZmDHd0nNPchxD DCS9B4Y4A62nDhFday99KA== X-Google-Smtp-Source: AGHT+IGCaJDO5HxA1JrQ3trYq1mZgAVJbVh/QmApzDwyIdyVJeYbHjoW+NICkcizlG/u5obfXBOTOg== X-Received: by 2002:a17:907:3d86:b0:aa6:9eac:4b7e with SMTP id a640c23a62f3a-aac2d455458mr2795714566b.30.1735318659824; Fri, 27 Dec 2024 08:57:39 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:39 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 10/23] dt-bindings: clock: imx8m-clock: add phandle to the anatop Date: Fri, 27 Dec 2024 17:56:13 +0100 Message-ID: <20241227165719.3902388-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085741_603469_20A228F8 X-CRM114-Status: GOOD ( 13.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding the phandle to the anatop node will break the ABI but will allow for a better description of the clock generation hardware, making the dependency of CCM on anatop explicit. Indeed, the CCM receives the PLLs generated by anatop as inputs, which, together with the oscillators, are used to generate the clocks for the on-chip peripherals. By doing this, it will also be possible to generalize the CCM driver code, which will no longer require the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New .../devicetree/bindings/clock/imx8m-clock.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a81478..b23e639e6389 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -43,12 +43,20 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h for the full list of i.MX8M clock IDs. + fsl,anatop: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the anatop module that outputs the PLLs, which, + along with the oscillators, are used to generate the clocks for + the on-chip peripherals. + required: - compatible - reg - clocks - clock-names - '#clock-cells' + - fsl,anatop allOf: - if: @@ -109,6 +117,7 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop = <&anatop>; }; - | @@ -120,6 +129,7 @@ examples: <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop = <&anatop>; }; ... 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:41 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 11/23] arm64: dts: imx8mm: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:14 +0100 Message-ID: <20241227165719.3902388-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085744_536255_4991ABB6 X-CRM114-Status: GOOD ( 10.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 597041a05073..b1a4cc521bf4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -645,6 +645,7 @@ clk: clock-controller@30380000 { <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, <&clk IMX8MM_CLK_A53_CORE>, <&clk IMX8MM_CLK_NOC>, From patchwork Fri Dec 27 16:56:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDE21E7718B for ; Fri, 27 Dec 2024 17:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=S3H13EAbQnYh5KL130M+yAXwGl0WzQAYvdh+BFvfpuk=; b=d5JvQooZo1Ev+vUSkueHWtgx9w 3xCB5zD6qw9Vl8tSyewTWBXHiNDdhzzespiwairQaEiNblqiIAj/0gdfAvz7TXwUOnKlsrcIAgqws 9qfVbVh74i0xqMlXAPBQeEPEVb9Djm6r/1PybimRiQph+P0qdxJuO/M85NAYou0W9r5TIyUq1oiqc VWNx0fSrpX92GYjNdL0Ticfzo2/kCKt9k94lGlWNW0P+Ca3fSHwapKbYZ3HxNih8QJ+AM3UGcJHff i+VlF3abh4bzIeH9l33AzsY682ooeL4yl5kKH2Xm2oXP86Z//Veb3NqgGvxP535hHsCRbMK09RJmO ogh7WvmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDtE-00000000grO-2pBT; Fri, 27 Dec 2024 17:12:44 +0000 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDej-00000000eY7-3XHN for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:46 +0000 Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-aaeec07b705so497663266b.2 for ; Fri, 27 Dec 2024 08:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318664; x=1735923464; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S3H13EAbQnYh5KL130M+yAXwGl0WzQAYvdh+BFvfpuk=; b=HZn/pcuPKoXoNZibncYqmSfQufCSl1kT94cfX23rcahVgAjBicJGes1wcBx+bJyw7w Pyv9AgEpH/Xd6+OMqXTxAsPf7MpIYjB+oGEEZMRVVxxFgBTESl6WP1ZZSwyBWnHdTDyf pcFcRyWSpfut5nRCdZ1AKQuhe0O0fL5Ylx68E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318664; x=1735923464; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S3H13EAbQnYh5KL130M+yAXwGl0WzQAYvdh+BFvfpuk=; b=kLTaA4cYYpELECL1W9/9mHwBbD8NCxK9QMNSSq2TB4TuNzCSyXaIAVqL7AVwVSFUS0 HJ5uBegiuStICQ/zJ+D57lQlLYeqdEO1Oy32bZVELg5o2XW7twa/gzlnSI+BCsFyLkSt zq6SeWNJkAo2k0uMGYtEMtlsiq1Ndyh1YSN4jwtUous+3Xc2PE22UCLg3SC+X1C0TEus eABxkxWPXd5LSE/9y/3snwPuExvxMoLuJrZv6cn0mRwBNriu+d0PXUfJ/t35NqtaK9CX Qy9rcTEcynAGXvHxSKr1JvbP7G8FOTap2aZk/Oz9fjHgXgt5XxRUB+5vGBWpYiA6y1i2 mutA== X-Forwarded-Encrypted: i=1; AJvYcCV3Q1YyYvJtSyYgighrFRRlRiEeCsDnYiXJaMFDlrUS+QpEX46UQoUA1oB7kypqDHIk9H+qdgEJTGrZKZPSyTbA@lists.infradead.org X-Gm-Message-State: AOJu0YxJ5Zq37o9jQdG+80Uy/NV0QQTviAKYyiZ/8kAdXbIT/YpFe5Po pvN9t8UFlZwHgOA0VAZ0BjvDiq8iDpDqzMhvgHMqJS+JHlfeQidmnQ6hpda7Tj0= X-Gm-Gg: ASbGncveYdFlz9MDTVvW+ZI1ubFpFr9Xf8fU0uD7YKp1LIkk/yggqySj1q7V7YGaH+o pAU5O1g8P0KfhAmaVbo+S6NW8Fnhyk6U5Eh3DFyTJ7WssnKPQDFGWKRpzLvo2FuoNpxhVot0+KH JEndVZwYT+lqYNapCAZOKHo5O304ivc0ulK6rRigbnjvSsUchNV9tg450ZWwJnv/SVdQqaMYoH8 wMMKN2oRMK7xzgRAgtJuwZO16Vtj65lbkQbm2kpDkRoU2OkEq0ObNriC+sYSQApuZmjAWksmg40 tozE3LM/VQ5SUbco/uepNw== X-Google-Smtp-Source: AGHT+IG0IOUDjXj7M8HLWY3rdlmEmUiO6k9aRVSVPoDq9wO9uWrUVEvcWB+pKuqU8J+AxzpC5sR7Iw== X-Received: by 2002:a17:907:3f12:b0:aa6:7220:f12f with SMTP id a640c23a62f3a-aac2ad8abccmr3008858366b.18.1735318664166; Fri, 27 Dec 2024 08:57:44 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:43 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 12/23] arm64: dts: imx8mn: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:15 +0100 Message-ID: <20241227165719.3902388-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085745_880376_AEF7B38A X-CRM114-Status: GOOD ( 10.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 49be492b5687..68efa77535cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -646,6 +646,7 @@ clk: clock-controller@30380000 { <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, From patchwork Fri Dec 27 16:56:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2140E7718B for ; Fri, 27 Dec 2024 17:14:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=z/Q5xeJIoq5Ujssv/lVVpXyTtV/F6QlZNcPSL4YMIqE=; b=z9u7iD0tx37xxQB4mLVOkI4e68 bRSNXmGh2BVuaRdDuTLIuHqzngrYp9oHE1qgdlDbzuqR+o6w2pXtPdl6NJ79AgMKqDvspEVJvVJLF LFXiLAKk6F3SRiMXLqfb3UhNyy3HEGshqkrTJ2mRSsHX5OQd1QsA5NKtWBzb30sc+vWzAn1WKCCQX J1mtfKICkxc0Ynn/ZxlfucM8u3p6LIMrnrA8VGjrZxzP1Sy1wZAtbbmM4WURh61ftWY/QXZiV72q+ jGL2Ld3Vpd+H1pSlHpqA0SJk1/nGzaIfqKxWvgmZaPhbsx0V2024qnuofBmB5V0pqG3Z1rJg/VAFM Bt63Iwbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDuN-00000000gy6-1Ope; Fri, 27 Dec 2024 17:13:55 +0000 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDek-00000000eYl-3iKv for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:47 +0000 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-aaef00ab172so487132866b.3 for ; Fri, 27 Dec 2024 08:57:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318665; x=1735923465; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z/Q5xeJIoq5Ujssv/lVVpXyTtV/F6QlZNcPSL4YMIqE=; b=pyubXaiO03Gxo2V3mqVUFRMAIfEPJE/maoNco8B2Ln5xKN64fI/s1ZxB9PpNp9ffq+ 0/XILoMpIkFYaHsiFDDe5xuuVzLHdmriluv2EfCQon5k2dda4eSrnxho5b0CV4rPWBsQ nUgY2miln1cILBFaOaw/ZH6wHxoxGkpDZn4IQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318665; x=1735923465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z/Q5xeJIoq5Ujssv/lVVpXyTtV/F6QlZNcPSL4YMIqE=; b=c+onrEZaVl/Fb6gU2THOKvgXIKRCkcvQJ0yH0NaSQScokAfdDjlmy67PDN1DwpoBjp X29gbGK+udYHfyuopcyg4XFdlLvw39VwksepdLC1qQ5k7u0xQO2xHrFPFSM9zqyjSPA6 b+W5FY19DyKFDx9DKKnZsju3uYj96ClggrCEU2MwBqrsY/ai1AReORFLvlefjwrsJx33 +MLgT+GdblSEQXf8JwCVQPLVc6e4PFIRgyQInC8Ha+yVNef5tbJpCVCVZXdyQUgZuvPA U/k3KfwrP5lpUB7NvB1yi1TIdC0M7Sxw+jwFchCiI3JdE+IKu9j2ucSFlxWWuhedJWuZ pl0g== X-Forwarded-Encrypted: i=1; AJvYcCVgpTckK+YOJQ2NXllu3vNGEEfXPkfzdGfbrOvM88+tATrZzxNH4RdOUATpK8jl+DK7pBOsUS2tLi3PxScu6RkK@lists.infradead.org X-Gm-Message-State: AOJu0YyhHbQxDoRwAnUFYCaMWI8IS3bpD0nzzCi1xmd6LoqG9E5akKHO 6let/mOpx0vMI83flf5X/z34w3L3kZY+RegYFqVE3DocOSvrjqdAR6vdtmpAqcI= X-Gm-Gg: ASbGncvClqvC57KSA6VsmGTz2xWBajFjj2sIde3N28PAYC03tgGQAeAXnc4CeXn1HAY eQ8ghQZbKFRELSpMM2PK8A7G+SITsI/9xYhttekttk6U6bCGhsYVQnp7VSVzZta5Fr7elr48mCR 1fT/CCd32X1rvhHnuKzW22UVqDg03s2CLBVisu5Om99s3Y3qVxFYvRl4foVCvEDKvzsXz7GxOUQ 5zBic4g+HxCrJAr6g3NtSNbHl3TTUJa/bPqJY+JmSNCvD6bLXaTiVJEFkg2neG5lmcJry3Nmdbi 557upXvH+z6dTCs74nB14g== X-Google-Smtp-Source: AGHT+IG7WGJrOsb7TyGRh1ACx7FW71ZyfueLA84uEuZp9U5n20JO6c7QeCVbSZ/v+tRXVp6Smkf9tQ== X-Received: by 2002:a05:6402:2802:b0:5d3:cff5:635e with SMTP id 4fb4d7f45d1cf-5d81de065b8mr63355995a12.26.1735318665532; Fri, 27 Dec 2024 08:57:45 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:45 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 13/23] arm64: dts: imx8mp: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:16 +0100 Message-ID: <20241227165719.3902388-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085746_923725_BA368D56 X-CRM114-Status: GOOD ( 10.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 0b928e173f29..a1872b5d6e2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -754,6 +754,7 @@ clk: clock-controller@30380000 { <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, From patchwork Fri Dec 27 16:56:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64BF2E7718B for ; Fri, 27 Dec 2024 17:15:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vOKJ3wQvbvnKfy50Gr8I3coc2Gwt+700w35xpJ+3wzM=; b=aBKuin4I5bbZ1MA2YGSG8rhYGC pym3R4Rv5XUT0yZqViAqjWFv1mBDjVs3Tw4Pie1Z5LBgS8A7z9X/Rgm9oz47Ptwn/auVWjDxB9zWD accaK5w5KMI7HBb4hQ9kNs9YH2kW/8skm+LNP761P+BRAc6xIKgZgsSDnIi7akbDiBTXweNySAhOQ uH4jqtAroVbVC0BHkacCrOfs9E8oco2/ccXzc8MCIefmDM+rfarb/bK2aTWCVLFRVn59vwbn4RTte 2HDaZEicUkROOZt7FA97H088hudbfIJxR4JRQ7rYqUYP8xFCvyfbkGyc0KLIpz/Iqeb8UYNFHEzCV 96kpK7dw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDvU-00000000h4U-4AXd; Fri, 27 Dec 2024 17:15:04 +0000 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDem-00000000eZH-33J1 for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:49 +0000 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-aa66e4d1d5aso1195252266b.2 for ; Fri, 27 Dec 2024 08:57:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318667; x=1735923467; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vOKJ3wQvbvnKfy50Gr8I3coc2Gwt+700w35xpJ+3wzM=; b=BEsMYRc7rPz3kZb9ssUYpxCd7cfPr1MWVvtljOtGffJFH+0G4k6Ht4wijgNiZCuZJF hqCehPg1Z+fsc2MnAAXeDKAve156swH3bV1i7eTMiDf8cWnvMrJA9S1KyTw/jm+BTEFo pC8qIjGNk7qjtaxerBTY++FSMrvcQSk5DAnJY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318667; x=1735923467; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vOKJ3wQvbvnKfy50Gr8I3coc2Gwt+700w35xpJ+3wzM=; b=vMDo+TrLBBPIIYJOeilzYJ4j8UG3/0HVvMeW1J/rQAbYOj2MFqSk43Xl1hJzMYlN8B ft97i23UQ1egs6nbm95cMq9fJJ4TsNSIoeiSxemkiMEKe0YTAwHaVSOHZnHGb5R1CTH+ ldzoCjMHA7q011AJEqbcpHZKll9UBilQ2mwQYa/OpQamvpdTVup857anaBnD183LtKf5 T5Uye1RrqvFQ6/Ur0xTTl7Uqr9Wro5px8+6OlVVQ7HUoAO34uhRYV8rYGnPakSRa+h1+ wRGCMxir6ekKIpv+FxKmTKuc1IPqQaqF7+55Pd/+C9xKBMV4SvrgD8Q7Hj9ZYXXyrcqz 5hRQ== X-Forwarded-Encrypted: i=1; AJvYcCWGQLEY/nB5RZudB4eowjVpXQ2lJsZudekWVgzEqJd4EAh6MkdMtWLBjqHYqfUvsueYcXPes2mt1sSt91YHnnYL@lists.infradead.org X-Gm-Message-State: AOJu0YzsDuu6Q3aGUN5uCgnJsILN3pGQt13bPRjAOfmBvJccGWjG48Wp vVc5HcUa0jV9sRDZebDKwJtqx/QFvJycnsj6J8S1W2fa7vLuthmK91Ja4dzZ+70= X-Gm-Gg: ASbGnctgagG+aGNvbIqrxISSvq91ZBH51eNfYUeJciktIOADMG0y8I8TGPKxo3jed/H +NcvhaPi89AsC3GA6AO+eCHqZmyohBS+I+nLGcLOPDBE6pqLUg1r7P21KIgyZHdREBq8Cj+AiV6 x9rmaY1VR8LGsVBlOBqZDimeIAmx6jmklPvkvXGooZhps7b+tHGP09XfPSGuER2nJ8XCKrIzgJ4 YnrPe3eJYUwIIkkj1oEvdJ6iHtC6Tr3PH0x/G7OdDOXjKAP23QvMEemOBRgMDwfJJSmqTInpG0o 2AhDsnYVeiHAeBxQh9igqA== X-Google-Smtp-Source: AGHT+IGgrc+HQYxCKLo2SLlUL/mY7iziyIkQErGfzOsjT9xrluZfeOeDPohhXk9ai5VYtyng9jIdHA== X-Received: by 2002:a17:907:961f:b0:aa6:abe2:5cba with SMTP id a640c23a62f3a-aac27026cfemr2873979066b.2.1735318666969; Fri, 27 Dec 2024 08:57:46 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:46 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 14/23] arm64: dts: imx8mq: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:17 +0100 Message-ID: <20241227165719.3902388-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085748_767022_BB50FAE9 X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1d1424a136f0..6f42e42e13e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -859,6 +859,7 @@ clk: clock-controller@30380000 { clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, <&clk IMX8MQ_CLK_NOC>, From patchwork Fri Dec 27 16:56:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B770E7718B for ; Fri, 27 Dec 2024 17:16:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2b1DvWsKR3kWK9JNfXRovoEHigCoxQCmQlYrGVfIyUo=; b=y2ZOlSCcA6OvNI+c9qY3jqvc+P HjL7l2GJ97ZrEjm/TintkCCsOrZDS8hNFK78y1KqlLioPUif0M/Ilrcg49UlbgEdFDYnCTPDRq58V OhKLkggMDqbGaaHWfC7rpvbEVS+/gU8z2CAn6jzJ/Sf+xV9eNDgvMQv/J7Ha3K3Pg64Wms1yIE8b1 LLPs+lAGY9gLZXwKM7iV/bI29su5mO0vndu1bOhJG37G+Xp0//6bbuJCA3ToEXdbZXbIM3adOEcZR Fh+ZCP+0bbeTSNchRp8YclnL/f+b26u09fmwWcqhI7tlqUj4U+3BZEHJSHRtrI6BfcVxlf7yxqrou 7LnqsGyQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tRDwd-00000000hFQ-38hG; Fri, 27 Dec 2024 17:16:15 +0000 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tRDen-00000000eZd-3A2A for linux-arm-kernel@lists.infradead.org; Fri, 27 Dec 2024 16:57:51 +0000 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-aaf0f1adef8so306550566b.3 for ; Fri, 27 Dec 2024 08:57:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318668; x=1735923468; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2b1DvWsKR3kWK9JNfXRovoEHigCoxQCmQlYrGVfIyUo=; b=SlgFXH7a2KmW/N4dE9uqZ4PwhGAdJXFM/5prlvnFA3m1PH8BVK7jhC77KBcsRQ0Lye Uey0eSN0FToyZ9s1eO82h+cwOlCpNO++AemMo5f4eIy6hhPoIMqTxCaEHdO5IUGscoxH U4PKtu/Op1xP59xhNaxBA7HP2Kw9tRVJ4dHQI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318668; x=1735923468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2b1DvWsKR3kWK9JNfXRovoEHigCoxQCmQlYrGVfIyUo=; b=visid5RE/HrM7iZHozF2XMciVW1CI3nZ/u+7pPAWzz96+uMqupfx73Ej2OiK72A/KJ fDg04+YbqFq9yDMDMwNUJN125+gx22iX/GNIr/t/jJXm1AslpT3A+TDVS2ob3v9wKij1 2k2GfaMw2MF8GGBvpNg4G5IRSM9X6ZKKV18bt9ZMFzj7/pe8WB73vfaEjcAxgk7xtP7O YLMgZkFYyhhrLe+Ja62sxsu3ujTFQ3q5i0HkFhC6wxmbZfM46H71E7OP2YzyxiM4Ntw3 pINzO1vmJA6Utk6L5Kg/PIgqpnPTbvUby5kieCfNjnMl85mAcXjEsuYXOSx9puTVj9xC +qtA== X-Forwarded-Encrypted: i=1; AJvYcCXMl32D3P8an/KjI6Sb7n8X1xbLKXhOlE956A+JKjr0i5VenhvQdRm259XMStiMABQwNoNCIOrF0Uaep1uXwsHT@lists.infradead.org X-Gm-Message-State: AOJu0YxsgeHs9SontvMjvje+AeMISqYcqTQEOrsAYdxS+Btpm/Gl3cCX Pm+xAt22G4oXVgBdM4ARUdj7bQmWALM3+FHACyNaVSZKblM2qQ2DZ88laSwfRi0= X-Gm-Gg: ASbGncvHR9smc+siFXS8zdINpzhQc6TRsRiZ9/dtO7wdgqaxLECy2cLE3YAfUpLSW3Z VqyltUnOEe1j3w21RWnNkanHrI11/85vdcEIJzVaCx09ls5vFgW2RV073obqgNJuBOJ9PSIbLY9 O56qfFGDTb+Yy+XoHDgZWVuDf4pCDIRF4vXAX+0IgCIby/0lq+V/0pvZUj90WhD0sOOXth2/Cod fKnL0/w2OWWYbhnOIzie34U4p4ELs0SPrMPSA10vdfxsUgTwjELrkCF2VxiyE5/nRTYdQkAdfiK XwsmU6zLDuLXp0Zl7vjp4g== X-Google-Smtp-Source: AGHT+IFdtsrBznelwwJuBM0+oIFuAtsVZztgwfPwBkxRjqySUJIDbs8HNHC7GQMygSlEz9WnVs+UvA== X-Received: by 2002:a17:907:704:b0:aac:23db:af61 with SMTP id a640c23a62f3a-aac2874937fmr2719500066b.3.1735318668380; Fri, 27 Dec 2024 08:57:48 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:48 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 15/23] clk: imx: add hw API imx_anatop_get_clk_hw Date: Fri, 27 Dec 2024 17:56:18 +0100 Message-ID: <20241227165719.3902388-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085749_793850_FAC7A442 X-CRM114-Status: GOOD ( 11.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Get the hw of a clock registered by the anatop module. This function is preparatory for future developments. Signed-off-by: Dario Binacchi --- Changes in v7: - Add device_node type parameter to imx8m_anatop_get_clk_hw() - Rename imx8m_anatop_get_clk_hw() to imx_anatop_get_clk_hw() - Drop the gaurding macros so the code can be used also by i.MX9 Changes in v5: - Consider CONFIG_CLK_IMX8M{M,N,P,Q}_MODULE to fix compilation errors Changes in v4: - New drivers/clk/imx/clk.c | 15 +++++++++++++++ drivers/clk/imx/clk.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index df83bd939492..a906d3cd960b 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -128,6 +128,21 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name) } EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); +struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id) +{ + struct of_phandle_args args; + struct clk_hw *hw; + + args.np = np; + args.args_count = 1; + args.args[0] = id; + + hw = __clk_get_hw(of_clk_get_from_provider(&args)); + pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw)); + return hw; +} +EXPORT_SYMBOL_GPL(imx_anatop_get_clk_hw); + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..50e407cf48d9 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -487,4 +487,6 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask); +struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id); + #endif From patchwork Fri Dec 27 16:56:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E8D7E7718B for ; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:49 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 16/23] clk: imx: add support for i.MX8MN anatop clock driver Date: Fri, 27 Dec 2024 17:56:19 +0100 Message-ID: <20241227165719.3902388-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085751_778770_C188C05F X-CRM114-Status: GOOD ( 18.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi --- Changes in v7: - Update the code based on the changes made to the imx8m_anatop_get_clk_hw(): - Rename imx8m_anatop_get_clk_hw to imx_anatop_get_clk_hw - Add device_node type parameter - Call of_parse_phandle() to get the anatop's device node. Changes in v6: - Define IMX8MN_ANATOP_CLK_END inside the driver after it has ben removed from include/dt-bindings/clock/imx8mn-clock.h. Changes in v4: - New drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mn.c | 186 ++++++++---------- 3 files changed, 367 insertions(+), 104 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..f0f1d01c68f8 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -26,7 +26,7 @@ mxc-clk-objs += clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o -obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o +obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn-anatop.o clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8mn-anatop.c new file mode 100644 index 000000000000..43101b0a758e --- /dev/null +++ b/drivers/clk/imx/clk-imx8mn-anatop.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver + * + * Copyright (c) 2022 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define IMX8MN_ANATOP_CLK_END IMX8MN_ANATOP_CLK_CLKOUT2 + +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; +static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "dummy", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mn_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MN_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = IMX8MN_ANATOP_CLK_END; + hws = clk_hw_data->hws; + + hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] = + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] = + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] = + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] = + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] = + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] = + imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] = + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] = + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MN_ANATOP_AUDIO_PLL1] = + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MN_ANATOP_AUDIO_PLL2] = + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MN_ANATOP_VIDEO_PLL] = + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MN_ANATOP_DRAM_PLL] = + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, + &imx_1443x_dram_pll); + hws[IMX8MN_ANATOP_GPU_PLL] = + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_M7_ALT_PLL] = + imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MN_ANATOP_ARM_PLL] = + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MN_ANATOP_SYS_PLL3] = + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, + &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] = + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] = + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] = + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] = + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] = + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] = + imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, + m7_alt_pll_bypass_sels, + ARRAY_SIZE(m7_alt_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] = + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] = + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] = + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] = + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] = + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MN_ANATOP_DRAM_PLL_OUT] = + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MN_ANATOP_GPU_PLL_OUT] = + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] = + imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", + base + 0x74, 11); + hws[IMX8MN_ANATOP_ARM_PLL_OUT] = + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MN_ANATOP_SYS_PLL3_OUT] = + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL1_OUT] = + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); + hws[IMX8MN_ANATOP_SYS_PLL1_40M] = + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL1_80M] = + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL1_100M] = + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL1_133M] = + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL1_160M] = + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL1_200M] = + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL1_266M] = + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL1_400M] = + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL1_800M] = + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL2_OUT] = + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); + hws[IMX8MN_ANATOP_SYS_PLL2_50M] = + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL2_100M] = + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL2_125M] = + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL2_166M] = + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL2_200M] = + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL2_250M] = + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL2_333M] = + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL2_500M] = + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL2_1000M] = + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] = + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] = + imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, + 0, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT1] = + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] = + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] = + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT2] = + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END); + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mn_anatop_clk_of_match[] = { + { .compatible = "fsl,imx8mn-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match); + +static struct platform_driver imx8mn_anatop_clk_driver = { + .probe = imx8mn_anatop_clocks_probe, + .driver = { + .name = "imx8mn-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs = true, + .of_match_table = imx8mn_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mn_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..984331372139 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -24,16 +24,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; -static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; -static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; -static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; -static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; -static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; -static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; -static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; - static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -308,21 +298,20 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "dummy", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; static int imx8mn_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; + struct device_node *np = dev->of_node, *anp; void __iomem *base; int ret; + base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MN_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -331,99 +320,93 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMX8MN_CLK_END; hws = clk_hw_data->hws; - hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + anp = of_parse_phandle(np, "fsl,anatop", 0); + if (!anp) { + anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + } + + of_node_put(anp); + + hws[IMX8MN_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_DUMMY); + hws[IMX8MN_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_24M); + hws[IMX8MN_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_32K); hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); - base = devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(base))) { - ret = PTR_ERR(base); - goto unregister_hws; - } - - hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); - hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); - hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll); + hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL); + hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL); + hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_REF_SEL); + hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_REF_SEL); + hws[IMX8MN_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_REF_SEL); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL); + hws[IMX8MN_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_REF_SEL); + hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL); + + hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1); + hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2); + hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL); + hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL); + hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); + hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL); + hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL); + hws[IMX8MN_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1); + hws[IMX8MN_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2); + hws[IMX8MN_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3); /* PLL bypass out */ - hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_BYPASS); + hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_BYPASS); + hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_BYPASS); + hws[IMX8MN_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_BYPASS); + hws[IMX8MN_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_BYPASS); + hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_BYPASS); + hws[IMX8MN_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_BYPASS); + hws[IMX8MN_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_BYPASS); /* PLL out gate */ - hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); - hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13); - hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); - hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); - hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11); - hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); - hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); + hws[IMX8MN_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_OUT); + hws[IMX8MN_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_OUT); + hws[IMX8MN_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_OUT); + hws[IMX8MN_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_OUT); + hws[IMX8MN_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_OUT); + hws[IMX8MN_M7_ALT_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_OUT); + hws[IMX8MN_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_OUT); + hws[IMX8MN_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_OUT); /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); - hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); - hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); - hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); - hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); - hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); - hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); - hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); - hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + hws[IMX8MN_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_OUT); + hws[IMX8MN_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_40M); + hws[IMX8MN_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_80M); + hws[IMX8MN_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_100M); + hws[IMX8MN_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_133M); + hws[IMX8MN_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_160M); + hws[IMX8MN_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_200M); + hws[IMX8MN_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_266M); + hws[IMX8MN_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_400M); + hws[IMX8MN_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_800M); /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); - hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); - hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); - hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); - hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); - hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); - hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); - hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); - hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); - - hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4); - hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); - hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4); - hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); - - np = dev->of_node; - base = devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) { - ret = PTR_ERR(base); - goto unregister_hws; - } + hws[IMX8MN_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_OUT); + hws[IMX8MN_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_50M); + hws[IMX8MN_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_100M); + hws[IMX8MN_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_125M); + hws[IMX8MN_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_166M); + hws[IMX8MN_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_200M); + hws[IMX8MN_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_250M); + hws[IMX8MN_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_333M); + hws[IMX8MN_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_500M); + hws[IMX8MN_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_1000M); + + hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_SEL); + hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_DIV); + hws[IMX8MN_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1); + hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_SEL); + hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_DIV); + hws[IMX8MN_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2); /* CORE */ hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000); @@ -599,18 +582,15 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); if (ret < 0) { - dev_err(dev, "failed to register hws for i.MX8MN\n"); - goto unregister_hws; + imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); + return dev_err_probe(dev, ret, + "failed to register hws for i.MX8MN\n"); } imx_register_uart_clocks(); + dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n"); return 0; - -unregister_hws: - imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); - - return ret; } static const struct of_device_id imx8mn_clk_of_match[] = { From patchwork Fri Dec 27 16:56:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CEDFE7718B for ; Fri, 27 Dec 2024 17:18:47 +0000 (UTC) DKIM-Signature: v=1; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:51 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 17/23] dt-bindings: clock: imx8m-clock: add PLLs Date: Fri, 27 Dec 2024 17:56:20 +0100 Message-ID: <20241227165719.3902388-18-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085752_991591_305B0D7D X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Though adding the PLLs to clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - New .../bindings/clock/imx8m-clock.yaml | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index b23e639e6389..eb2e6e702de9 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -29,12 +29,12 @@ properties: maxItems: 2 clocks: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 clock-names: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 '#clock-cells': const: 1 @@ -94,6 +94,10 @@ allOf: - description: ext2 clock input - description: ext3 clock input - description: ext4 clock input + - description: audio1 PLL input + - description: audio2 PLL input + - description: dram PLL input + - description: video PLL input clock-names: items: @@ -103,20 +107,31 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + - const: audio_pll1 + - const: audio_pll2 + - const: dram_pll + - const: video_pll additionalProperties: false examples: # Clock Control Module node: - | + #include + clock-controller@30380000 { compatible = "fsl,imx8mm-ccm"; reg = <0x30380000 0x10000>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop = <&anatop>; }; From patchwork Fri Dec 27 16:56:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D107DE7718B for ; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:52 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 18/23] arm64: dts: imx8mm: add PLLs to clock controller module (CCM) Date: Fri, 27 Dec 2024 17:56:21 +0100 Message-ID: <20241227165719.3902388-19-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085754_358395_C772CF32 X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index b1a4cc521bf4..c3287978c42b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -642,9 +642,14 @@ clk: clock-controller@30380000 { ; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, <&clk IMX8MM_CLK_A53_CORE>, From patchwork Fri Dec 27 16:56:22 2024 Content-Type: text/plain; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:54 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 19/23] arm64: dts: imx8mn: add PLLs to clock controller module (CCM) Date: Fri, 27 Dec 2024 17:56:22 +0100 Message-ID: <20241227165719.3902388-20-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085755_811613_0EFAE11D X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 68efa77535cb..ef25c4a655ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -643,9 +643,14 @@ clk: clock-controller@30380000 { ; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_DRAM_PLL>, + <&anatop IMX8MN_ANATOP_VIDEO_PLL>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, From patchwork Fri Dec 27 16:56:23 2024 Content-Type: text/plain; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 20/23] arm64: dts: imx8mp: add PLLs to clock controller module (CCM) Date: Fri, 27 Dec 2024 17:56:23 +0100 Message-ID: <20241227165719.3902388-21-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085757_212295_E8332522 X-CRM114-Status: UNSURE ( 9.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a1872b5d6e2e..ccf990a63372 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -751,9 +751,14 @@ clk: clock-controller@30380000 { ; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_DRAM_PLL>, + <&anatop IMX8MP_ANATOP_VIDEO_PLL>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop = <&anatop>; assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, <&clk IMX8MP_CLK_A53_CORE>, From patchwork Fri Dec 27 16:56:24 2024 Content-Type: text/plain; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:57 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 21/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Date: Fri, 27 Dec 2024 17:56:24 +0100 Message-ID: <20241227165719.3902388-22-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085759_224531_81FE428C X-CRM114-Status: GOOD ( 16.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The addition of DT bindings for enabling and tuning spread spectrum clocking generation can be applied specifically to the PLLs. The "" value for the fsl,ssc-method property is specifically intended to specify a "no SSC" case, as in the example, when you don't want to configure spread spectrum for one of the PLLs, thus avoiding the use of a method that would only make sense if SSC were being set. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - List the PLLs to strictly define the setup order for each of the added properties - Drop maxItems from "fsl,ssc-modfreq-hz" and "fsl,ssc-modrate-percent" properties - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - Improve the commit message - change minItems from 7 to 1 for all the ssc properties added - change maxItems from 10 to 4 for alle the ssc properties added - update the DTS example Changes in v4: - Drop "fsl,ssc-clocks" property. The other added properties now refer to the clock list. - Updated minItems and maxItems of - clocks - clock-names - fsl,ssc-modfreq-hz - fsl,ssc-modrate-percent - fsl,ssc-modmethod - Updated the dts examples Changes in v3: - Added in v3 - The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. .../bindings/clock/imx8m-clock.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index eb2e6e702de9..76040ee9cd5c 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -50,6 +50,46 @@ properties: along with the oscillators, are used to generate the clocks for the on-chip peripherals. + fsl,ssc-modfreq-hz: + description: + The values of modulation frequency (Hz unit) for each clock + supporting spread spectrum. + minItems: 1 + items: + - description: audio_pll1 + - description: audio_pll2 + - description: dram_pll + - description: video_pll + + fsl,ssc-modrate-percent: + description: + The percentage values of modulation rate for each clock + supporting spread spectrum. + minItems: 1 + items: + - description: audio_pll1 + - description: audio_pll2 + - description: dram_pll + - description: video_pll + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: | + The modulation techniques for each clock supporting spread + spectrum in this order:: + - audio_pll1 + - audio_pll2 + - dram_pll + - video_pll + minItems: 1 + maxItems: 4 + items: + enum: + - "" + - down-spread + - up-spread + - center-spread + required: - compatible - reg @@ -84,6 +124,10 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + fsl,ssc-modfreq-hz: false + fsl,ssc-modrate-percent: false + fsl,ssc-modmethod: false + else: properties: clocks: @@ -133,6 +177,9 @@ examples: "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", "dram_pll", "video_pll"; fsl,anatop = <&anatop>; + fsl,ssc-modfreq-hz = <6818>, <0>, <0>, <2419>; + fsl,ssc-modrate-percent = <3>, <0>, <0>, <7>; + fsl,ssc-modmethod = "down-spread", "", "", "center-spread"; }; - | From patchwork Fri Dec 27 16:56:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE144E7718B for ; Fri, 27 Dec 2024 17:24:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:58 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 22/23] clk: imx: pll14xx: support spread spectrum clock generation Date: Fri, 27 Dec 2024 17:56:25 +0100 Message-ID: <20241227165719.3902388-23-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085800_707232_F39754A6 X-CRM114-Status: GOOD ( 19.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for spread spectrum clock (SSC) generation to the pll14xxx driver. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v6: - Update the code based on the changes made to the DT bindings drivers/clk/imx/clk-pll14xx.c | 134 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 16 ++++ 2 files changed, 150 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..c20f1ade9dff 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) #define LOCK_TIMEOUT_US 10000 @@ -40,6 +46,8 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + bool ssc_enable; + struct imx_pll14xx_ssc ssc_conf; }; #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long parent_rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *conf = &pll->ssc_conf; + u32 sscg_ctrl, mfr, mrr; + + sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &= + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + mfr = parent_rate / (conf->mod_freq * pdiv * (1 << 5)); + mrr = (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, conf->mod_type); + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } @@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, gnrl_ctl &= ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } @@ -542,3 +577,102 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + pll->ssc_enable = true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc); + +static int clk_pll14xx_ssc_mod_type(const char *name, + enum imx_pll14xx_ssc_mod_type *mod_type) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_types[] = { + { .name = "down-spread", .id = IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name = "up-spread", .id = IMX_PLL14XX_SSC_UP_SPREAD }, + { .name = "center-spread", .id = IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i = 0; i < ARRAY_SIZE(mod_types); i++) { + if (!strcmp(name, mod_types[i].name)) { + *mod_type = mod_types[i].id; + return 0; + } + } + + return -EINVAL; +} + +static int clk_pll14xx_ssc_index(const char *pll_name) +{ + static const char *const pll_names[] = { + "audio_pll1", + "audio_pll2", + "dram_pll", + "video_pll" + }; + int i; + + for (i = 0; i < ARRAY_SIZE(pll_names); i++) { + if (!strcmp(pll_names[i], pll_name)) + return i; + } + + return -ENODEV; +} + +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name, + struct imx_pll14xx_ssc *conf) +{ + int index, ret; + const char *s; + + if (!conf) + return -EINVAL; + + index = clk_pll14xx_ssc_index(pll_name); + if (index < 0) + return index; + + ret = of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", index, + &conf->mod_freq); + if (ret) + return ret; + + ret = of_property_read_u32_index(np, "fsl,ssc-modrate-percent", index, + &conf->mod_rate); + if (ret) { + pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n", + np); + return ret; + } + + ret = of_property_read_string_index(np, "fsl,ssc-modmethod", index, &s); + if (ret) { + pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n", + np); + return ret; + } + + if (strlen(s) == 0) + return -ENODEV; + + ret = clk_pll14xx_ssc_mod_type(s, &conf->mod_type); + if (ret) { + pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np); + return ret; + } + + pr_debug("%s: SSC %s settings: mod_freq: %d, mod_rate: %d: mod_method: %s [%d]\n", + __func__, pll_name, conf->mod_freq, conf->mod_rate, s, conf->mod_type); + + return 0; +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 50e407cf48d9..38e4a4cf253d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -69,6 +69,18 @@ struct imx_pll14xx_clk { int flags; }; +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; @@ -489,4 +501,8 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id); +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf); +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name, + struct imx_pll14xx_ssc *conf); + #endif From patchwork Fri Dec 27 16:56:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13922059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE823E7718B for ; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:58:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 23/23] clk: imx8mn: support spread spectrum clock generation Date: Fri, 27 Dec 2024 17:56:26 +0100 Message-ID: <20241227165719.3902388-24-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241227_085803_348118_D3AC1064 X-CRM114-Status: GOOD ( 15.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v7: - Add and manage fsl,anatop property as phandle to the anatop node with the new patches: - 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop - 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM - 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM - 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM - 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM Changes in v6: - Merge patches: 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop to 05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names now renamed 05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs - Split the patch 15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch into 12/18 dt-bindings: clock: imx8m-clock: add PLLs 16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking Changes in v5: - Fix compilation errors. - Separate driver code from dt-bindings Changes in v4: - Add dt-bindings for anatop - Add anatop driver - Drop fsl,ssc-clocks from spread spectrum dt-bindings Changes in v3: - Patches 1/8 has been added in version 3. The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. - Patches {3,5}/8 have been added in version 3. - Patches {4,6,8}/8 use ccm device node instead of the anatop one. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 984331372139..9a04e8138b7d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; base = devm_platform_ioremap_resource(pdev, 0); @@ -347,9 +348,21 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL); hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf); + hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf); + hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf); + hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf); + hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL); hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL);