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([2401:4900:1c07:9010:ac08:3a91:844a:cc65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbd3sm14877943b3a.110.2024.12.27.11.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 11:02:37 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/6] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block Date: Fri, 27 Dec 2024 19:02:05 +0000 Message-ID: <20241227190210.69025-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. For example, specific bits in these registers indicate resets caused by events such as underflow or overflow of the watchdog timer. This functionality allows the watchdog driver to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Add the syscon-compatible property to the RZ/V2H(P) and RZ/G3E CPG block, allowing drivers to interact with the CPG_ERROR_RSTm registers as required. Signed-off-by: Lad Prabhakar --- v1->v2 - No change --- .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f42d79e73e70 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -17,9 +17,11 @@ description: properties: compatible: - enum: - - renesas,r9a09g047-cpg # RZ/G3E - - renesas,r9a09g057-cpg # RZ/V2H + items: + - enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H + - const: syscon reg: maxItems: 1 @@ -73,7 +75,7 @@ additionalProperties: false examples: - | clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0x10420000 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 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([2401:4900:1c07:9010:ac08:3a91:844a:cc65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbd3sm14877943b3a.110.2024.12.27.11.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 11:02:43 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/6] arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node Date: Fri, 27 Dec 2024 19:02:06 +0000 Message-ID: <20241227190210.69025-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `syscon` compatible for CPG node to allow the IP blocks to interact with the CPG registers as needed. Signed-off-by: Lad Prabhakar --- v1->v2 - No change --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 7a422e9ad29e..f4e865b534a3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -132,7 +132,7 @@ soc: soc { ranges; cpg: clock-controller@10420000 { - compatible = "renesas,r9a09g047-cpg"; + compatible = "renesas,r9a09g047-cpg", "syscon"; reg = <0 0x10420000 0 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; From patchwork Fri Dec 27 19:02:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 13922075 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25DBB1F8AEB; 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([2401:4900:1c07:9010:ac08:3a91:844a:cc65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbd3sm14877943b3a.110.2024.12.27.11.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 11:02:48 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/6] arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node Date: Fri, 27 Dec 2024 19:02:07 +0000 Message-ID: <20241227190210.69025-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `syscon` compatible for CPG node to allow the IP blocks to interact with the CPG registers as needed. Signed-off-by: Lad Prabhakar --- v1->v2 - No change --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index e39da64a32e9..69de6c302b17 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -243,7 +243,7 @@ pinctrl: pinctrl@10410000 { }; cpg: clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0 0x10420000 0 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; From patchwork Fri Dec 27 19:02:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 13922076 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B28C21F8AFA; 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Fri, 27 Dec 2024 11:02:54 -0800 (PST) Received: from prasmi.. ([2401:4900:1c07:9010:ac08:3a91:844a:cc65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbd3sm14877943b3a.110.2024.12.27.11.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 11:02:54 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 4/6] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property Date: Fri, 27 Dec 2024 19:02:08 +0000 Message-ID: <20241227190210.69025-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The RZ/V2H(P) CPG block includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. In the event of a watchdog overflow or underflow, a system reset is issued, and the CPG_ERROR_RST2[0/1/2/3] bits are set depending on the watchdog in use: CM33 = 0, CA55 = 1, CR8_0 = 2, CR8_1 = 3. For the watchdog driver to determine and report the current boot status, it needs to read the CPG_ERROR_RST2[0/1/2/3]bits and provide this information to the user upon request. To facilitate this operation, add `renesas,syscon-cpg-error-rst` property to the WDT node, which maps to the `syscon` CPG node, enabling retrieval of the necessary information. Additionally, the property is marked as required for the RZ/V2H(P) SoC to ensure future compatibility (e.g., where the same IP block is present on the RZ/G3E SoC) and explicitly disallowed for other SoCs. Signed-off-by: Lad Prabhakar --- v1->v2 - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst` - Updated commit message --- .../bindings/watchdog/renesas,wdt.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 29ada89fdcdc..ca62ae8b1b0c 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -112,6 +112,19 @@ properties: timeout-sec: true + renesas,syscon-cpg-error-rst: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The first cell is a phandle to the SYSCON entry required to obtain + the current boot status. The second cell specifies the CPG_ERROR_RSTm + register offset within the SYSCON, and the third cell indicates the + bit within the CPG_ERROR_RSTm register. + items: + - items: + - description: Phandle to the CPG node + - description: The CPG_ERROR_RSTm register offset + - description: The bit within CPG_ERROR_RSTm register of interest + required: - compatible - reg @@ -182,7 +195,11 @@ allOf: properties: interrupts: false interrupt-names: false + required: + - renesas,syscon-cpg-error-rst else: + properties: + renesas,syscon-cpg-error-rst: false required: - interrupts From patchwork Fri Dec 27 19:02:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 13922077 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED161F9412; 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([2401:4900:1c07:9010:ac08:3a91:844a:cc65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbd3sm14877943b3a.110.2024.12.27.11.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 11:03:00 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information Date: Fri, 27 Dec 2024 19:02:09 +0000 Message-ID: <20241227190210.69025-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar On the RZ/V2H(P) SoC we can determine if the current boot is due to `Power-on-Reset` or due to the `Watchdog`. The information used to determine this is present on the CPG block. The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an reset. CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an underflow/overflow on WDT1 causing an error interrupt. To fetch this information from CPG block `syscon` is used and bootstatus field in the watchdog device is updated based on the CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it. Signed-off-by: Lad Prabhakar --- v1->v2 - Returned ret in error path instead of -EINVAL - Dropped unnecessar regmap_read --- drivers/watchdog/rzv2h_wdt.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index 8defd0241213..ab7e35928190 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -4,14 +4,17 @@ * * Copyright (C) 2024 Renesas Electronics Corporation. */ +#include #include #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -40,6 +43,9 @@ #define WDT_DEFAULT_TIMEOUT 60U +#define CPG_ERROR_RST2(x) BIT(x) +#define CPG_ERROR_RST2_WEN(x) BIT((x) + 16) + static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" @@ -206,9 +212,37 @@ static const struct watchdog_ops rzv2h_wdt_ops = { static int rzv2h_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct rzv2h_wdt_priv *priv; + unsigned int bootstatus = 0; + struct regmap *syscon; int ret; + /* Do not error out to maintain old DT compatibility */ + syscon = syscon_regmap_lookup_by_phandle(np, "renesas,syscon-cpg-error-rst"); + if (!IS_ERR(syscon)) { + struct of_phandle_args args; + u32 reg; + + ret = of_parse_phandle_with_fixed_args(np, "renesas,syscon-cpg-error-rst", + 2, 0, &args); + if (ret) + return ret; + + ret = regmap_read(syscon, args.args[0], ®); + if (ret) + return ret; + + if (reg & CPG_ERROR_RST2(args.args[1])) { + ret = regmap_write(syscon, args.args[0], + CPG_ERROR_RST2(args.args[1]) | + CPG_ERROR_RST2_WEN(args.args[1])); + if (ret) + return ret; + } + bootstatus = reg & CPG_ERROR_RST2(args.args[1]) ? WDIOF_CARDRESET : 0; + } + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -243,6 +277,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev) priv->wdev.info = &rzv2h_wdt_ident; priv->wdev.ops = &rzv2h_wdt_ops; priv->wdev.parent = dev; + priv->wdev.bootstatus = bootstatus; watchdog_set_drvdata(&priv->wdev, priv); watchdog_set_nowayout(&priv->wdev, nowayout); watchdog_stop_on_unregister(&priv->wdev); From patchwork Fri Dec 27 19:02:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 13922078 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A5431F8AD8; Fri, 27 Dec 2024 19:03:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735326188; cv=none; b=YBbXscigG0vwQU6mzYfwbVzG9+5KQkwpIxkuJ+i3JXkGm9n1xfv1j3qX9olTPqlv5sslRC69UKUXI7IjCR0euyRmgh7VO3qGHWiJfN4unkabhkHCAJjj7aQLe0ZOh7eHiJCWtOUXCS+U+idZB6gaLcrinTIgJUc7kXo5/xYkCTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735326188; c=relaxed/simple; bh=/IAGnTy2IYyK4HHK19qpN0BQgEWU57aHh+40aFZGiPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eyCZ1dSwqINJFVgjhTsmP1Nk8dfvTRJAe4FNt+vCDVVQafwlXHmvT/3ZFbwg5GFHzGfpfzPbbsd2TxV66AytsmUN7DE4wOlEjHWL8aozrtxR8B72YMrrkO/y2KxV1DcDVZwrCEQh2zW/IXw2ixQ6urrLV74zFlpXWg6lI1M6wRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=L+0OrFKG; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L+0OrFKG" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-21680814d42so81540885ad.2; Fri, 27 Dec 2024 11:03:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735326186; x=1735930986; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V1J2dnV8brqVh/DdliqC6kZPsixqWVPm/rUxD17Pm08=; b=L+0OrFKG/MkzWHLnb9liXkz1WBi5vztIpe70fzdk9AaRtI4MaWHMDOb0/lDpiEcaNr Le2Igr4p6XsEz2l42sfjm8dVIQUjG6/7D/nJ9F52sGy2lDIHOxhgqH2MAv2eM5OZw3m2 +TBVyRwolYiLEvlbECDCZjqxVoxmwiqrjjTD18h5EX9U2rW9B3sIwVJGhgIF8D3biCM0 jizhnaqgc97X4H8J3q9B0rfahw5Ak9gZgJKoHp5WTzjMpZsjTX/nuoaLjL17NmogxCXx UrPP8j/QgwEXtNsbFw1vxLC6HUlPcl+2iP7k7zOavypIghrHSMpzQgxvAB8wuRC9wTen 2HBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735326186; x=1735930986; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V1J2dnV8brqVh/DdliqC6kZPsixqWVPm/rUxD17Pm08=; b=jMqQshAHz1MEAAjqPPm0b8J4WLmy4HVLFWUFKm8IwWyoz2skY6uEIM0rpjZq8A0v5T LtRv5xFUA4IOkBjM0AzGUhvAVj8FG9PRHiQ6LVblX/WI48gqSD1Zlils5KUlIFC3oJee Axsn0kx79YGEmQClnovBzSUlbMaYXui09999oWXD+Z7UI7MPqOE3ZDhZrd2PPPRXURTu Fpulm3FMKeswP/6uS/cXHpRc5GckEQB6xD7wPn8/GoSRJ3Zew7VVapi/i7ig7YQ2jSR1 30936zNCwkg5WRUyvEGfPfrjrjyIOm3f924mpWamzclfQNWkTOvS8gwnljMDRdPkYiTh Vukg== X-Forwarded-Encrypted: i=1; AJvYcCVWKW+EB4lOuqmUAnJIyPhbFFMMfATSccaQ9QtcKXZLOHJUnCcWvSSxu4jnBC6vKTs1MiJy2PDKS9TWC7ErEIE=@vger.kernel.org, AJvYcCWanYzLNLWQu3QZkxRZLohzDTkzQjWt4BJOBC0nOJKyuiAl0yTURLonnitSWJrl904eg/rTHd/SGscTtShL@vger.kernel.org, AJvYcCXUxCGq0rHxbAfxM5ByL/Rb9PNos6fAPQDafkehe4MrgHEvUBCZnZxcrDczVWWM1byrKmwEqJsig0FL@vger.kernel.org, AJvYcCXePSuh53spRKqZO7II9YmjIWOdW761SbFyP4HMaaHhgfRpKM8NqDRGeNGK8XYSnefGqRmsjNaAkozs@vger.kernel.org X-Gm-Message-State: AOJu0YzgvOr1uKLwc/DHEVMIzv70ZTAU8bidl/8g+dEYHGMMot485vFj fEY0iQ+elyeCj1vQi8wYb4JYQgRQAjxtK0p7AA2CrNtgclMsGfcW X-Gm-Gg: ASbGncs2mE8az1VOhfbMzHA1XMgvd3gwQfSwSjQadsv3XuW2gBCQWY1PTcLrk41DqQO nOdUlkVUIqncEs4d4th2ccgCOiy9lGyMWJW8M/oZV5HNWsNdcevVbluX1M+93lFEE3nN/2NoznV wAy12bbaZRchu+3+cwrCUb2uSRZcWsvCVjeW8br1OLUpZDobcZvKLS+983YoIPWQGjRvBvvUfGY Ym3gAlNCiouX7fThNK71q1xoJMZ00fq2TxGzBGnCTsucPkL4tK94QN3AIPxveanSKpZvNz+5OAZ 3sWQjIM= X-Google-Smtp-Source: AGHT+IFL+M73myxJNmX1bGIfrW37yeUdq+u1cotILMeODj/VRZzE/LPIf1prAWoT2pg7kdjxJshCMw== X-Received: by 2002:a05:6a20:d48f:b0:1e1:9fef:e974 with SMTP id adf61e73a8af0-1e5e04a3040mr44538890637.24.1735326186240; Fri, 27 Dec 2024 11:03:06 -0800 (PST) Received: from prasmi.. ([2401:4900:1c07:9010:ac08:3a91:844a:cc65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbd3sm14877943b3a.110.2024.12.27.11.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 11:03:05 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 6/6] arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst` property to WDT node Date: Fri, 27 Dec 2024 19:02:10 +0000 Message-ID: <20241227190210.69025-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241227190210.69025-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `renesas,syscon-cpg-error-rst` property to WDT node, to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Signed-off-by: Lad Prabhakar --- v1->v2 - No change --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 69de6c302b17..efc3fd582e12 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -445,6 +445,7 @@ wdt0: watchdog@11c00400 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x75>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 0>; status = "disabled"; }; @@ -455,6 +456,7 @@ wdt1: watchdog@14400000 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x76>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>; status = "disabled"; }; @@ -465,6 +467,7 @@ wdt2: watchdog@13000000 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x77>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 2>; status = "disabled"; }; @@ -475,6 +478,7 @@ wdt3: watchdog@13000400 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x78>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 3>; status = "disabled"; };