From patchwork Mon Dec 30 03:43:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Karl.Li" X-Patchwork-Id: 13923033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39376E77188 for ; Mon, 30 Dec 2024 03:49:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=K2BfXDrGZ7RvRP4Ca4D5lZ3ETGg9zyB/1qmZRsOCQzA=; b=jEEAN4xIEJzyQOJy5b3I83yUqe ijLqstHhJTYONAVgSL37nczpqOWFcPiT64bwXx0PG9pl789Tb9TMxw7OEoy8RggmnxMBARNbOpTOo eZqnDcx5ygoCtCtqf8LsMUyz/j1ms9af+ee6gcZGplGAxz8woSJoo9HGYW0Fx4l76g5RYicExw0Nl qQfuq8F6yl3t1f+v+wozHLtdrdFiCqobpDD0ZHvlnUN6SQmd7FPaFKx8PSD0W8Z4v49e4UeZplQyI 4BT4qIqeyP0kFSO46lMfWj++x195zEhUv2awnvfhVxrTOAUO39iyh2VXxlPggVcCD03znJAuQTHy/ CQb3btZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tS6m6-00000004SrR-2a1I; Mon, 30 Dec 2024 03:49:02 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tS6jn-00000004STw-1ybQ; Mon, 30 Dec 2024 03:46:40 +0000 X-UUID: a9ce5574c66011ef9048ed6ed365623b-20241229 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=K2BfXDrGZ7RvRP4Ca4D5lZ3ETGg9zyB/1qmZRsOCQzA=; b=gdrBUr8pyMIJtfU8NbkRJAkzR7EfaGfgw/Eg385LurzBxeDPjfJIBtzKG7q41W+bvKW7qSiJMhk/Wl4jAdClJj+Qld1ENOkpMW5xFq+X5GbokmeqwunsS4LpOFE4xe2awah1+6NLB55HQba1iSLwf93+9MvRqhsapK7rmyKx2kA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:775bed21-d8e6-4134-a384-e724c611c8e7,IP:0,U RL:25,TC:0,Content:100,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,AC TION:release,TS:100 X-CID-META: VersionHash:60aa074,CLOUDID:c88d1537-e11c-4c1a-89f7-e7a032832c40,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|801,TC:nil,Content:3|50,ED M:1,IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OS A:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: a9ce5574c66011ef9048ed6ed365623b-20241229 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1478531017; Sun, 29 Dec 2024 20:46:33 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Dec 2024 11:46:30 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Dec 2024 11:46:30 +0800 From: Karl.Li To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Karl Li CC: , , , , Chungying Lu , Chien-Chih Tseng , Andy Teng , Chen-Yu Tsai , , Karl Li Subject: [PATCH v2 1/3] dt-bindings: mailbox: mediatek: Add apu-mailbox dt-bindings Date: Mon, 30 Dec 2024 11:43:35 +0800 Message-ID: <20241230034446.1195728-2-karl.li@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241230034446.1195728-1-karl.li@mediatek.com> References: <20241230034446.1195728-1-karl.li@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241229_194639_511622_D9FE715D X-CRM114-Status: GOOD ( 13.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Karl Li Add devicetree binding for apu-mailbox. MediaTek APU (AI Processing Unit) is a microcontroller unit designed for AI acceleration tasks. The MediaTek APU-Mailbox facilitates communication with the APU microcontroller. Signed-off-by: Karl Li --- .../mailbox/mediatek,apu-mailbox.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml new file mode 100644 index 000000000000..fdb0dec5fb78 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,apu-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek APU mailbox + +maintainers: + - Karl Li + +description: + MediaTek APU (AI Processing Unit) is a microcontroller unit + designed for AI acceleration tasks. The MediaTek APU-Mailbox + facilitates communication with the APU microcontroller. + Within the MediaTek APU subsystem, a message passing mechanism is + built on top of the mailbox system. The mailbox only has limited + space for each message. The firmware expects the message header + from the mailbox, while the message body is passed through some + fixed shared memory. + +properties: + compatible: + const: mediatek,mt8196-apu-mailbox + + "#mbox-cells": + const: 1 + description: + The cell describe which channel the device will use. + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - "#mbox-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mailbox@4c200000 { + compatible = "mediatek,mt8196-apu-mailbox"; + reg = <0 0x4c200000 0 0xfffff>; + interrupts = ; + #mbox-cells = <1>; + }; + }; From patchwork Mon Dec 30 03:43:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Karl.Li" X-Patchwork-Id: 13923034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AD09E7718F for ; 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Sun, 29 Dec 2024 20:46:36 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Dec 2024 11:46:33 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Dec 2024 11:46:33 +0800 From: Karl.Li To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Karl Li CC: , , , , Chungying Lu , Chien-Chih Tseng , Andy Teng , "Chen-Yu Tsai" , , Karl Li Subject: [PATCH v2 2/3] mailbox: add support for bottom half received data Date: Mon, 30 Dec 2024 11:43:36 +0800 Message-ID: <20241230034446.1195728-3-karl.li@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241230034446.1195728-1-karl.li@mediatek.com> References: <20241230034446.1195728-1-karl.li@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241229_194642_517542_EEB6A9BC X-CRM114-Status: GOOD ( 21.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Karl Li Within the MediaTek APU subsystem, a message passing mechanism is constructed on top of the mailbox system. The mailbox only has limited space for each message. The MTK APU firmware expects the message header from the mailbox, while the message body is passed through some fixed shared memory. The mailbox interrupt also serves as a mutex for the shared memory. Thus the interrupt may only be cleared after the message is handled. To be specific, the MTK APU firmware fills the message body into a fixed shared memory, while passing the message header via a mailbox. --------------- --------------- --------- | Kernel Buffer | <- | Shared Memory | <- | MTK APU | --------------- --------------- --------- The top-half handler first copies the data from the shared memory to the kernel buffer. Subsequently, the bottom-half handler uses the data in the kernel buffer for specific processing tasks. However, it is possible for the MTK APU to send a new message while the kernel is still processing the previous one. In such cases, the top-half handler may overwrite the kernel buffer while the data is still needed, leading to a race condition. Additionally, due to performance considerations, we cannot allocate a new kernel buffer for each message. To prevent this, we need a mechanism to protect the kernel buffer from such race conditions. Since we cannot use locks to protect the kernel buffer in an atomic context, we use the mailbox interrupt as a mutex for the shared memory to further protect our kernel buffer. Therefore, we clear the interrupt only after the message is handled. Since the bottom half callback might need to go to sleep, we require a sleepable callback for mailbox clients. This patch adds a new sleepable RX callback for mailbox clients for cases where handling the incoming message requires sleeping. Signed-off-by: Karl Li --- drivers/mailbox/mailbox.c | 16 ++++++++++++++++ include/linux/mailbox_client.h | 2 ++ include/linux/mailbox_controller.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index d3d26a2c9895..d58a77fcf804 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -164,6 +164,22 @@ void mbox_chan_received_data(struct mbox_chan *chan, void *mssg) } EXPORT_SYMBOL_GPL(mbox_chan_received_data); +/** + * mbox_chan_received_data_bh - A way for controller driver to push data + * received from remote to the upper layer. + * @chan: Pointer to the mailbox channel on which RX happened. + * @mssg: Client specific message typecasted as void * + * + * For the operations which is not atomic can be called from + * mbox_chan_received_data_bh(). + */ +void mbox_chan_received_data_bh(struct mbox_chan *chan, void *mssg) +{ + if (chan->cl->rx_callback_bh) + chan->cl->rx_callback_bh(chan->cl, mssg); +} +EXPORT_SYMBOL_GPL(mbox_chan_received_data_bh); + /** * mbox_chan_txdone - A way for controller driver to notify the * framework that the last TX has completed. diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h index 734694912ef7..2cc6fa4e1bf9 100644 --- a/include/linux/mailbox_client.h +++ b/include/linux/mailbox_client.h @@ -22,6 +22,7 @@ struct mbox_chan; * if the client receives some ACK packet for transmission. * Unused if the controller already has TX_Done/RTR IRQ. * @rx_callback: Atomic callback to provide client the data received + * @rx_callback_bh: Non-atomic callback to provide client the data received * @tx_prepare: Atomic callback to ask client to prepare the payload * before initiating the transmission if required. * @tx_done: Atomic callback to tell client of data transmission @@ -33,6 +34,7 @@ struct mbox_client { bool knows_txdone; void (*rx_callback)(struct mbox_client *cl, void *mssg); + void (*rx_callback_bh)(struct mbox_client *cl, void *mssg); void (*tx_prepare)(struct mbox_client *cl, void *mssg); void (*tx_done)(struct mbox_client *cl, void *mssg, int r); }; diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 6fee33cb52f5..74c6a31cd313 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -130,6 +130,7 @@ struct mbox_chan { int mbox_controller_register(struct mbox_controller *mbox); /* can sleep */ void mbox_controller_unregister(struct mbox_controller *mbox); /* can sleep */ void mbox_chan_received_data(struct mbox_chan *chan, void *data); /* atomic */ +void mbox_chan_received_data_bh(struct mbox_chan *chan, void *data); /* can sleep */ void mbox_chan_txdone(struct mbox_chan *chan, int r); /* atomic */ int devm_mbox_controller_register(struct device *dev, From patchwork Mon Dec 30 03:43:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Karl.Li" X-Patchwork-Id: 13923035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1ECBE77188 for ; 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Sun, 29 Dec 2024 20:46:37 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Dec 2024 11:46:35 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Dec 2024 11:46:35 +0800 From: Karl.Li To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Karl Li CC: , , , , Chungying Lu , Chien-Chih Tseng , Andy Teng , "Chen-Yu Tsai" , , Karl Li Subject: [PATCH v2 3/3] mailbox: mediatek: Add mtk-apu-mailbox driver Date: Mon, 30 Dec 2024 11:43:37 +0800 Message-ID: <20241230034446.1195728-4-karl.li@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241230034446.1195728-1-karl.li@mediatek.com> References: <20241230034446.1195728-1-karl.li@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241229_194643_521329_55ECDDA3 X-CRM114-Status: GOOD ( 24.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Karl Li Add mtk-apu-mailbox driver to support the communication with APU remote microprocessor. Also, the mailbox hardware contains extra spare (scratch) registers that other hardware blocks use to communicate through. Use regmap to provide the such operations. Signed-off-by: Karl Li --- drivers/mailbox/Kconfig | 9 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mtk-apu-mailbox.c | 202 ++++++++++++++++++++++++ include/linux/mailbox/mtk-apu-mailbox.h | 15 ++ 4 files changed, 228 insertions(+) create mode 100644 drivers/mailbox/mtk-apu-mailbox.c create mode 100644 include/linux/mailbox/mtk-apu-mailbox.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 8ecba7fb999e..7cea37e7b9df 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -241,6 +241,15 @@ config MTK_ADSP_MBOX between processors with ADSP. It will place the message to share buffer and will access the ipc control. +config MTK_APU_MBOX + tristate "MediaTek APU Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Say yes here to add support for the MediaTek APU Mailbox + driver. The mailbox implementation provides access from the + application processor to the MediaTek AI Processing Unit. + If unsure say N. + config MTK_CMDQ_MBOX tristate "MediaTek CMDQ Mailbox Support" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 5f4f5b0ce2cc..0b992be69f6f 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -53,6 +53,8 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_MTK_ADSP_MBOX) += mtk-adsp-mailbox.o +obj-$(CONFIG_MTK_APU_MBOX) += mtk-apu-mailbox.o + obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o diff --git a/drivers/mailbox/mtk-apu-mailbox.c b/drivers/mailbox/mtk-apu-mailbox.c new file mode 100644 index 000000000000..44f84cdc9ff4 --- /dev/null +++ b/drivers/mailbox/mtk-apu-mailbox.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_APU_MBOX_INBOX (0x0) +#define MTK_APU_MBOX_OUTBOX (0x20) +#define MTK_APU_MBOX_INBOX_IRQ (0xc0) +#define MTK_APU_MBOX_OUTBOX_IRQ (0xc4) +#define MTK_APU_MBOX_INBOX_IRQ_MASK (0xd0) + +#define MTK_APU_MBOX_SPARE_OFF_START (0x40) +#define MTK_APU_MBOX_SPARE_OFF_END (0xB0) + +struct mtk_apu_mailbox_platdata { + u8 msg_mbox_slots; +}; + +struct mtk_apu_mailbox { + u8 msg_mbox_slots; + struct device *dev; + void __iomem *regs; + struct mbox_controller mbox; + struct mtk_apu_mailbox_msg msgs; +}; + +static inline struct mtk_apu_mailbox *get_mtk_apu_mailbox(struct mbox_controller *mbox) +{ + return container_of(mbox, struct mtk_apu_mailbox, mbox); +} + +static irqreturn_t mtk_apu_mailbox_irq(int irq, void *data) +{ + struct mbox_chan *chan = data; + struct mtk_apu_mailbox *apu_mbox = get_mtk_apu_mailbox(chan->mbox); + struct mbox_chan *link = &apu_mbox->mbox.chans[0]; + u8 data_cnt = fls(readl(apu_mbox->regs + MTK_APU_MBOX_OUTBOX_IRQ)); + + memcpy_fromio(apu_mbox->msgs.data, apu_mbox->regs + MTK_APU_MBOX_OUTBOX, + sizeof(*apu_mbox->msgs.data) * data_cnt); + + mbox_chan_received_data(link, apu_mbox->msgs.data); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t mtk_apu_mailbox_irq_thread(int irq, void *data) +{ + struct mbox_chan *chan = data; + struct mtk_apu_mailbox *apu_mbox = get_mtk_apu_mailbox(chan->mbox); + struct mbox_chan *link = &apu_mbox->mbox.chans[0]; + + mbox_chan_received_data_bh(link, apu_mbox->msgs.data); + writel(readl(apu_mbox->regs + MTK_APU_MBOX_OUTBOX_IRQ), + apu_mbox->regs + MTK_APU_MBOX_OUTBOX_IRQ); + + return IRQ_HANDLED; +} + +static int mtk_apu_mailbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_apu_mailbox *apu_mbox = get_mtk_apu_mailbox(chan->mbox); + struct mtk_apu_mailbox_msg *msg = data; + + if (msg->data_cnt <= 0 || msg->data_cnt > apu_mbox->msg_mbox_slots) { + dev_err(apu_mbox->dev, "%s: invalid data_cnt %d\n", __func__, msg->data_cnt); + return -EINVAL; + } + + /* + * Mask lowest "data_cnt-1" interrupts bits, so the interrupt on the other side + * triggers only after the last data slot is written (sent). + */ + writel(GENMASK(msg->data_cnt - 2, 0), apu_mbox->regs + MTK_APU_MBOX_INBOX_IRQ_MASK); + memcpy_toio(apu_mbox->regs + MTK_APU_MBOX_INBOX, + msg->data, sizeof(*msg->data) * msg->data_cnt); + + return 0; +} + +static bool mtk_apu_mailbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_apu_mailbox *apu_mbox = get_mtk_apu_mailbox(chan->mbox); + + return readl(apu_mbox->regs + MTK_APU_MBOX_INBOX_IRQ) == 0; +} + +static const struct mbox_chan_ops mtk_apu_mailbox_ops = { + .send_data = mtk_apu_mailbox_send_data, + .last_tx_done = mtk_apu_mailbox_last_tx_done, +}; + +static bool mtk_apu_mailbox_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg >= MTK_APU_MBOX_SPARE_OFF_START && reg < MTK_APU_MBOX_SPARE_OFF_END) + return true; + return false; +} + +static const struct regmap_config mtk_apu_mailbox_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x100, + .readable_reg = mtk_apu_mailbox_regmap_accessible_reg, + .writeable_reg = mtk_apu_mailbox_regmap_accessible_reg, +}; + +static int mtk_apu_mailbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct mtk_apu_mailbox_platdata *data; + struct mtk_apu_mailbox *apu_mbox; + struct regmap *regmap; + int irq = -1, ret = 0; + + data = of_device_get_match_data(dev); + + apu_mbox = devm_kzalloc(dev, sizeof(*apu_mbox), GFP_KERNEL); + if (!apu_mbox) + return -ENOMEM; + + apu_mbox->dev = dev; + platform_set_drvdata(pdev, apu_mbox); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + apu_mbox->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(apu_mbox->regs)) + return PTR_ERR(apu_mbox->regs); + + apu_mbox->msg_mbox_slots = data->msg_mbox_slots; + apu_mbox->msgs.data = devm_kcalloc(dev, apu_mbox->msg_mbox_slots, + sizeof(*apu_mbox->msgs.data), GFP_KERNEL); + if (!apu_mbox->msgs.data) + return -ENOMEM; + + apu_mbox->mbox.txdone_irq = false; + apu_mbox->mbox.txdone_poll = true; + apu_mbox->mbox.txpoll_period = 1; + apu_mbox->mbox.ops = &mtk_apu_mailbox_ops; + apu_mbox->mbox.dev = dev; + apu_mbox->mbox.num_chans = 1; + apu_mbox->mbox.chans = devm_kcalloc(dev, apu_mbox->mbox.num_chans, + sizeof(*apu_mbox->mbox.chans), + GFP_KERNEL); + if (!apu_mbox->mbox.chans) + return -ENOMEM; + + ret = devm_mbox_controller_register(dev, &apu_mbox->mbox); + if (ret) + return ret; + + ret = devm_request_threaded_irq(dev, irq, mtk_apu_mailbox_irq, + mtk_apu_mailbox_irq_thread, IRQF_ONESHOT, + dev_name(dev), apu_mbox->mbox.chans); + if (ret) + return dev_err_probe(dev, ret, "Failed to request IRQ\n"); + + regmap = devm_regmap_init_mmio(dev, apu_mbox->regs, &mtk_apu_mailbox_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return 0; +} + +static const struct mtk_apu_mailbox_platdata mt8196_platdata = { + .msg_mbox_slots = 8, +}; + +static const struct of_device_id mtk_apu_mailbox_of_match[] = { + { .compatible = "mediatek,mt8196-apu-mailbox", .data = &mt8196_platdata }, + {} +}; +MODULE_DEVICE_TABLE(of, mtk_apu_mailbox_of_match); + +static struct platform_driver mtk_apu_mailbox_driver = { + .probe = mtk_apu_mailbox_probe, + .driver = { + .name = "mtk-apu-mailbox", + .of_match_table = mtk_apu_mailbox_of_match, + }, +}; +module_platform_driver(mtk_apu_mailbox_driver); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek APU Mailbox Driver"); diff --git a/include/linux/mailbox/mtk-apu-mailbox.h b/include/linux/mailbox/mtk-apu-mailbox.h new file mode 100644 index 000000000000..0afce8848205 --- /dev/null +++ b/include/linux/mailbox/mtk-apu-mailbox.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 MediaTek Inc. + * + */ + +#ifndef __MTK_APU_MAILBOX_H__ +#define __MTK_APU_MAILBOX_H__ + +struct mtk_apu_mailbox_msg { + u8 data_cnt; + u32 *data; +}; + +#endif /* __MTK_APU_MAILBOX_H__ */