From patchwork Wed Jan 1 16:33:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13924240 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 07C391E2603; Wed, 1 Jan 2025 16:39:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735749569; cv=none; b=UtFK4YwiTq7FVxenMgICb0bfi/89wjqxB4IPmcUMtudKdezVHwZCacpg8fub5pM8jP10T3eTqfQfWj093eHV0Vu//emup9pDKQmGqFzC9y6M7Rz3W/5fLh5AMrPbQnaYcICcw1N3QRTurqE+i4NmBL+XrFi6ieo33H/5IS0lIiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735749569; c=relaxed/simple; bh=gG9XneZdmjRsx8/ONF7lfJ3JGEIRv7GSaIB6aw2awh4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sEsS5HOmW0wANvlGEYc7vAISGmyBO6gVShSThkkIrewtD2qntheQ7xukT5dEeiEiNQlWxZmxOGNhug2AwG8OUZWGxpoEsCPz2p1uChEtVtFgsDIQY2gHE90jmWoUqoQmTtGmFO6lFGvFoLMb+M35OQeD1e/XH3fgbDC0kIYRgCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: tlWTTPPgTvKyEufc76xZBg== X-CSE-MsgGUID: KsYQNf/ESXmaDAvRsOf5Jw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Jan 2025 01:34:22 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.21]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 05A664026B1E; Thu, 2 Jan 2025 01:34:06 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com, robh@kernel.org Subject: [PATCH v2 1/4] dt-bindings: soc: renesas: Add RZ/G3E variant SYS bindings Date: Wed, 1 Jan 2025 17:33:41 +0100 Message-ID: <20250101163344.128139-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> References: <20241206212559.192705-1-john.madieu.xa@bp.renesas.com> <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add RZ/G3E (R9A09G047) variant to the existing RZ/V2H System Controller (SYS) binding as both IPs are compatible. Signed-off-by: John Madieu Reviewed-by: Rob Herring (Arm) --- Changes: - v1 -> v2: Do not rely on syscon compatible string anymore Notes: v1: Acked-by: Rob Herring (Arm) v1: Reviewed-by: Geert Uytterhoeven v2: Tags dropped due to small changes in compatible property structure. .../bindings/soc/renesas/renesas,r9a09g057-sys.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml index ebbf0c9109ce..e0f7503a9f35 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -22,7 +22,10 @@ description: | properties: compatible: - const: renesas,r9a09g057-sys + items: + - enum: + - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g057-sys # RZ/V2H reg: maxItems: 1 From patchwork Wed Jan 1 16:33:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13924239 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2AD9F1854; Wed, 1 Jan 2025 16:39:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735749568; cv=none; b=lPO9OEdDkw2pwOo52A6+aphR6nyqmgwY0NOYs0FTYV6aS9/n7u//2hruh2CoabbKxe84h8SiVssxoDpr9MGShtuBdlgLJS/E6NoVnfSjREZ6l2kuJRt53Skh64SbE0iIAMkMtEppm+bmCwMxxatPdvFpUQnkhrWg2C/kr4/p/Kw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735749568; c=relaxed/simple; bh=10lf4L9j2ImlYynPSlLc/iXl8oDcwqivU7ovR+RyJZ0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S36ceZY2FFVy8e1hrW2pVIqrRva92/KigMzIb301rw4zcbGDWBW1dujCHuB3tz9z0sK03tgTc6ofuGoK22nHAlUUvyq+N2REiwyYRinDxYCpNzksopkLVDsOX7q3ahsamt5NDHSJhhqjIltkE99R88hM1pX5a8N2PFcrL79dCRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 10fr/eY/RZ22E8bbk6x7Cg== X-CSE-MsgGUID: K7IuNOELT32c4RN3Whqjig== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Jan 2025 01:34:14 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.21]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 251FD4026C88; Thu, 2 Jan 2025 01:34:10 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com, robh@kernel.org Subject: [PATCH v2 2/4] soc: renesas: rz-sysc: Fix SoC ID string extraction Date: Wed, 1 Jan 2025 17:33:42 +0100 Message-ID: <20250101163344.128139-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> References: <20241206212559.192705-1-john.madieu.xa@bp.renesas.com> <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Fix string length calculation when extracting the SoC ID from the compatible string. Add +1 to the size calculation to ensure proper string termination when copying with strncpy(). This prevents potential string trunctation when processing the device tree compatible string to identify the SoC. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven --- New patch introduced in v2, targetting specific fix. drivers/soc/renesas/rz-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index d34d295831b8..e472fda3995b 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -231,7 +231,7 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat soc_id_start = strchr(match->compatible, ',') + 1; soc_id_end = strchr(match->compatible, '-'); - size = soc_id_end - soc_id_start; + size = soc_id_end - soc_id_start + 1; if (size > 32) size = 32; strscpy(soc_id, soc_id_start, size); From patchwork Wed Jan 1 16:33:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13924241 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 68C4F1E32CF; Wed, 1 Jan 2025 16:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735749570; cv=none; b=LVC7tHtXo05nXe4t6UHImkh1T2wHQeHdf08iD/9yWRVCBqFsoEsmgxTG1r+jAGo87h6pJKll8B7ta+4q7DI8AW0a8LDqZoWucpdr+GaiYiJBhSt8sNu5VOWS8WUjV6OHMDnINFTm+JTHv7KwVsnCOrqdmX4HBisRdXJbRJUem7o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735749570; c=relaxed/simple; bh=AxPUmLAqRQ8Jgxv2ZsnJGki1oskRrnWS1MzcJMEgpYM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fSiyNhYI1FGfUNHQ66uHcFUKRDLCOUH6JdcCfAlrEYuGFqqklaXEg8vsWAgu7ZZmKdAeqy7Kxn78+66xZ63yg4MzXenat3L//7FVet/uot4fUlNVmDzqoL+LDBRudWcvxTPNYoWlVNHWz6Nx4vljXzTvAAh+LxlHQix30UzWymo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: w5xmIJtcSvuJFxxaV38zhg== X-CSE-MsgGUID: 2iuqLZYgSJqCIKf9qqUP0Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Jan 2025 01:34:25 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.21]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 448D14026460; Thu, 2 Jan 2025 01:34:15 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com, robh@kernel.org Subject: [PATCH v2 3/4] soc: renesas: rz-sysc: Add support for RZ/G3E family Date: Wed, 1 Jan 2025 17:33:43 +0100 Message-ID: <20250101163344.128139-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> References: <20241206212559.192705-1-john.madieu.xa@bp.renesas.com> <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add SoC detection support for RZ/G3E SoC. Also add support for detecting the number of cores and ETHOS-U55 NPU and also detect PLL mismatch for SW settings other than 1.7GHz. Signed-off-by: John Madieu --- Changes in v2: - Group bitfields ordered by registers - Rename SoC-specific callback field to 'print_id' - Explicitely select 'MFD_SYSCON' config option - Do not rely on 'syscon'-compatible probing anymore. drivers/soc/renesas/Kconfig | 6 +++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a09g047-sysc.c | 73 ++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.c | 22 ++++++++- drivers/soc/renesas/rz-sysc.h | 6 +++ 5 files changed, 106 insertions(+), 2 deletions(-) create mode 100644 drivers/soc/renesas/r9a09g047-sysc.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index a792a3e915fe..33759f69c37c 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -348,6 +348,7 @@ config ARCH_R9A09G011 config ARCH_R9A09G047 bool "ARM64 Platform support for RZ/G3E" + select SYSC_R9A09G047 help This enables support for the Renesas RZ/G3E SoC variants. @@ -386,9 +387,14 @@ config RST_RCAR config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST + select MFD_SYSCON config SYSC_R9A08G045 bool "Renesas RZ/G3S System controller support" if COMPILE_TEST select SYSC_RZ +config SYSC_R9A09G047 + bool "Renesas RZ/G3E System controller support" if COMPILE_TEST + select SYSC_RZ + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 8cd139b3dd0a..3256706112d9 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o +obj-$(CONFIG_SYSC_R9A09G047) += r9a09g047-sysc.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o diff --git a/drivers/soc/renesas/r9a09g047-sysc.c b/drivers/soc/renesas/r9a09g047-sysc.c new file mode 100644 index 000000000000..3ad6057f9196 --- /dev/null +++ b/drivers/soc/renesas/r9a09g047-sysc.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3E System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_DEVID 0x304 +#define SYS_LSI_DEVID_REV GENMASK(31, 28) +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) +#define SYS_LSI_MODE 0x300 +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_CA55_DIS BIT(8) +#define SYS_LSI_PRR_NPU_DIS BIT(1) +#define SYS_MAX_REG 0x170c + + +static void rzg3e_sysc_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + bool is_quad_core, npu_enabled; + u32 prr_val, mode_val; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check CPU and NPU configuration */ + is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS); + npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS); + + dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n", + is_quad_core ? "Quad" : "Dual", + soc_dev_attr->family, + soc_dev_attr->soc_id, + soc_dev_attr->revision, + npu_enabled ? " with Ethos-U55" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzg3e_sysc_soc_id_init_data __initconst = { + .family = "RZ/G3E", + .id = 0x8679447, + .offset = SYS_LSI_DEVID, + .revision_mask = SYS_LSI_DEVID_REV, + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC, + .print_id = rzg3e_sysc_print_id, +}; + +const struct rz_sysc_init_data rzg3e_sysc_init_data = { + .soc_id_init_data = &rzg3e_sysc_soc_id_init_data, + .max_register_offset = SYS_MAX_REG, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index e472fda3995b..6a33807e925a 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -130,6 +130,10 @@ static bool rz_sysc_writeable_reg(struct device *dev, unsigned int off) struct rz_sysc *sysc = dev_get_drvdata(dev); struct rz_sysc_signal *signal; + /* Fast path if not signal-aware */ + if (!sysc->num_signals) + return true; + /* Any register containing a signal is writeable. */ signal = rz_sysc_off_to_signal(sysc, off, 0); if (signal) @@ -143,6 +147,10 @@ static bool rz_sysc_readable_reg(struct device *dev, unsigned int off) struct rz_sysc *sysc = dev_get_drvdata(dev); struct rz_sysc_signal *signal; + /* Fast path if not signal-aware */ + if (!sysc->num_signals) + return true; + /* Any register containing a signal is readable. */ signal = rz_sysc_off_to_signal(sysc, off, 0); if (signal) @@ -257,8 +265,15 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat return -ENODEV; } - dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family, - soc_dev_attr->soc_id, soc_dev_attr->revision); + /* Try to call SoC-specific device identification */ + if (soc_data->print_id) { + soc_data->print_id(sysc->dev, sysc->base, soc_dev_attr); + } else { + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", + soc_dev_attr->family, + soc_dev_attr->soc_id, + soc_dev_attr->revision); + } soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) @@ -283,6 +298,9 @@ static struct regmap_config rz_sysc_regmap = { static const struct of_device_id rz_sysc_match[] = { #ifdef CONFIG_SYSC_R9A08G045 { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif +#ifdef CONFIG_SYSC_R9A09G047 + { .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sysc_init_data }, #endif { } }; diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index babca9c743c7..2c92b252b40c 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -8,7 +8,9 @@ #ifndef __SOC_RENESAS_RZ_SYSC_H__ #define __SOC_RENESAS_RZ_SYSC_H__ +#include #include +#include #include /** @@ -42,6 +44,7 @@ struct rz_sysc_signal { * @offset: SYSC SoC ID register offset * @revision_mask: SYSC SoC ID revision mask * @specific_id_mask: SYSC SoC ID specific ID mask + * @print_id: SoC-specific extended device identification */ struct rz_sysc_soc_id_init_data { const char * const family; @@ -49,6 +52,8 @@ struct rz_sysc_soc_id_init_data { u32 offset; u32 revision_mask; u32 specific_id_mask; + void (*print_id)(struct device *dev, void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr); }; /** @@ -65,6 +70,7 @@ struct rz_sysc_init_data { u32 max_register_offset; }; +extern const struct rz_sysc_init_data rzg3e_sysc_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; #endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Wed Jan 1 16:33:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13924236 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 04FCD1854; Wed, 1 Jan 2025 16:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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02 Jan 2025 01:34:29 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.21]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 638884026B1F; Thu, 2 Jan 2025 01:34:19 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com, robh@kernel.org Subject: [PATCH v2 4/4] arm64: dts: renesas: r9a09g047: add sys node Date: Wed, 1 Jan 2025 17:33:44 +0100 Message-ID: <20250101163344.128139-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> References: <20241206212559.192705-1-john.madieu.xa@bp.renesas.com> <20250101163344.128139-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add system controller node to RZ/G3E (R9A09G047) SoC DTSI. Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index b73daf43683f..e87521cf9a0b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -162,6 +162,13 @@ cpg: clock-controller@10420000 { #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + ostm0: timer@11800000 { compatible = "renesas,r9a09g047-ostm", "renesas,ostm"; reg = <0x0 0x11800000 0x0 0x1000>;