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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 16:37:06.2832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 774c3abc-88f8-4ec6-35e5-08dd2b4bb1f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8549 From: Rohit Visavalia As per commit a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc"), xlnx_vcu driver code is moved to clock from soc, so moving the dt-binding. Signed-off-by: Rohit Visavalia --- .../devicetree/bindings/{soc/xilinx => clock}/xlnx,vcu.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/{soc/xilinx => clock}/xlnx,vcu.txt (100%) diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/clock/xlnx,vcu.txt similarity index 100% rename from Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt rename to Documentation/devicetree/bindings/clock/xlnx,vcu.txt From patchwork Thu Jan 2 16:36:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Visavalia X-Patchwork-Id: 13924604 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2043.outbound.protection.outlook.com [40.107.220.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 189BE1B07AE; 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Signed-off-by: Rohit Visavalia --- .../devicetree/bindings/clock/xlnx,vcu.txt | 26 --------- .../devicetree/bindings/clock/xlnx,vcu.yaml | 58 +++++++++++++++++++ 2 files changed, 58 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.txt create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.txt b/Documentation/devicetree/bindings/clock/xlnx,vcu.txt deleted file mode 100644 index 2417b13ba468..000000000000 --- a/Documentation/devicetree/bindings/clock/xlnx,vcu.txt +++ /dev/null @@ -1,26 +0,0 @@ -LogicoreIP designed compatible with Xilinx ZYNQ family. -------------------------------------------------------- - -General concept ---------------- - -LogicoreIP design to provide the isolation between processing system -and programmable logic. Also provides the list of register set to configure -the frequency. - -Required properties: -- compatible: shall be one of: - "xlnx,vcu" - "xlnx,vcu-logicoreip-1.0" -- reg : The base offset and size of the VCU_PL_SLCR register space. -- clocks: phandle for aclk and pll_ref clocksource -- clock-names: The identification string, "aclk", is always required for - the axi clock. "pll_ref" is required for pll. -Example: - - xlnx_vcu: vcu@a0040000 { - compatible = "xlnx,vcu-logicoreip-1.0"; - reg = <0x0 0xa0040000 0x0 0x1000>; - clocks = <&si570_1>, <&clkc 71>; - clock-names = "pll_ref", "aclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml new file mode 100644 index 000000000000..bdb14594c40b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: LogicoreIP designed compatible with Xilinx ZYNQ family. + +maintainers: + - Rohit Visavalia + +description: + LogicoreIP design to provide the isolation between processing system + and programmable logic. Also provides the list of register set to configure + the frequency. + +properties: + compatible: + items: + - enum: + - xlnx,vcu + - xlnx,vcu-logicoreip-1.0 + + reg: + description: + The base offset and size of the VCU_PL_SLCR register space. + minItems: 1 + + clocks: + description: List of clock specifiers + items: + - description: pll ref clocksource + - description: aclk + + clock-names: + items: + - const: pll_ref + - const: aclk + +required: + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + fpga { + #address-cells = <2>; + #size-cells = <2>; + xlnx_vcu: vcu@a0040000 { + compatible = "xlnx,vcu-logicoreip-1.0"; + reg = <0x0 0xa0040000 0x0 0x1000>; + clocks = <&si570_1>, <&clkc 71>; + clock-names = "pll_ref", "aclk"; + }; + }; From patchwork Thu Jan 2 16:37:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Visavalia X-Patchwork-Id: 13924607 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2072.outbound.protection.outlook.com [40.107.94.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D4B1AAA1C; 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It is marked as optional as some of the ZynqMP designs are having vcu_reset (reset pin of VCU IP) is driven by proc_sys_reset, proc_sys_reset is another PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by axi_gpio or PS GPIO so there will be no GPIO entry. Signed-off-by: Rohit Visavalia --- Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml index bdb14594c40b..b3061309f8dd 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml @@ -36,6 +36,11 @@ properties: - const: pll_ref - const: aclk + reset-gpios: + description: Optional GPIO used to reset the VCU, if available. Need use this + reset gpio when in design 'vcu_resetn' is driven by gpio. + maxItems: 1 + required: - reg - clocks @@ -52,6 +57,7 @@ examples: xlnx_vcu: vcu@a0040000 { compatible = "xlnx,vcu-logicoreip-1.0"; reg = <0x0 0xa0040000 0x0 0x1000>; + reset-gpios = <&gpio 0x4e GPIO_ACTIVE_HIGH>; clocks = <&si570_1>, <&clkc 71>; clock-names = "pll_ref", "aclk"; };