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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 01/15] net/mlx5: HWS, remove the use of duplicated structs Date: Thu, 2 Jan 2025 20:14:00 +0200 Message-ID: <20250102181415.1477316-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|PH0PR12MB7888:EE_ X-MS-Office365-Filtering-Correlation-Id: 54ef7390-96e0-41a8-8796-08dd2b596647 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: CrxaFAFRNUx+rBuv+WRg69Dh/NCwS4O8Bu8nzixLhtt88EeedDpZgzaeBn1Ef2hE1b8ZaT9AxMZjOEsGcnLLE7YaUa8snL3vTARj+e9Ipu/BSSxYvxcEn4X3zfsUskq08y5CxMEE4cD18JeNPyUK08WVUwiwbpT/c+arPCt6vPoPTiP7X++ucAjded9Ygs06BVwHsA65IPEoSazKHGSo/O6R3BqsNJKNcLy4r3MG/FdHiVaU5g8iKeTwGm6EIvVgZcjXHF3yPoXoLQVz7kJFHxSoGQ5XFEsuG5/E2K1pfS4dKpKIYWEBccwuIek6OmaFkhHe2y3bL4AKx81U313NuNr7BR7UgJVqHQNEAJJGuVUips9LPABQW4CFPDKGXcS1bWJe1ZiXGzuMr9FDaXmuPCn6HMZvVm8VuAuGD5+0cLgtECf4YldK+bPrWAtCXj7CWCpD2c/lbFOeofKOR35ck9Wl8dEU+RLoiIq/rlYCUboOo0co3N3jJTD+8hm7eYrA/DVWRuY3Ka8cY5y7aHywKROBkW8Ej7DbXr9eAiI68ojNwoUanINw6D1Qj4Qhg2Yh/YCa2q1mwmuNQHPRU7gJEyucjoI09KfgutLKlwmwex+jign5Cngj+hZDeEKXV/hFNXmdbImdnluoN0II73VAVY5tIdgjGYN5d5I4wiSKXzrrniQnRVZgybQbS5WI70KkAE1w8q0X3ynTKKMCD5bqsxQE9pRHUlCv/8Wje6l5aVPN3Jtpf6v4BY/MweU/f461nO43FSA4Lsuzygal8uIEW1e0aCILSMqhCy2g1cgjoLzK49osiBakO3RHCKYXBH1IvBbanFDNEoQbXJ4UPFt+xmnI6jDp7NapQQoePl+F8GPLo8mfT4iPZ/epoXaA63KYYdYkx+PTUXAFsedSQPTfgE44k8EDnf8pc70f1zo0Haewb+c+TogG4oA5lhAHPzDfX2r9BWy+AjBou4OY82i0fQcYnUjjVjKeC8Wbj6+QTTvX3qNvJWsoglT4mix0ttwULvyGvWxzb6LKZRGtpfagcWB0ix14PBJP8A4BsrSfUlnI+nAxOMWqVG9dmm0zZJiVVE3xRQJJ8lFvvOIoewK87g50ELm2y/9w4TuSYDNyUVXJwYpaHmM5KS7ccWRvs1EpmLqBshUKszEsQ9pz2YioV4gIPBrePVB3aZcckw4hb1F6RURC6JC1W5P7+NYjDqKOC78CDWFvobZfVl56gDENnYzXPkLS74tbSVK5WzrGyTn+p4uy1Sc2cIzJ0WMLRZubNnob5edCUzQjwO4jpHCYkx0FxYywYCSKrzjTjpSBzjr7MUSPK+RLuhq7JaPdEHwWtFD6d/7ORRiuPFaE9H+eYpdVQYA0DWecOHTk4KDe721gAGmU0axm1y5WlIJKWk2fogmV9g0RWXF3BhTAnknCG8HAN14ph8J20nNBUT51R7ffitRhj1jb5BWi0TW+v8BK9Lcequz59a8oF8zR/ldt22T3f57Pme31vbyTDcsGIwk= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:12.3119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54ef7390-96e0-41a8-8796-08dd2b596647 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7888 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Remove definition in HWS of structs that are already defined in mlx5_ifc.h, and fix the usage of these structs. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/cmd.c | 20 ++++----- .../mellanox/mlx5/core/steering/hws/prm.h | 42 ------------------- 2 files changed, 10 insertions(+), 52 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c index c00c138c3366..13689c0c1a44 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c @@ -622,12 +622,12 @@ int mlx5hws_cmd_arg_create(struct mlx5_core_dev *mdev, u32 pd, u32 *arg_id) { + u32 in[MLX5_ST_SZ_DW(create_modify_header_arg_in)] = {0}; u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; - u32 in[MLX5_ST_SZ_DW(create_arg_in)] = {0}; void *attr; int ret; - attr = MLX5_ADDR_OF(create_arg_in, in, hdr); + attr = MLX5_ADDR_OF(create_modify_header_arg_in, in, hdr); MLX5_SET(general_obj_in_cmd_hdr, attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT); MLX5_SET(general_obj_in_cmd_hdr, @@ -635,8 +635,8 @@ int mlx5hws_cmd_arg_create(struct mlx5_core_dev *mdev, MLX5_SET(general_obj_in_cmd_hdr, attr, op_param.create.log_obj_range, log_obj_range); - attr = MLX5_ADDR_OF(create_arg_in, in, arg); - MLX5_SET(arg, attr, access_pd, pd); + attr = MLX5_ADDR_OF(create_modify_header_arg_in, in, arg); + MLX5_SET(modify_header_arg, attr, access_pd, pd); ret = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); if (ret) { @@ -812,7 +812,7 @@ int mlx5hws_cmd_packet_reformat_create(struct mlx5_core_dev *mdev, struct mlx5hws_cmd_packet_reformat_create_attr *attr, u32 *reformat_id) { - u32 out[MLX5_ST_SZ_DW(alloc_packet_reformat_out)] = {0}; + u32 out[MLX5_ST_SZ_DW(alloc_packet_reformat_context_out)] = {0}; size_t insz, cmd_data_sz, cmd_total_sz; void *prctx; void *pdata; @@ -845,7 +845,7 @@ int mlx5hws_cmd_packet_reformat_create(struct mlx5_core_dev *mdev, goto out; } - *reformat_id = MLX5_GET(alloc_packet_reformat_out, out, packet_reformat_id); + *reformat_id = MLX5_GET(alloc_packet_reformat_context_out, out, packet_reformat_id); out: kfree(in); return ret; @@ -854,13 +854,13 @@ int mlx5hws_cmd_packet_reformat_create(struct mlx5_core_dev *mdev, int mlx5hws_cmd_packet_reformat_destroy(struct mlx5_core_dev *mdev, u32 reformat_id) { - u32 out[MLX5_ST_SZ_DW(dealloc_packet_reformat_out)] = {0}; - u32 in[MLX5_ST_SZ_DW(dealloc_packet_reformat_in)] = {0}; + u32 out[MLX5_ST_SZ_DW(dealloc_packet_reformat_context_out)] = {0}; + u32 in[MLX5_ST_SZ_DW(dealloc_packet_reformat_context_in)] = {0}; int ret; - MLX5_SET(dealloc_packet_reformat_in, in, opcode, + MLX5_SET(dealloc_packet_reformat_context_in, in, opcode, MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT); - MLX5_SET(dealloc_packet_reformat_in, in, + MLX5_SET(dealloc_packet_reformat_context_in, in, packet_reformat_id, reformat_id); ret = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/prm.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/prm.h index de92cecbeb92..271490a51b96 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/prm.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/prm.h @@ -390,11 +390,6 @@ struct mlx5_ifc_definer_bits { u8 match_mask[0x160]; }; -struct mlx5_ifc_arg_bits { - u8 rsvd0[0x88]; - u8 access_pd[0x18]; -}; - struct mlx5_ifc_header_modify_pattern_in_bits { u8 modify_field_select[0x40]; @@ -428,11 +423,6 @@ struct mlx5_ifc_create_definer_in_bits { struct mlx5_ifc_definer_bits definer; }; -struct mlx5_ifc_create_arg_in_bits { - struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; - struct mlx5_ifc_arg_bits arg; -}; - struct mlx5_ifc_create_header_modify_pattern_in_bits { struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; struct mlx5_ifc_header_modify_pattern_in_bits pattern; @@ -479,36 +469,4 @@ enum { MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL = 1, }; -struct mlx5_ifc_alloc_packet_reformat_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - - u8 syndrome[0x20]; - - u8 packet_reformat_id[0x20]; - - u8 reserved_at_60[0x20]; -}; - -struct mlx5_ifc_dealloc_packet_reformat_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - - u8 packet_reformat_id[0x20]; - - u8 reserved_at_60[0x20]; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 02/15] net/mlx5: HWS, remove implementation of unused FW commands Date: Thu, 2 Jan 2025 20:14:01 +0200 Message-ID: <20250102181415.1477316-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|MW4PR12MB7287:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b9a72eb-ef15-4aa9-3577-08dd2b596a8b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: WeafaYGj/LqF0zcxXuhLUuBAicZJOm4BHvKuI26oMIKQiqkPX6t7SxIFnP9vCB+7Nl39GHN/oGq1POh6EgZg3mRNM1I0aX1bJIhdx56NVaQ/ZU439kdTA1fv8T5aOo9PI3GnX68JLOryC7vTwc5eXp5EaxjBJukc5odsk1pLphnPmXkuIDKW2x5sJ9EP9IdjvR3mINcm6GyiGAar/pBNQPkbP4QB/cbJy3/JZRzrb81L+E4Ulvob8rJ9Y0tC7lzpmuo/guGMblABUC3w9U6TojCJ4c1hAZZywnvNE4c7aGsXXVbiaw/asBMJuLuuQaobYxL8CMfM/HV7GJH5TPqb4NNev9Kw/oHMCmXF2rIS7KIJd+Ds7nspkTUORJ4r4krV0fOWY64uq4lbpWoDfXn4gOBz8KNDqOBi71FIkBMv6gKpK90FCtkf6sCSIYnHz5Nm6C0j/CiKGblAauhw05ERsKr+62ZqMB7Tb0KHoE2xuQbtVvFfUmMRnuoCJnQR3dc7ZYKGiN6EAgUW+xWjLRReAg/1Ve4MRGU+Hy8R7/dmLDkvXS9sd6yFlQYG839y3pTnMWg9upYh1BzBFMRCEBmhb84Pm4nU6e7OuF+zh6Ic29pwV41QK0l5IsQiVRH8UVnIJTi+rAvv5eB2kmxDZRnZKyESFnuMy/HaycqVWS1ujzQq4kHLv0hM5Wzz9PP3Gu3aRiFkFg9HTtOxVvm9R2UWBZaSivkPGJx52ZqDDzJuuuEfMqMyeTRKnIWON2L4Pk7OX0/g4HCpIJtRx7blqtmO8qR8l1b1uGEPyNv9IlREjWXnfIcDq1hhyXD6lFoAddone3haZ5Gj3kofoyrGemQhMtQfGs18m/Vb1yHEtzeP4ioEUwVohUan79icxf+i3uofM7JIQB2OJo78BwEhXLh94RJ+qeoa0z1w1M/3nuGrAInRllOM7/FwLwZhkC/NOgQPX1WoU8kpCr+egc5D3dANVJXo9XmjdUGd7x4koW51OAWVgqajXDIyCuZrZSTXYGuXu/oaKHR0Oq8zMwc+dpNSbxN53lnY+5wRfpL4ojIqJ1YBK7oYR0I95L5DlR9sJCXz9otiyud/5Iiu9aq8erB/sFZdpOepnaWCNtjJKh360J6EdkVDRJNK7ofLDvPPp7jCeq3ERK9fnbJDUWlyPam6r2NGFMDj/fDR7HqxNf2UXL0Dypmz7rRo8QPjmwj9ADtHDv09pYV3FV528xIpfZhq2f3sNCGvWVtz93Ky97oTGE5IwDrY7MLuq9/O+GACPHJikWJw4p/A8b6dZSzR5sxTuo6wmlHriJwShnRioZpTn/AzbDEaSx5l84mZ7jtIajH7MOh+mEKR5bwBaK9RQthHyYg8hdjE4DYopRN5SZvfdtMtecnNXZexxjoBOcGfNSnSPoGtIE4jLTpkZ4q8G87xy7zoy6nivVAEsu6bYk/+OvdQvIXXbTQ7D6FDIyW4eFnsXWc4S29RSsYD3hUOX20z9yvo6NIg9yf3Of8K1XpfrY0= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:19.4664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b9a72eb-ef15-4aa9-3577-08dd2b596a8b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7287 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Remove functions that manage alias objects - they are not used. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/cmd.c | 67 ------------------- .../mellanox/mlx5/core/steering/hws/cmd.h | 11 --- 2 files changed, 78 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c index 13689c0c1a44..6fd7747f08ec 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c @@ -889,73 +889,6 @@ int mlx5hws_cmd_sq_modify_rdy(struct mlx5_core_dev *mdev, u32 sqn) return ret; } -int mlx5hws_cmd_allow_other_vhca_access(struct mlx5_core_dev *mdev, - struct mlx5hws_cmd_allow_other_vhca_access_attr *attr) -{ - u32 out[MLX5_ST_SZ_DW(allow_other_vhca_access_out)] = {0}; - u32 in[MLX5_ST_SZ_DW(allow_other_vhca_access_in)] = {0}; - void *key; - int ret; - - MLX5_SET(allow_other_vhca_access_in, - in, opcode, MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS); - MLX5_SET(allow_other_vhca_access_in, - in, object_type_to_be_accessed, attr->obj_type); - MLX5_SET(allow_other_vhca_access_in, - in, object_id_to_be_accessed, attr->obj_id); - - key = MLX5_ADDR_OF(allow_other_vhca_access_in, in, access_key); - memcpy(key, attr->access_key, sizeof(attr->access_key)); - - ret = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); - if (ret) - mlx5_core_err(mdev, "Failed to execute ALLOW_OTHER_VHCA_ACCESS command\n"); - - return ret; -} - -int mlx5hws_cmd_alias_obj_create(struct mlx5_core_dev *mdev, - struct mlx5hws_cmd_alias_obj_create_attr *alias_attr, - u32 *obj_id) -{ - u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; - u32 in[MLX5_ST_SZ_DW(create_alias_obj_in)] = {0}; - void *attr; - void *key; - int ret; - - attr = MLX5_ADDR_OF(create_alias_obj_in, in, hdr); - MLX5_SET(general_obj_in_cmd_hdr, - attr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT); - MLX5_SET(general_obj_in_cmd_hdr, - attr, obj_type, alias_attr->obj_type); - MLX5_SET(general_obj_in_cmd_hdr, attr, op_param.create.alias_object, 1); - - attr = MLX5_ADDR_OF(create_alias_obj_in, in, alias_ctx); - MLX5_SET(alias_context, attr, vhca_id_to_be_accessed, alias_attr->vhca_id); - MLX5_SET(alias_context, attr, object_id_to_be_accessed, alias_attr->obj_id); - - key = MLX5_ADDR_OF(alias_context, attr, access_key); - memcpy(key, alias_attr->access_key, sizeof(alias_attr->access_key)); - - ret = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); - if (ret) { - mlx5_core_err(mdev, "Failed to create ALIAS OBJ\n"); - goto out; - } - - *obj_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); -out: - return ret; -} - -int mlx5hws_cmd_alias_obj_destroy(struct mlx5_core_dev *mdev, - u16 obj_type, - u32 obj_id) -{ - return hws_cmd_general_obj_destroy(mdev, obj_type, obj_id); -} - int mlx5hws_cmd_generate_wqe(struct mlx5_core_dev *mdev, struct mlx5hws_cmd_generate_wqe_attr *attr, struct mlx5_cqe64 *ret_cqe) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h index 434f62b0904e..038f58890785 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h @@ -334,14 +334,6 @@ mlx5hws_cmd_forward_tbl_create(struct mlx5_core_dev *mdev, void mlx5hws_cmd_forward_tbl_destroy(struct mlx5_core_dev *mdev, struct mlx5hws_cmd_forward_tbl *tbl); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Erez Shitrit , Tariq Toukan Subject: [PATCH net-next 03/15] net/mlx5: HWS, denote how refcounts are protected Date: Thu, 2 Jan 2025 20:14:02 +0200 Message-ID: <20250102181415.1477316-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|LV8PR12MB9134:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b2649af-b602-4f6f-3f8a-08dd2b596ea4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: MXTjEiEKt0PZosvdOAZOJ43+rk1FEIzpbMofUeeIegWx9NHwQz65QTpJd08cLtp5Y/QgQkP1anQFXNXX/uDA4yc1Ulw1c0t/FvG0wjd7IydBdn/vcHrTB1njGQCTIQkr0UP66jvo+F5+Ymdv+J9vZmXp1xyDxewGbJD/8dvirOR/Vr4PrL0Klp5+p2ONT4g2CZvHp7K6BZ9r6lK//RxgsDWj31sPkYmz+ZFqRSbfqyze065ujvwvlMzt5rChcQIMD/vnyuaTZLdVXaZ9INcYDyq5WcuroDXZinBBsO5FtkBh+MMmtoJNCktOjR9cP3721abO6VscbaqTNwgcrbXEbZKX9BKqpoRfyyOo6AifQbKNjNOM5xTzzoxUuiGz91jMytyqRdvO8N6DQR3wbxpTUeObTUCu+oBOo8RKVX/MzDbE5BsyfAPa+ufWQF269z1wj3hGpNPJeJtmAF4G0Ds6afUDgFY85eRkzVkCjki0jsirQtNcXg71aonN0tPNclqtOmZJRR0g+UnS6W1F/0yuYx6VFrTCsvKISrubBPxQHHcrv1EXG2u6plWkiSZgu+OUEsoH6q3+O1VKSvTYomyqma2N2QGV7iWAaL/IJu3PKCKARTOCrzsryF08R8tZjVxiyQG4vyn65D6oBwE2+SPrLY9mwYH3XhtqZ5dM+J1gon2Jj1chF4kLX5QI3baAJw5yG9GPulF+dzVNeoXEc+W5hT9BbCDU5W99NPGvjik3VYvKS+vOrynMiktEQqswD2OAchpsjcKPbE4Ur+XMI2Vt34PhqWdGC5sxFp/ykv8hg5FGZkaXg16F2GNEMEbGEHUbJW75o9MGrMffmrR+RYK/UmE4FWJC7dTNQILVp/6Uxgaw3kIr2yDEh65U73Z+2RaZyQ6SIeI5XPkhrobxCWDboAQmtL2vmDBC2X59n3GCPMUdPbYa5B+OGgCvFOOZI4zpRNaK3Pe1ezCPQTDXFyEiYHZVBtOMJNq0K1Wc0tuGJyyD0Pu0K9vAvsW0Ms2Sd7Z4pJC4f/DJwp08mJEyScaqSSTo66NBdHcKXmqu5qWsCIuhMLN/o5zJ9BixlZ8Rw+qdQ6hnkyT+N8f1y17Tf7odcrrI4Ub3FdQ/G9wWSH73a+/waN/XTe0OIgE6ajccZceeg7eEJaGQmCKNq4whnkTatbOr24j7cOD0Lif9Biy3Gd4h8JeC9WtWhbjsufDAwXfVlpCt9nMFFuXChRtIzYcY6jFp5qGp5fMbmq7hbOBIX2rXRBgqdodQqtGxud7UWJPryEPDtpEsLv/CFHqbSqoYxurHrpqV1HCdHMOULrWWXWFm9cBTe4E6ldydp7viwHvTsrk1wo3yKnp+JiZy7nPfDcaiBE0rI54DUzD0eTuz8ihDNGPgcmDwIS5jXktkd5r0ekDf3FueB9XhU13ij5BhBJCgTh7v/nXdDyh5IunphShQec52sbqs03n1ZRTivSKXXr/6D3W/Ee8MYOXIMEWOh5/4VA2nr7malqeWcJmhpKo= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:26.3257 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b2649af-b602-4f6f-3f8a-08dd2b596ea4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9134 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Some HWS structs have refcounts that are just u32. Comment how they are protected and add '__must_hold()' annotation where applicable. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Erez Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h | 2 +- .../net/ethernet/mellanox/mlx5/core/steering/hws/definer.h | 2 +- .../net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h | 2 +- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c | 3 ++- 5 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h index e8f562c31826..4669c9fbcfb2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h @@ -70,12 +70,12 @@ struct mlx5hws_action_default_stc { struct mlx5hws_pool_chunk nop_dw6; struct mlx5hws_pool_chunk nop_dw7; struct mlx5hws_pool_chunk default_hit; - u32 refcount; + u32 refcount; /* protected by context ctrl lock */ }; struct mlx5hws_action_shared_stc { struct mlx5hws_pool_chunk stc_chunk; - u32 refcount; + u32 refcount; /* protected by context ctrl lock */ }; struct mlx5hws_actions_apply_data { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h index 038f58890785..610c63d81ad9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h @@ -63,7 +63,7 @@ struct mlx5hws_cmd_forward_tbl { u8 type; u32 ft_id; u32 fg_id; - u32 refcount; + u32 refcount; /* protected by context ctrl lock */ }; struct mlx5hws_cmd_rtc_create_attr { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h index 9432d5084def..5c1a2086efba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h @@ -785,7 +785,7 @@ struct mlx5hws_definer_cache { struct mlx5hws_definer_cache_item { struct mlx5hws_definer definer; - u32 refcount; + u32 refcount; /* protected by context ctrl lock */ struct list_head list_node; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h index 27ca93385b08..8ddb51980044 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h @@ -31,7 +31,7 @@ struct mlx5hws_pattern_cache_item { u8 *data; u16 num_of_actions; } mh_data; - u32 refcount; + u32 refcount; /* protected by pattern_cache lock */ struct list_head ptrn_list_node; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c index 9576e02d00c3..5b183739d5fd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c @@ -37,6 +37,7 @@ static void hws_table_set_cap_attr(struct mlx5hws_table *tbl, } static int hws_table_up_default_fdb_miss_tbl(struct mlx5hws_table *tbl) +__must_hold(&tbl->ctx->ctrl_lock) { struct mlx5hws_cmd_ft_create_attr ft_attr = {0}; struct mlx5hws_cmd_set_fte_attr fte_attr = {0}; @@ -70,7 +71,6 @@ static int hws_table_up_default_fdb_miss_tbl(struct mlx5hws_table *tbl) return -EINVAL; } - /* ctx->ctrl_lock must be held here */ ctx->common_res[tbl_type].default_miss = default_miss; ctx->common_res[tbl_type].default_miss->refcount++; @@ -79,6 +79,7 @@ static int hws_table_up_default_fdb_miss_tbl(struct mlx5hws_table *tbl) /* Called under ctx->ctrl_lock */ static void hws_table_down_default_fdb_miss_tbl(struct mlx5hws_table *tbl) +__must_hold(&tbl->ctx->ctrl_lock) { struct mlx5hws_cmd_forward_tbl *default_miss; struct mlx5hws_context *ctx = tbl->ctx; From patchwork Thu Jan 2 18:14:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13924762 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2044.outbound.protection.outlook.com [40.107.244.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2E714F9F7 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Erez Shitrit , Tariq Toukan Subject: [PATCH net-next 04/15] net/mlx5: HWS, simplify allocations as we support only FDB Date: Thu, 2 Jan 2025 20:14:03 +0200 Message-ID: <20250102181415.1477316-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E0:EE_|CH0PR12MB8550:EE_ X-MS-Office365-Filtering-Correlation-Id: 199bbce1-6e91-4e25-3b5c-08dd2b597217 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: LmQfQ1PTrvP9OjJmTm0BJNv0ue9MXlo6V5eecaNatFrWA3kPuHbAbSI8wN5K/FUkyp4cf80W8AJMalXL5NmRkdctdX9xYa009NK7GYRsgquKXffwoCmwSUqopCcctqwl8j5UqafNXxydSRPS0HjiPXAVkA8p2EPSu12asvzLJ5H5djTrBCXFoL13F+naPZw0U3b29ceJww4lmUj+Qhd7DYN4pneKsOkYP2M6qSi/2qX9dShtlWMRZMdxFYvJ/9geBYXh3QXb/DNncuD/sptB5jjIZj2gQ/SlYL3OZ/cOpcCDXui1KHRzEZT7W6JB3m1OWShXgrNVj70v3+Z8nw/uSXjMWPfrdeOvD48czwGwp7gu4UYsL0mNHJsQQn0Hdjgg4u4z7ISScEdbfHyF7Y34GQPtNjNVNWGiSBesd2iYOBv6L7kw6s4V/vcBQWFRBl4GbyRjVG9H8pMT1BI+ALK+rWmKstQqhGZcHmIo5/FSev7T2y4Q7qnfp3MHz33h6MOKtleC/q3FSg+cYxE2XuGuAPyPmuG6+/Gi9JlaVCp+rGHpE5+2jCD1AEcoG+CSJ+Ru1bWvAhbkgU43qyy9/BpGoRkihv4Q1zUIEBC+7tFrOMhF645zKOxX+caIJsUESHP0hEFB14F07f8vBudxpijDxAQB40QrCgjOjNYCXyNt/bXow0taRBdZZLOk9ye9odRFswtV7GpFI16w8PLDZ4Yde4VKdxbk+b0kFJPW5dVlVGxprvLxEsGOafZexHKdmy/jqxc2Qh7PpFyCvjvpoewqmTJfKK5AnT0oDk01mLObMrsshOleLkznlUVru9drNc4xYsyQoQTQIEUAi1Krk05hDw8/9qYouq3VbdN2tgiNiDRpFx9v2BkjVyuR352WDESndrL206EVh85NWNhl2FOtwYV6ZEKXtM+ghNEJO4I9yqfjKaGh1M7rPqL1fx7dAm/QDbKYBbocyGixxnbXt4r+z6u6BceuXTvdflFAKNbAWiUM3b/mOfxoyewety8c/zA8Clpsw3qYlopqVKscEgx/dnyzBnPzGBjYARd92lzwb4BoFL6P3MmxCPUEg00OgzZOZcppRUSmBw9J5qdNFNopGycUEbBCt+83N/uDOcVtOUx+Q/rWUKTKX9n7CZjhASbtWFBHg5zB2+j1aYOY4g8IW1vtl5tM1WKXB2u5cJp3cEsIQDIVH1NkmSU7kUF1/BUX5SDNA2B1jAkO5OzQYQAL9J5+WWTt0P96bmDREX98fESexJW335rcQiXGZtF3ScVvglCkKKuWZU1b5NNZ08gltKUncOQHnEtJMohkxKxmFxsyHOJoen8OFPKScz8GEfXIispIhbx4YRQEGqgz21lqSM0EmAnasLSdP3Smb/z+/mBIq1+0Afj4T3VOBmjsXqjn6LE8tNsvbBQLo11MYd/uPZ9VAGVv3cCnAwuYp9FJR1Ln0I4Qvam9NHV147I7a9DQIFEdHET0ymtRznWP6A3voa1UHprgs1NropzvA5xMPAg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:32.0656 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 199bbce1-6e91-4e25-3b5c-08dd2b597217 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8550 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik In pools, STCs and actions: no need to allocate array for various table types, as HWS is used to manage only FDB flow tables. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Erez Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/action.c | 107 +++++++++--------- .../mellanox/mlx5/core/steering/hws/action.h | 2 +- .../mellanox/mlx5/core/steering/hws/cmd.c | 2 +- .../mellanox/mlx5/core/steering/hws/context.c | 29 ++--- .../mellanox/mlx5/core/steering/hws/context.h | 4 +- .../mellanox/mlx5/core/steering/hws/debug.c | 36 +++--- .../mellanox/mlx5/core/steering/hws/matcher.c | 4 +- .../mellanox/mlx5/core/steering/hws/rule.c | 2 +- .../mellanox/mlx5/core/steering/hws/table.c | 13 +-- 9 files changed, 87 insertions(+), 112 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index a897cdc60fdb..67d4f40cbd83 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -11,31 +11,29 @@ /* This is the longest supported action sequence for FDB table: * DECAP, POP_VLAN, MODIFY, CTR, ASO, PUSH_VLAN, MODIFY, ENCAP, Term. */ -static const u32 action_order_arr[MLX5HWS_TABLE_TYPE_MAX][MLX5HWS_ACTION_TYP_MAX] = { - [MLX5HWS_TABLE_TYPE_FDB] = { - BIT(MLX5HWS_ACTION_TYP_REMOVE_HEADER) | - BIT(MLX5HWS_ACTION_TYP_REFORMAT_TNL_L2_TO_L2) | - BIT(MLX5HWS_ACTION_TYP_REFORMAT_TNL_L3_TO_L2), - BIT(MLX5HWS_ACTION_TYP_POP_VLAN), - BIT(MLX5HWS_ACTION_TYP_POP_VLAN), - BIT(MLX5HWS_ACTION_TYP_MODIFY_HDR), - BIT(MLX5HWS_ACTION_TYP_PUSH_VLAN), - BIT(MLX5HWS_ACTION_TYP_PUSH_VLAN), - BIT(MLX5HWS_ACTION_TYP_INSERT_HEADER) | - BIT(MLX5HWS_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | - BIT(MLX5HWS_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), - BIT(MLX5HWS_ACTION_TYP_CTR), - BIT(MLX5HWS_ACTION_TYP_TAG), - BIT(MLX5HWS_ACTION_TYP_ASO_METER), - BIT(MLX5HWS_ACTION_TYP_MODIFY_HDR), - BIT(MLX5HWS_ACTION_TYP_TBL) | - BIT(MLX5HWS_ACTION_TYP_VPORT) | - BIT(MLX5HWS_ACTION_TYP_DROP) | - BIT(MLX5HWS_ACTION_TYP_SAMPLER) | - BIT(MLX5HWS_ACTION_TYP_RANGE) | - BIT(MLX5HWS_ACTION_TYP_DEST_ARRAY), - BIT(MLX5HWS_ACTION_TYP_LAST), - }, +static const u32 action_order_arr[MLX5HWS_ACTION_TYP_MAX] = { + BIT(MLX5HWS_ACTION_TYP_REMOVE_HEADER) | + BIT(MLX5HWS_ACTION_TYP_REFORMAT_TNL_L2_TO_L2) | + BIT(MLX5HWS_ACTION_TYP_REFORMAT_TNL_L3_TO_L2), + BIT(MLX5HWS_ACTION_TYP_POP_VLAN), + BIT(MLX5HWS_ACTION_TYP_POP_VLAN), + BIT(MLX5HWS_ACTION_TYP_MODIFY_HDR), + BIT(MLX5HWS_ACTION_TYP_PUSH_VLAN), + BIT(MLX5HWS_ACTION_TYP_PUSH_VLAN), + BIT(MLX5HWS_ACTION_TYP_INSERT_HEADER) | + BIT(MLX5HWS_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | + BIT(MLX5HWS_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), + BIT(MLX5HWS_ACTION_TYP_CTR), + BIT(MLX5HWS_ACTION_TYP_TAG), + BIT(MLX5HWS_ACTION_TYP_ASO_METER), + BIT(MLX5HWS_ACTION_TYP_MODIFY_HDR), + BIT(MLX5HWS_ACTION_TYP_TBL) | + BIT(MLX5HWS_ACTION_TYP_VPORT) | + BIT(MLX5HWS_ACTION_TYP_DROP) | + BIT(MLX5HWS_ACTION_TYP_SAMPLER) | + BIT(MLX5HWS_ACTION_TYP_RANGE) | + BIT(MLX5HWS_ACTION_TYP_DEST_ARRAY), + BIT(MLX5HWS_ACTION_TYP_LAST), }; static const char * const mlx5hws_action_type_str[] = { @@ -83,8 +81,8 @@ static int hws_action_get_shared_stc_nic(struct mlx5hws_context *ctx, int ret; mutex_lock(&ctx->ctrl_lock); - if (ctx->common_res[tbl_type].shared_stc[stc_type]) { - ctx->common_res[tbl_type].shared_stc[stc_type]->refcount++; + if (ctx->common_res.shared_stc[stc_type]) { + ctx->common_res.shared_stc[stc_type]->refcount++; mutex_unlock(&ctx->ctrl_lock); return 0; } @@ -124,8 +122,8 @@ static int hws_action_get_shared_stc_nic(struct mlx5hws_context *ctx, goto free_shared_stc; } - ctx->common_res[tbl_type].shared_stc[stc_type] = shared_stc; - ctx->common_res[tbl_type].shared_stc[stc_type]->refcount = 1; + ctx->common_res.shared_stc[stc_type] = shared_stc; + ctx->common_res.shared_stc[stc_type]->refcount = 1; mutex_unlock(&ctx->ctrl_lock); @@ -178,16 +176,16 @@ static void hws_action_put_shared_stc(struct mlx5hws_action *action, } mutex_lock(&ctx->ctrl_lock); - if (--ctx->common_res[tbl_type].shared_stc[stc_type]->refcount) { + if (--ctx->common_res.shared_stc[stc_type]->refcount) { mutex_unlock(&ctx->ctrl_lock); return; } - shared_stc = ctx->common_res[tbl_type].shared_stc[stc_type]; + shared_stc = ctx->common_res.shared_stc[stc_type]; mlx5hws_action_free_single_stc(ctx, tbl_type, &shared_stc->stc_chunk); kfree(shared_stc); - ctx->common_res[tbl_type].shared_stc[stc_type] = NULL; + ctx->common_res.shared_stc[stc_type] = NULL; mutex_unlock(&ctx->ctrl_lock); } @@ -206,10 +204,10 @@ bool mlx5hws_action_check_combo(struct mlx5hws_context *ctx, enum mlx5hws_action_type *user_actions, enum mlx5hws_table_type table_type) { - const u32 *order_arr = action_order_arr[table_type]; + const u32 *order_arr = action_order_arr; + bool valid_combo; u8 order_idx = 0; u8 user_idx = 0; - bool valid_combo; if (table_type >= MLX5HWS_TABLE_TYPE_MAX) { mlx5hws_err(ctx, "Invalid table_type %d", table_type); @@ -321,8 +319,8 @@ int mlx5hws_action_alloc_single_stc(struct mlx5hws_context *ctx, __must_hold(&ctx->ctrl_lock) { struct mlx5hws_cmd_stc_modify_attr cleanup_stc_attr = {0}; - struct mlx5hws_pool *stc_pool = ctx->stc_pool[table_type]; struct mlx5hws_cmd_stc_modify_attr fixup_stc_attr = {0}; + struct mlx5hws_pool *stc_pool = ctx->stc_pool; bool use_fixup; u32 obj_0_id; int ret; @@ -387,8 +385,8 @@ void mlx5hws_action_free_single_stc(struct mlx5hws_context *ctx, struct mlx5hws_pool_chunk *stc) __must_hold(&ctx->ctrl_lock) { - struct mlx5hws_pool *stc_pool = ctx->stc_pool[table_type]; struct mlx5hws_cmd_stc_modify_attr stc_attr = {0}; + struct mlx5hws_pool *stc_pool = ctx->stc_pool; u32 obj_id; /* Modify the STC not to point to an object */ @@ -561,7 +559,7 @@ hws_action_create_stcs(struct mlx5hws_action *action, u32 obj_id) if (action->flags & MLX5HWS_ACTION_FLAG_HWS_FDB) { ret = mlx5hws_action_alloc_single_stc(ctx, &stc_attr, MLX5HWS_TABLE_TYPE_FDB, - &action->stc[MLX5HWS_TABLE_TYPE_FDB]); + &action->stc); if (ret) goto out_err; } @@ -585,7 +583,7 @@ hws_action_destroy_stcs(struct mlx5hws_action *action) if (action->flags & MLX5HWS_ACTION_FLAG_HWS_FDB) mlx5hws_action_free_single_stc(ctx, MLX5HWS_TABLE_TYPE_FDB, - &action->stc[MLX5HWS_TABLE_TYPE_FDB]); + &action->stc); mutex_unlock(&ctx->ctrl_lock); } @@ -1639,8 +1637,8 @@ hws_action_create_dest_match_range_table(struct mlx5hws_context *ctx, rtc_attr.table_type = mlx5hws_table_get_res_fw_ft_type(MLX5HWS_TABLE_TYPE_FDB, false); /* STC is a single resource (obj_id), use any STC for the ID */ - stc_pool = ctx->stc_pool[MLX5HWS_TABLE_TYPE_FDB]; - default_stc = ctx->common_res[MLX5HWS_TABLE_TYPE_FDB].default_stc; + stc_pool = ctx->stc_pool; + default_stc = ctx->common_res.default_stc; obj_id = mlx5hws_pool_chunk_get_base_id(stc_pool, &default_stc->default_hit); rtc_attr.stc_base = obj_id; @@ -1731,7 +1729,7 @@ hws_action_create_dest_match_range_fill_table(struct mlx5hws_context *ctx, ste_attr.used_id_rtc_0 = &used_rtc_0_id; ste_attr.used_id_rtc_1 = &used_rtc_1_id; - common_res = &ctx->common_res[MLX5HWS_TABLE_TYPE_FDB]; + common_res = &ctx->common_res; /* init an empty match STE which will always hit */ ste_attr.wqe_ctrl = &wqe_ctrl; @@ -1750,7 +1748,7 @@ hws_action_create_dest_match_range_fill_table(struct mlx5hws_context *ctx, wqe_ctrl.stc_ix[MLX5HWS_ACTION_STC_IDX_CTRL] |= htonl(MLX5HWS_ACTION_STC_IDX_LAST_COMBO2 << 29); wqe_ctrl.stc_ix[MLX5HWS_ACTION_STC_IDX_HIT] = - htonl(hit_ft_action->stc[MLX5HWS_TABLE_TYPE_FDB].offset); + htonl(hit_ft_action->stc.offset); wqe_data_arr = (__force __be32 *)&range_wqe_data; @@ -1843,7 +1841,7 @@ mlx5hws_action_create_dest_match_range(struct mlx5hws_context *ctx, stc_attr.ste_table.match_definer_id = ctx->caps->trivial_match_definer; ret = mlx5hws_action_alloc_single_stc(ctx, &stc_attr, MLX5HWS_TABLE_TYPE_FDB, - &action->stc[MLX5HWS_TABLE_TYPE_FDB]); + &action->stc); if (ret) goto error_unlock; @@ -1970,8 +1968,8 @@ __must_hold(&ctx->ctrl_lock) struct mlx5hws_action_default_stc *default_stc; int ret; - if (ctx->common_res[tbl_type].default_stc) { - ctx->common_res[tbl_type].default_stc->refcount++; + if (ctx->common_res.default_stc) { + ctx->common_res.default_stc->refcount++; return 0; } @@ -2023,8 +2021,8 @@ __must_hold(&ctx->ctrl_lock) goto free_nop_dw7; } - ctx->common_res[tbl_type].default_stc = default_stc; - ctx->common_res[tbl_type].default_stc->refcount++; + ctx->common_res.default_stc = default_stc; + ctx->common_res.default_stc->refcount++; return 0; @@ -2046,9 +2044,7 @@ __must_hold(&ctx->ctrl_lock) { struct mlx5hws_action_default_stc *default_stc; - default_stc = ctx->common_res[tbl_type].default_stc; - - default_stc = ctx->common_res[tbl_type].default_stc; + default_stc = ctx->common_res.default_stc; if (--default_stc->refcount) return; @@ -2058,7 +2054,7 @@ __must_hold(&ctx->ctrl_lock) mlx5hws_action_free_single_stc(ctx, tbl_type, &default_stc->nop_dw5); mlx5hws_action_free_single_stc(ctx, tbl_type, &default_stc->nop_ctr); kfree(default_stc); - ctx->common_res[tbl_type].default_stc = NULL; + ctx->common_res.default_stc = NULL; } static void hws_action_modify_write(struct mlx5hws_send_engine *queue, @@ -2150,8 +2146,7 @@ hws_action_apply_stc(struct mlx5hws_actions_apply_data *apply, { struct mlx5hws_action *action = apply->rule_action[action_idx].action; - apply->wqe_ctrl->stc_ix[stc_idx] = - htonl(action->stc[apply->tbl_type].offset); + apply->wqe_ctrl->stc_ix[stc_idx] = htonl(action->stc.offset); } static void @@ -2181,7 +2176,7 @@ hws_action_setter_modify_header(struct mlx5hws_actions_apply_data *apply, rule_action = &apply->rule_action[setter->idx_double]; action = rule_action->action; - stc_idx = htonl(action->stc[apply->tbl_type].offset); + stc_idx = htonl(action->stc.offset); apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW6] = stc_idx; apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW7] = 0; @@ -2240,7 +2235,7 @@ hws_action_setter_insert_ptr(struct mlx5hws_actions_apply_data *apply, apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW6] = 0; apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] = htonl(arg_idx); - stc_idx = htonl(action->stc[apply->tbl_type].offset); + stc_idx = htonl(action->stc.offset); apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW6] = stc_idx; apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW7] = 0; @@ -2272,7 +2267,7 @@ hws_action_setter_tnl_l3_to_l2(struct mlx5hws_actions_apply_data *apply, apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW6] = 0; apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] = htonl(arg_idx); - stc_idx = htonl(action->stc[apply->tbl_type].offset); + stc_idx = htonl(action->stc.offset); apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW6] = stc_idx; apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW7] = 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h index 4669c9fbcfb2..6d1592c49e0c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h @@ -124,7 +124,7 @@ struct mlx5hws_action { struct mlx5hws_context *ctx; union { struct { - struct mlx5hws_pool_chunk stc[MLX5HWS_TABLE_TYPE_MAX]; + struct mlx5hws_pool_chunk stc; union { struct { u32 pat_id; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c index 6fd7747f08ec..9b71ff80831d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c @@ -359,7 +359,7 @@ void mlx5hws_cmd_set_attr_connect_miss_tbl(struct mlx5hws_context *ctx, ft_attr->type = fw_ft_type; ft_attr->table_miss_action = MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL; - default_miss_tbl = ctx->common_res[type].default_miss->ft_id; + default_miss_tbl = ctx->common_res.default_miss->ft_id; if (!default_miss_tbl) { pr_warn("HWS: no flow table ID for default miss\n"); return; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.c index 4a8928f33bb9..9cda2774fd64 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.c @@ -23,7 +23,6 @@ static int hws_context_pools_init(struct mlx5hws_context *ctx) struct mlx5hws_pool_attr pool_attr = {0}; u8 max_log_sz; int ret; - int i; ret = mlx5hws_pat_init_pattern_cache(&ctx->pattern_cache); if (ret) @@ -39,23 +38,17 @@ static int hws_context_pools_init(struct mlx5hws_context *ctx) max_log_sz = min(MLX5HWS_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max); pool_attr.alloc_log_sz = max(max_log_sz, ctx->caps->stc_alloc_log_gran); - for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++) { - pool_attr.table_type = i; - ctx->stc_pool[i] = mlx5hws_pool_create(ctx, &pool_attr); - if (!ctx->stc_pool[i]) { - mlx5hws_err(ctx, "Failed to allocate STC pool [%d]", i); - ret = -ENOMEM; - goto free_stc_pools; - } + pool_attr.table_type = MLX5HWS_TABLE_TYPE_FDB; + ctx->stc_pool = mlx5hws_pool_create(ctx, &pool_attr); + if (!ctx->stc_pool) { + mlx5hws_err(ctx, "Failed to allocate STC pool\n"); + ret = -ENOMEM; + goto uninit_cache; } return 0; -free_stc_pools: - for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++) - if (ctx->stc_pool[i]) - mlx5hws_pool_destroy(ctx->stc_pool[i]); - +uninit_cache: mlx5hws_definer_uninit_cache(ctx->definer_cache); uninit_pat_cache: mlx5hws_pat_uninit_pattern_cache(ctx->pattern_cache); @@ -64,12 +57,8 @@ static int hws_context_pools_init(struct mlx5hws_context *ctx) static void hws_context_pools_uninit(struct mlx5hws_context *ctx) { - int i; - - for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++) { - if (ctx->stc_pool[i]) - mlx5hws_pool_destroy(ctx->stc_pool[i]); - } + if (ctx->stc_pool) + mlx5hws_pool_destroy(ctx->stc_pool); mlx5hws_definer_uninit_cache(ctx->definer_cache); mlx5hws_pat_uninit_pattern_cache(ctx->pattern_cache); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.h index 1c9cc4fba083..38c3647444ad 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.h @@ -38,8 +38,8 @@ struct mlx5hws_context { struct mlx5_core_dev *mdev; struct mlx5hws_cmd_query_caps *caps; u32 pd_num; - struct mlx5hws_pool *stc_pool[MLX5HWS_TABLE_TYPE_MAX]; - struct mlx5hws_context_common_res common_res[MLX5HWS_TABLE_TYPE_MAX]; + struct mlx5hws_pool *stc_pool; + struct mlx5hws_context_common_res common_res; struct mlx5hws_pattern_cache *pattern_cache; struct mlx5hws_definer_cache *definer_cache; struct mutex ctrl_lock; /* control lock to protect the whole context */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c index 5b200b4bc1a8..60ada3143d60 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c @@ -368,9 +368,10 @@ static int hws_debug_dump_context_info(struct seq_file *f, struct mlx5hws_contex static int hws_debug_dump_context_stc_resource(struct seq_file *f, struct mlx5hws_context *ctx, - u32 tbl_type, struct mlx5hws_pool_resource *resource) { + u32 tbl_type = MLX5HWS_TABLE_TYPE_BASE + MLX5HWS_TABLE_TYPE_FDB; + seq_printf(f, "%d,0x%llx,%u,%u\n", MLX5HWS_DEBUG_RES_TYPE_CONTEXT_STC, HWS_PTR_TO_ID(ctx), @@ -382,31 +383,22 @@ static int hws_debug_dump_context_stc_resource(struct seq_file *f, static int hws_debug_dump_context_stc(struct seq_file *f, struct mlx5hws_context *ctx) { - struct mlx5hws_pool *stc_pool; - u32 table_type; + struct mlx5hws_pool *stc_pool = ctx->stc_pool; int ret; - int i; - - for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++) { - stc_pool = ctx->stc_pool[i]; - table_type = MLX5HWS_TABLE_TYPE_BASE + i; - if (!stc_pool) - continue; + if (!stc_pool) + return 0; - if (stc_pool->resource[0]) { - ret = hws_debug_dump_context_stc_resource(f, ctx, table_type, - stc_pool->resource[0]); - if (ret) - return ret; - } + if (stc_pool->resource[0]) { + ret = hws_debug_dump_context_stc_resource(f, ctx, stc_pool->resource[0]); + if (ret) + return ret; + } - if (i == MLX5HWS_TABLE_TYPE_FDB && stc_pool->mirror_resource[0]) { - ret = hws_debug_dump_context_stc_resource(f, ctx, table_type, - stc_pool->mirror_resource[0]); - if (ret) - return ret; - } + if (stc_pool->mirror_resource[0]) { + ret = hws_debug_dump_context_stc_resource(f, ctx, stc_pool->mirror_resource[0]); + if (ret) + return ret; } return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index 1bb3a6f8c3cd..e40193f30c54 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -318,8 +318,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_matcher *matcher, hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, rtc_type, false); /* STC is a single resource (obj_id), use any STC for the ID */ - stc_pool = ctx->stc_pool[tbl->type]; - default_stc = ctx->common_res[tbl->type].default_stc; + stc_pool = ctx->stc_pool; + default_stc = ctx->common_res.default_stc; obj_id = mlx5hws_pool_chunk_get_base_id(stc_pool, &default_stc->default_hit); rtc_attr.stc_base = obj_id; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c index e20c67a04203..14f6307a1772 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c @@ -315,7 +315,7 @@ static void hws_rule_create_init(struct mlx5hws_rule *rule, /* Init default action apply */ apply->tbl_type = tbl->type; - apply->common_res = &ctx->common_res[tbl->type]; + apply->common_res = &ctx->common_res; apply->jump_to_action_stc = matcher->action_ste[0].stc.offset; apply->require_dep = 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c index 5b183739d5fd..967d67ec10e3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c @@ -49,8 +49,8 @@ __must_hold(&tbl->ctx->ctrl_lock) if (tbl->type != MLX5HWS_TABLE_TYPE_FDB) return 0; - if (ctx->common_res[tbl_type].default_miss) { - ctx->common_res[tbl_type].default_miss->refcount++; + if (ctx->common_res.default_miss) { + ctx->common_res.default_miss->refcount++; return 0; } @@ -71,8 +71,8 @@ __must_hold(&tbl->ctx->ctrl_lock) return -EINVAL; } - ctx->common_res[tbl_type].default_miss = default_miss; - ctx->common_res[tbl_type].default_miss->refcount++; + ctx->common_res.default_miss = default_miss; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 05/15] net/mlx5: HWS, add error message on failure to move rules Date: Thu, 2 Jan 2025 20:14:04 +0200 Message-ID: <20250102181415.1477316-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|PH7PR12MB6659:EE_ X-MS-Office365-Filtering-Correlation-Id: f8bf11b4-f86e-4706-f516-08dd2b597260 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 0r6vgcUE/d/PS5GZWY3Xf5jXg2iLXe2sRGUSaEDaV+GH/32zXsitwgKhVFh6LB9dBUjQc4qrGRyfi58YuL/o2Av2t3JEPY/2sTNSdc5GPqOT7rRsgn+jh0uW8ui1xkjx+aaOx7uOF5PDJ3Pg7ivbItVA8k+qibaWTyO5yiLG60IvtClm5HL3GmoCvZSMz+cuNJ3lISPRHdRaqzVxoqfll0kVNm8TUj5WD1ZfgbybdBjD5VNsBmae7IxH0SpCMbri0yAwQmLI4PupZaZO0FlrrqNHkgNmCILyvyKkZzsTJ8j+6rLBfhf6ng2IR6UmGO95LY+oWkJRMLd2JGYO3yxh+6YPz3Mz73e8ExX/OT6CpZmYlEsbPCte1Kxvmsiy17VXQnJRTdwxhjZCkY1pGXVTvkQLUQQzw1jI9hVqs0zzw39tC6BMhupXA0JDswH0Afab03gR/8tEx3MaOIt1PXFUpJypFwj1El+H2tlQxHiN8wLS5PR3WMVQ+uQ4JEIJ4uLi5l585lPg8CUqsNbRKdHhPgyOpav3ChwA6zu2ngS2w6ZdACH7Kl6a4XwEZMzVQ/3X5Ros7I9L44veI8YErN6TfrqKw7jVgARkk4QZqwBEUocsmVTMUEO9PXAaZkKecEZ9P/Rm0oR2CdkMmgVaNnjyWBR+4kfRS0FzHBlUv1mDJ2GsBFfjk1pQ8RW3Se1llWS6bTslErPWr63DyTSIzsYeom56soxNuyXiJI8YLiD3tl2k4L/sc4qnWbs4kimlsx3nJUbyKxCTrB2tYi54y2BbSeCsxpKv68iwDT4cV+eJgVCPetY0kAJXB1J/Z1Ipff5fgQERukmEQsNikhk/wUR1Ho0jY28z4Dzv71ZSW+Ixl9Hm7G+VOMtAdYBTOI41WPtwX6bOb9k0C1sizFxoPqdn/wJLaH7wFcjvPz6OyDix6dxt4IecOD2nR/1JheX5HRjYOVHJS2v7j4bQbwQ4lxBfEmWG0JDUxOWHnHVZGy/olXDDYmLGfiapYbqyh9XeAmiw9vhuNnxxIAEM4waSTFD2zfjLd7jNW35cGHdF48Ht1WEs9D8h4xquFYhq4LJhEiyxPbubqhs6eioxzGsuM3DfVtlqPpGvwi/1ZdmnWrzelCRivwV/cvyU4k7V1vnuhMbVpKz2Qx4bLkxLT9Is09Qz/E4aNjEjZfm+REC2TMk7DWA/K4t+qszI3W2HxrtU+Tuw5s+H2RcP7w0L6TH2Go5draRdmn03969htc3ayrxZ604NFBbMaAsAlz2aBtOwMTvl5pwbyMi7QVPpmxLLearK0TuSqomtXi/d6IFU5ZZ1S19WNmC2XzL9JsRPnfy6BEuv1+/ibr9EJfyZHp6LSBjByTKkTrIzPtSSRaTWpkgJi4y1/owdzKPopnRkN/5h7gYn9ouIlApeyDZ5wBedghjQGXfdp+EU5I7ip450HlaMOfPIgrUcNOEw6rF07+PqDuKSnc7HY1mZvnD8lXchlQBdH5gIuK/07AP+1nW7FDLmOoc= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:32.6112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8bf11b4-f86e-4706-f516-08dd2b597260 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6659 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Add error message for failure to move rules from old matcher to new one during rehash. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/steering/hws/bwc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index baacf662c0ab..af8ab8750c70 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -615,8 +615,12 @@ static int hws_bwc_matcher_move_all_simple(struct mlx5hws_bwc_matcher *bwc_match ret = hws_bwc_queue_poll(ctx, rule_attr.queue_id, &pending_rules[i], false); - if (unlikely(ret)) + if (unlikely(ret)) { + mlx5hws_err(ctx, + "Moving BWC rule failed during rehash (%d)\n", + ret); goto free_bwc_rules; + } } } } while (!all_done); @@ -629,8 +633,11 @@ static int hws_bwc_matcher_move_all_simple(struct mlx5hws_bwc_matcher *bwc_match mlx5hws_send_engine_flush_queue(&ctx->send_queue[queue_id]); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 06/15] net/mlx5: HWS, change error flow on matcher disconnect Date: Thu, 2 Jan 2025 20:14:05 +0200 Message-ID: <20250102181415.1477316-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|CY5PR12MB6130:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c492ec1-9b7e-49b7-1736-08dd2b597651 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: r/mSB807/tF6bcBWZF6acfxqZpauJ1dcgxOhSLhGBQPtMjIDpw/Fvgbcqgtdyczf1uzhNfXrG1PlFMhD/PIfZ+UgHDmdbzU/Y43hfMu/OYX2qnc8LTPnKQgQ0KdlXLjcVqn3XbzYGTXv8Vz71yDYc3SHm04kIHrkUPPFGFbZaUBs9JYC+Xnpo1JiXLaH5w2RJmoH2p6KjSg3FHhvthYMCMcUEja9aMZ9qWcZMs4O8suhxbwGEaUPbpqxC3/WfpQwm+vs2GNkRhOsKuO6QZbMIAI/zcqf7j9za2fIeovVLJ99c9Y729r2wKA7NuXVSqadqhjHzJVQcODwvQYZOk9rygxE/HpjEk9DfNbKFh4hWBPuYK0R3/tko4Jr00t3IfLsHbO6lTIphNslnRxoRmWNVR9lkY08Y0u8wYB36DTFAcGBAf/D+NjFxEGWygt6FyHAu/2PIRsUzqtgj3ax9836lDhQjnZyCHqCMdCcxYbbmaHTRZWzOvufiATGdKTpWoj+TpKxZC4ibTHRXjC2FcVL/YWULLImZxtCeFVQ4TSq6AqkY1OvWaVaLuBBl22A2AWcYmHaVV4O/grAO+BNiy3jiqq/a1bnlxkqOSytCPU6TaZ/tAOM/YESLQH29QYxooGVOZsBefdir2hj3TXF/Qep0AZpznE1nxkzziDR/yGdvGSziCRH03AyBL/HaSD9rtYgkodIjIEgcXLd1MOtW7Z1xO7fTDLhYXTZCpsVezfWAb4NW/fJ20TCztsjEt2Fdim4d+n2Ui3e6+GOkalbpr4vS1hJJTeOdN5IwQWCcEEdVQoEC+1SLZeOg+W2tEpx1v/H4VRWtsVtL+3SmjZ0DIH+ebQId/4LSt4LZSP+eflNpu6DmBpasqvh4dUMs2Z8yZIn2+uoxVC4WBa1LpO9NoJ1sXBPCwz/K4R3tHzs0dh/BQBFPo7f5I8fJO1Im4yFyIs5E4Dl5hke9+NflqXzOSDnkOjXg1X0DM8scz1fO2CFTJk1DKUAx2KqWG94kG0MI7NMdrD/rnR6rmTjb5rc6hEYHQFeSZQG7Og3qyntVIBnxgoGf7snmF0soP1n2g9F5HoXAPIWyHHIofNnuouAWP/ZB+3x3Is7UoEm3N5Ji5IfWV5KNawyCm8Awr/1N4YrRW1g7cmd1edZKytzmjjtD7RzklQD5lT0pyk0Pplp+udCbcfv52pFURsU8fXmcBNX+iPUd+6/pVlmU3KbPdZKmaqf8z5BWjY0YqQ2bDEcuVb6YalpFNiaC8Nn/7SU0HUW1TVYcjQK5R4EArly4l7174tTrvmPP44PxYZRapJAmII+NjkWLQO6epHoENnq+f8mhtorxzlCdi1jFe6TqQOSxcsj9u0qB6uG72D1UsofU68KFhDkiseV5UEA5sjAsSKCpGNEphhWteobhIPDMs3sojm+dpePGo77cKLvupBTejigqB9e0nMgnhoNZ86XWR22x8vzQL4OGRZFRImDz8MB0MQRyuefAFypUx4yCvZ8hO4Kf8M= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:39.2025 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c492ec1-9b7e-49b7-1736-08dd2b597651 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6130 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Currently, when firmware failure occurs during matcher disconnect flow, the error flow of the function reconnects the matcher back and returns an error, which continues running the calling function and eventually frees the matcher that is being disconnected. This leads to a case where we have a freed matcher on the matchers list, which in turn leads to use-after-free and eventual crash. This patch fixes that by not trying to reconnect the matcher back when some FW command fails during disconnect. Note that we're dealing here with FW error. We can't overcome this problem. This might lead to bad steering state (e.g. wrong connection between matchers), and will also lead to resource leakage, as it is the case with any other error handling during resource destruction. However, the goal here is to allow the driver to continue and not crash the machine with use-after-free error. Signed-off-by: Yevgeny Kliteynik Signed-off-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/matcher.c | 24 +++++++------------ 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index e40193f30c54..fea2a945b0db 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -165,14 +165,14 @@ static int hws_matcher_disconnect(struct mlx5hws_matcher *matcher) next->match_ste.rtc_0_id, next->match_ste.rtc_1_id); if (ret) { - mlx5hws_err(tbl->ctx, "Failed to disconnect matcher\n"); - goto matcher_reconnect; + mlx5hws_err(tbl->ctx, "Fatal error, failed to disconnect matcher\n"); + return ret; } } else { ret = mlx5hws_table_connect_to_miss_table(tbl, tbl->default_miss.miss_tbl); if (ret) { - mlx5hws_err(tbl->ctx, "Failed to disconnect last matcher\n"); - goto matcher_reconnect; + mlx5hws_err(tbl->ctx, "Fatal error, failed to disconnect last matcher\n"); + return ret; } } @@ -180,27 +180,19 @@ static int hws_matcher_disconnect(struct mlx5hws_matcher *matcher) if (prev_ft_id == tbl->ft_id) { ret = mlx5hws_table_update_connected_miss_tables(tbl); if (ret) { - mlx5hws_err(tbl->ctx, "Fatal error, failed to update connected miss table\n"); - goto matcher_reconnect; + mlx5hws_err(tbl->ctx, + "Fatal error, failed to update connected miss table\n"); + return ret; } } ret = mlx5hws_table_ft_set_default_next_ft(tbl, prev_ft_id); if (ret) { mlx5hws_err(tbl->ctx, "Fatal error, failed to restore matcher ft default miss\n"); - goto matcher_reconnect; + return ret; } return 0; - -matcher_reconnect: - if (list_empty(&tbl->matchers_list) || !prev) - list_add(&matcher->list_node, &tbl->matchers_list); - else - /* insert after prev matcher */ - list_add(&matcher->list_node, &prev->list_node); - - return ret; } static void hws_matcher_set_rtc_attr_sz(struct mlx5hws_matcher *matcher, From patchwork Thu Jan 2 18:14:06 2025 Content-Type: text/plain; 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Thu, 2 Jan 2025 10:15:22 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 07/15] net/mlx5: HWS, remove wrong deletion of the miss table list Date: Thu, 2 Jan 2025 20:14:06 +0200 Message-ID: <20250102181415.1477316-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E3:EE_|MN2PR12MB4333:EE_ X-MS-Office365-Filtering-Correlation-Id: cab4fa04-cc20-41cb-1c66-08dd2b5976fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: eSnYOCEY2BPeRhTCMhevr6ajFcJ0xD79p4d8fsXqHKg9I/72bvgYp+9cgp0Ymu0kkOHWTOmydma+Y3IkFJwSRT6cw1V4Rs74PN56nXoTNS0mBE1Pl5+BL79cgyObXKwqcFHhgkc7Gkjbi5ypf5w03ATTtcluLAy8n9cAKnA1pFPb2iUtedS94DRJyU2xe6+UHsPDGf5EawXXMx6ctP1J+0lMtLRSOH8OA69fjdeEbdmIvJ/mUm2RtMoIZ7hkBNOMjxzk9fdTjPhYkrNyD9jW8LiNwVrstSMD39wyTBQn29ZPkISY2O1Ue6WTS1F4eLoLHN734QNm4VoAlFq+3+SR8ZuYEqPw8liUYqw9YKOKTTC90eDglQc2Xo82NXcR8/y/yVtyvTJAeTcfx04sv/jkpaIDiGDwlJL8eeyIFxby6o3srzpGqTyjKHovrewty6afugQlok0oIPzsIegfKucmS3l+/OHeG9ojWeERbTAOEWINPanSBupXhSNHZoIPUNEkAJQWKNbBqACRuyNZl6c0hCmw0kV8hktooJOHWBMIEovrAXPiurRMW+AWUHELmAnhliNoqA5shdHxwoaulIcVcIwtohp8lWOr6ah6TuROHpUR5LJ8mDXDLXd/GG5X9NozCY+45tOjx0EEYDFwTeOQVtQo8B5rKX3VD8VHVUpnGgBqji6kFyIjm+xzCjzNH53jvoBDsI9oHFUBpIjz5T916Ketvr0iYoiRo5zYNjEdrWw77aiMBvxqZNF6TZe/F+/qKbonk8BHjfVn1+jLDG9cziL/uTyVLl1nGXCKdsrbg/AKD5dlhbL5jtViIq/VnBadDPfFAqMNfEPJaQ84gk04Pz+7hbe33HV8RzjsQPhtw9eJdsA7Y0TOU8tfuUoZ4n8F8kY2A113+RGY5RuDepRZV/cVpt4g/xDqsuSHHoCx2FO/ug8uC792OyiKcY68z/xOrJFKb841zi919Bk8QWDz8vslKu2EdflG+MK3PKCOlBGFtkZNdqFXiJhJCmV6PQEe1l2i6OfJtPX1e4miwZSH/rspCLAF3XMgLHm8K9FWit8ccUcOfzvVqIV9w6FmV7kFSwR+N2bsyT76bQP+Iz5I3CcldGtd6hk0gBUKHEdbY/0Fwi9K445aMhdHcv4aSGCz8tjcdSEtveNv9zxxDxPOAxU3ayOTk8eFJCUPnG0vW57cH4utsWwu2CTMo34clam7ik/hZDO3awTPTRCRvXxcXNUVnV7OgN8cyScEIZD/B/eF3MI1woaVf06IahzUg/HaY0hbbfoOXZxUwFxAspa0xP73A8t2JNQHDPReXRmrD6BvCc2x3ICZM+F6URgr0TM7WuKopV5tvfCC7QiszbqNDTWxawFqU8JCODAb/09uaO0v01lcDrXwrjOlP/XXSr6VeblidX+1Jk0PAcHfseJ6vTRi3AwfQigIcSCVFeHMwGTuedyHTDiUG6HZZu13VOA7oWFQRAP3bNNd5MJLnGMLuYYhv9RLLEFHpirUpE8J+bM= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:40.2789 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cab4fa04-cc20-41cb-1c66-08dd2b5976fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4333 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Remove wrong cleanup of the old miss table list and simplify the error flow in the function. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Reviewed-by: Itamar Gozlan Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/steering/hws/table.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c index 967d67ec10e3..ab1297531232 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c @@ -478,15 +478,9 @@ int mlx5hws_table_set_default_miss(struct mlx5hws_table *tbl, if (old_miss_tbl) list_del_init(&tbl->default_miss.next); - old_miss_tbl = tbl->default_miss.miss_tbl; - if (old_miss_tbl) - list_del_init(&old_miss_tbl->default_miss.head); - if (miss_tbl) list_add(&tbl->default_miss.next, &miss_tbl->default_miss.head); - mutex_unlock(&ctx->ctrl_lock); - return 0; out: mutex_unlock(&ctx->ctrl_lock); return ret; From patchwork Thu Jan 2 18:14:07 2025 Content-Type: text/plain; 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Thu, 2 Jan 2025 10:15:26 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Erez Shitrit , Tariq Toukan Subject: [PATCH net-next 08/15] net/mlx5: HWS, reduce memory consumption of a matcher struct Date: Thu, 2 Jan 2025 20:14:07 +0200 Message-ID: <20250102181415.1477316-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013E:EE_|CY8PR12MB7145:EE_ X-MS-Office365-Filtering-Correlation-Id: a5c658e9-508f-4a07-6495-08dd2b597b49 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: 1PlE1E7dRvcXO8HROPNu+7lxPqZnpt2Bf9wfRrJySe/rBGaT66pykR3GIxmD1DwkNY6Wpc3MT/H4yiXvd+B1BxkDMmKZ9KrK1lIjAL1mQdl3kFApC5MNYjSlvlROy227pzl6dN3dHYyhgmMerHAlyiA6aJVQUs6tlxV65rI7qiGMKXc2Q6sua5oXv7gLjcIwANWWqkUaqGPfGfbKeXABzJIWkuAtW87JbWU0IyJ/Squ4uHpVHbkqhPP/HXPjhpWyir0ZhM+RtW1Pl5q1UixNkqgnv21eCRBZ9LTef94KH8LHM3gQvUcNUUT8ucttF7DV8CohSf/WNihWHTD7KI6AQIVRxXlSBkbWaeGONR16QqASc2XzX4LF8if3AA0sTuY68Z/dgTY4ZPamAIQ2PrARkTmMLlNp4n7LvRG8qLXqtw5Mj0+uxEawm4wWVswPfaZaeatcIrNrTqYI80mev5u12z1IU0/8LfnQZIfjwt8fzRqONi6HZra8tp0HEa3zcL1dG18GpCHgJDALe5ub2LFVpB04hfmWO4c8hgRyYx8Osir+qaRlBRN27rl8hSoSKxAtttwnFWuEi9PvwQv0WshpLd3LvXc4Pl5qt6ctEslS/kxPIlYQSxkVrHMSn3veFzxqpHvktXXVh+1/1/msWJAgVKQqznREKg9k83yqBH8hz6cUbpB+GswXp9V6X1VO2G5L5/qFGs+6RMA6IL55Zg5EtLY6U/r6tgoNmFA6KaCB3Z/6HgWEVRPdyv0bkNYFst2i/lQuvxi+6WQsIpcgX/+htPlq87MdDixF/xLqV0l1Zn8AzqBtVKOIe69VvE0lnSR+t9gZUCnP1OA+fejn/tyliRkHim+sbCCUI9U+xlMD0yVBqhccsfDTXlCNFzIKgW0UbbLKXElnijaPNjUS0V5qL/O1o6X8IT2/tsOsNzHaRi1xb4+sa1qrE+WZPEZMUB+JdrRA4L4Rkyql1f4tPpvnNSd9Zq7RK6TPe9L57crtY/bB1UIu7xDEoEpPQwy5v9mmI8OC03izx6gZrrOvlw2WbTSvCrYE4YNso9VjeY20+eSBQ8zpTYCNEuZyX/KwWJO+JUhPRP+/IV0cQLCdZMlr9DbuSpRWBntZzaWi0fWumDTGgkbPZfNT2G0dTQIs2zPgRs/F7vAgJo60J4IbXaok1SMD45j+bImAg9iLJ/TmJb+WfKLOXq41H9w1gNQNy8zPNVkMTNmi9xE1efWTlgLl+P921v1Jelg6ZfytT8SQS3oNyjTWDOKzYX8Jtl7TmELpN/lNcjNJ0HH7Xg8o6/51QZMxOT3tDynSnTb3XdrofwzWdOm0IiXrhjIeI6c+8k5kcuAJlieZgSC7ugLAeAWHrLONUhTfyuCuPtYqI28B6Ap+6++oJqwOKzzxeB2/fS1X1OHyL1gd0JA6z2r67qS7vH7k/GPodBWADsUs/uG1gI8Dd+W0cr0d+/aTyDJb6w+XTzBNvEe7Ftrp267RAldgi+uAyE1ZBIDY3bVRFQ2opCI= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:47.5407 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5c658e9-508f-4a07-6495-08dd2b597b49 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7145 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Instead of having a large array of action templates allocated with kmalloc, have smaller array and allocate it with kvmalloc. The size of the array represents the max number of AT attach operations for the same matcher. This number is not expected to be very high. In any case, when the limit is reached, the next attempt to attach new AT will result in creation of a new matcher and moving all the rules to this matcher. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Erez Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h | 8 +++++++- .../ethernet/mellanox/mlx5/core/steering/hws/matcher.c | 8 ++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h index 3d4965213b01..1d27638fa171 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h @@ -8,7 +8,13 @@ #define MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP 1 #define MLX5HWS_BWC_MATCHER_REHASH_PERCENT_TH 70 #define MLX5HWS_BWC_MATCHER_REHASH_BURST_TH 32 -#define MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM 255 + +/* Max number of AT attach operations for the same matcher. + * When the limit is reached, next attempt to attach new AT + * will result in creation of a new matcher and moving all + * the rules to this matcher. + */ +#define MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM 8 #define MLX5HWS_BWC_MAX_ACTS 16 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index fea2a945b0db..4419c72ad314 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -999,9 +999,9 @@ hws_matcher_set_templates(struct mlx5hws_matcher *matcher, if (!matcher->mt) return -ENOMEM; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Erez Shitrit , Tariq Toukan Subject: [PATCH net-next 09/15] net/mlx5: HWS, num_of_rules counter on matcher should be atomic Date: Thu, 2 Jan 2025 20:14:08 +0200 Message-ID: <20250102181415.1477316-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013E:EE_|CY8PR12MB8265:EE_ X-MS-Office365-Filtering-Correlation-Id: b98f7e72-1947-41a6-109a-08dd2b597d9b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: aVYB4jnkdcbVQKyGFVa3QhMMJYNPB5079iH2J1OZeHsjbACpEzJ1g1kaJJMLNWqk0iUB1JC9FMpC0SH/Np3fPZ7Nabfc27udC1xYepUWxnxyxFz4JYtIBT9OT8GasqN8Suwsvee8mdBKCyOOcwVNIn1T25yMN4TzAesQ5tkigpEsHthllGrJxUFI1+NyOVMhAKqtzAGJxmsi54gtCg04fHtGGzshmtOfmOczWc04XdaYJXqWbdqcBUc3rOANj6nhgzqAIABgeIOCK55FsgmD1t+uhdlizhKYebu18l46Sp9sN2rxNWj6b5IGEOrtzDCQY7v2jHoY+esXjRrEgC4rNXHHX8fOwxodXIso/o5t4NZQ9pnaG0jUDt6NHZCb5I+oP9Ku2eO6ftJqILeUDV8pQLpmszNbmR/uyMfmN1ISwDOBYRvYTqnI0j6yJaomHW6ozZe/Gt2RWqTANctfFwPM3UfK5f+/eZDFbMZovbOnuHtu/XcgBDw8+a+wsIs394l5hpoBxdo/PIlqsGbdbWvIrRJI9XYcj6wBwaxw6gn5o/maTx697aUA+V54X8h76V5cukq7PM3e67KPDJxwN1DpSdYmmUYsUSAND7AiXcHxi1Ct1cCvhLUSQ/+gcUSNlJz2GPi6gbgxNmlU6Cj5eBRwdLSrIJpxneVv3tyO1w/pHvAKJow2FzIpZQ46GrAKCDpnFU6K1EYGhIwspHaJPSgfZnmp/c8foJQxASgLt9R42Ap0kzRe3MAA/PgK6WBDlp4Rlk2wDmvZxwSeVQSjIbSHSxe/jWp/70qYqsNixGOlluPH30MOqBrGdyg9hfxGNvOvLet8jVifSlFJSxagkO27yNKN6bqG93Mxuy1OCW4MBO1ycYRzN1l+1U0FJ3WyhSqY9RYpuK5SRell9q0qZVJgSUcQKaYb3+AWRL76G5bPrFNKqlIjrc+XeolYN5oLaf8ZkElht/N9UEJxFnBIG74wqAUudEkmbr2x5hT5dKXDa8mdquKcxxOlGk4ne43rjil9n4uTPMnfBhepbG7kCHxC9vXItkYFXgcxMR5+1TD7yhpIgG2osZqAgCjqBYEM8IIL6gHfz9yIFQwPcUyUumgecekcb4aQbmBIJB30aez3+7L/2bGB1fRtNdcym5H32XLGvUwviMwOyYq7KR/9zYDrvqmtwLXP/Wv329sWYcx1lr8ipCwqviVwJO+EY+6sO3qXdfQtKbJ3IyUbPsK7+JbrUn/t38uirrHyg45hkTONvZvHGO8fUS7nUu5mubTUdJCXCdr8zZd2/6fiXaqa2KOKU2fIcK/wCiMonl/JNmdoTU8ZEQpHmzjVZUme4/CR/otLivl7faDLTyRwYKK5qa5/tZqPn3GbbnkDui7E85C/yFk9ZNzwrsarAYFRAA4I2vFZn6ik23rmzDRDpBSY5/FQqEcdAwEq4BzGvzflr/+icinqH268/QoV6vOJ4+FD2cdsoqy6So9o+Wv/SYUZFJNVVZdpa6os3li8Lwse5Y5gu1w= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:51.4157 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b98f7e72-1947-41a6-109a-08dd2b597d9b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8265 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Rule counter in matcher's struct is used in two places: 1. As heuristics to decide when the number of rules have crossed a certain percentage threshold and the matcher should be resized. We don't mind here if the number will be off by 1-2 due to concurrency. 2. When destroying matcher, the counter value is checked and the user is warned if it is not 0. Here we lock all the queues, so the counter will be correct. We don't need to always have *exact* number, but we do need this number to not be corrupted, which is what is happening when the counter isn't atomic, due to update by different threads. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Erez Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/bwc.c | 17 +++++++++++------ .../mellanox/mlx5/core/steering/hws/bwc.h | 2 +- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index af8ab8750c70..40d688ed6153 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -152,6 +152,8 @@ mlx5hws_bwc_matcher_create(struct mlx5hws_table *table, if (!bwc_matcher) return NULL; + atomic_set(&bwc_matcher->num_of_rules, 0); + /* Check if the required match params can be all matched * in single STE, otherwise complex matcher is needed. */ @@ -199,10 +201,12 @@ int mlx5hws_bwc_matcher_destroy_simple(struct mlx5hws_bwc_matcher *bwc_matcher) int mlx5hws_bwc_matcher_destroy(struct mlx5hws_bwc_matcher *bwc_matcher) { - if (bwc_matcher->num_of_rules) + u32 num_of_rules = atomic_read(&bwc_matcher->num_of_rules); + + if (num_of_rules) mlx5hws_err(bwc_matcher->matcher->tbl->ctx, "BWC matcher destroy: matcher still has %d rules\n", - bwc_matcher->num_of_rules); + num_of_rules); mlx5hws_bwc_matcher_destroy_simple(bwc_matcher); @@ -309,7 +313,7 @@ static void hws_bwc_rule_list_add(struct mlx5hws_bwc_rule *bwc_rule, u16 idx) { struct mlx5hws_bwc_matcher *bwc_matcher = bwc_rule->bwc_matcher; - bwc_matcher->num_of_rules++; + atomic_inc(&bwc_matcher->num_of_rules); bwc_rule->bwc_queue_idx = idx; list_add(&bwc_rule->list_node, &bwc_matcher->rules[idx]); } @@ -318,7 +322,7 @@ static void hws_bwc_rule_list_remove(struct mlx5hws_bwc_rule *bwc_rule) { struct mlx5hws_bwc_matcher *bwc_matcher = bwc_rule->bwc_matcher; - bwc_matcher->num_of_rules--; + atomic_dec(&bwc_matcher->num_of_rules); list_del_init(&bwc_rule->list_node); } @@ -711,7 +715,8 @@ hws_bwc_matcher_rehash_size(struct mlx5hws_bwc_matcher *bwc_matcher) * Need to check again if we really need rehash. * If the reason for rehash was size, but not any more - skip rehash. */ - if (!hws_bwc_matcher_rehash_size_needed(bwc_matcher, bwc_matcher->num_of_rules)) + if (!hws_bwc_matcher_rehash_size_needed(bwc_matcher, + atomic_read(&bwc_matcher->num_of_rules))) return 0; /* Now we're done all the checking - do the rehash: @@ -804,7 +809,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_rule *bwc_rule, } /* check if number of rules require rehash */ - num_of_rules = bwc_matcher->num_of_rules; + num_of_rules = atomic_read(&bwc_matcher->num_of_rules); if (unlikely(hws_bwc_matcher_rehash_size_needed(bwc_matcher, num_of_rules))) { mutex_unlock(queue_lock); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h index 1d27638fa171..06c2a30c0d4e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h @@ -25,7 +25,7 @@ struct mlx5hws_bwc_matcher { u8 num_of_at; u16 priority; u8 size_log; - u32 num_of_rules; /* atomically accessed */ + atomic_t num_of_rules; struct list_head *rules; }; From patchwork Thu Jan 2 18:14:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13924767 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2089.outbound.protection.outlook.com [40.107.92.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DCDB18C907 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 10/15] net/mlx5: HWS, separate SQ that HWS uses from the usual traffic SQs Date: Thu, 2 Jan 2025 20:14:09 +0200 Message-ID: <20250102181415.1477316-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|BY5PR12MB4180:EE_ X-MS-Office365-Filtering-Correlation-Id: 1eace3bd-f2a6-4b0a-9a01-08dd2b597f40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: NG1BB//LSEB8WPGctVQ3eeFFB9aw36ABoFz7yvYteWKllMS4/qVOQshRn98lilrGOxYRUhuhv9o9ZM7/zO4Jq1OZUfC+PCrCbMFB2KoNsZvKB1ft8CKTZyGGEOsYKPydmdq+1XIgywRlIMmw98DX5LtSeTfzmaC1x2HsiL20sGoE+cmXXmxuaxVMzA/cqlfebCEMx//A6pZiScx72oOTci932R8pHR+u1wiyJF8ft1fJvmjHM5VkB3dbXZKyhIUSbKjRg43zcEOO879OmGttRiVURR48T8KrJ77bXmih7XqSXl5nWUG6MSk3+mQ+7uaHPmRN72LUkP+nxXmUdXw1YOw2SlCwl6uEmZbLmuF3qTLW23E1uPQoLQUCPgFJIe87+KoVN1001vGxaUu5Jyev2NofQmRviKed/+1KwNlS3FGsKpS9Kh9+eyY9p1eXcWG6TWsx0viuB0UVPqxwrAwQ4kmD6pLMecNiujXd8PsM/mczXyguL8VU2KZpTlDk3v6TUJSuDY9QayRdLjd/4kXcqNigGeR+6H2c5hPoqKOdcnqTvU9YBm9xkc70Guu5tEgTWNdwWAWfNXEGwbY+qfE/dxHift/Z+feqckb06mwVwzcQMNRLV+THWYzZuYcjdB+yMZmefMBHQNcHn6MxOPKc3KP7ujYhi/jmIpdhe1uVI8aW13EhemKEEUoIfTPyoyP1VPMGiofzGOEvl+zIV12B/kpVNvvsiFVMtSe/zKpzDmhfRMYyRht3GhiK7G/du7PHBwz21QJnFQiM5SvtW+EG4P4JAFH0DCy2DCkY5xK87mwX2Qs8Bv3znfyYKjD4t/cQkE9m4ZCzCDGQDCMsZinPEbHubjJ+lM6rbnI+hmtAZQy4zqwXqc0tkZNm98nBcrCZzSrXAeZ2C7DjBc4XdJq0a2QzxuPlyIr4etaF6U0LI9g1+B93p6Z2H12aLEOshlfH69oI6ypfGrkl3TbW5CyMZtgxj9SnIzvparh6OYvruWbkWgCULyz+anNs6O8Z5l7AXyp9C3SqNYBJTWNjsASPDrZy3bFNC1MgxI3luMtPzVwVDH+2EI9FRP118qX+8lfpPje2d2W4pRVRn9fhtOJy9Yqon0oq0yp5zArSe1Nvpf3ViAFGV52hfgbHqYCv7aFPlUVUyqBNvVMZ10m2aLjNIWaoEGLsmEVR1sQYRY60ujniaw+2Tvfc9QpInxux8scX1QpqC4wZipeAAigIc1Qm1BU4ByTGkGRG5+TrFdMiCIJcZilkiPXGtQ+H0TAluCYAXVmw3PMD0wPROwJzBPd055Aps6ricfh3o1rFh+552UIPSZ7Y/krUhG0TSLwWgLjbcd/RHH6dZrt/pwwc2jJo6T39JTiLzVW1PvfimlmnujFpzRam8/8urdMvKRap+FnBTYMis81x3nsrwJ7ArmgM6pg+yAumi8tSlqzz/EurSiFE0nvXQaNKLlLvhSd/jb4AwbSHIZxadl7HyDr+vtfx0ltk0Q0PAnAgRCqgD/VXQmk= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:54.1471 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1eace3bd-f2a6-4b0a-9a01-08dd2b597f40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4180 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Mark the HWS SQ as 'non_wire' so that 'Flow Update' flow won't mix with network traffic. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c index 20fe126ffd22..c680b7f984e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c @@ -633,6 +633,7 @@ static int hws_send_ring_create_sq(struct mlx5_core_dev *mdev, u32 pdn, MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); MLX5_SET(sqc, sqc, flush_in_error_en, 1); + MLX5_SET(sqc, sqc, non_wire, 1); ts_format = mlx5_is_real_time_sq(mdev) ? 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Erez Shitrit , Tariq Toukan Subject: [PATCH net-next 11/15] net/mlx5: HWS, fix definer's HWS_SET32 macro for negative offset Date: Thu, 2 Jan 2025 20:14:10 +0200 Message-ID: <20250102181415.1477316-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|CH3PR12MB7499:EE_ X-MS-Office365-Filtering-Correlation-Id: 280d17dc-8bae-448e-57dc-08dd2b598186 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:57.9752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 280d17dc-8bae-448e-57dc-08dd2b598186 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7499 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik When bit offset for HWS_SET32 macro is negative, UBSAN complains about the shift-out-of-bounds: UBSAN: shift-out-of-bounds in drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:177:2 shift exponent -8 is negative Fixes: 74a778b4a63f ("net/mlx5: HWS, added definers handling") Signed-off-by: Yevgeny Kliteynik Reviewed-by: Erez Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c index 8fe96eb76baf..10ece7df1cfa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c @@ -70,7 +70,7 @@ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Tariq Toukan Subject: [PATCH net-next 12/15] net/mlx5: HWS, handle returned error value in pool alloc Date: Thu, 2 Jan 2025 20:14:11 +0200 Message-ID: <20250102181415.1477316-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E0:EE_|PH0PR12MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: ffb06548-6e03-482c-64c5-08dd2b598354 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: jNrw+yvXxbQ/BcSUltHMJuouDadHHi3mXAyGvty9EF207ww28q8QezBbeW7N9YpGeF3++G+ESrdFYvYaCTbY4hepmIInHANZ1/vH8NgQxjKupHxLMSm/bKaUV6bVPIlwTctwza/0Le4yHg3ITowNBiM6GFdDsixAGGa88qTNklHQ1OOMLwhFANBr01qxFBXbBi6eAObKdV34GcBeuB0/0TFw5tCs31FC8Q2P8Ysrpjlvsnhe3wfXipKQSPkk/bPmiOGnCaWgQcf42T38YubDazajTjvbL72XSSglf3tjCujSenKe0RzBeaEcrCtaDW1KzPmzq1e98n9rywszPZzhrid1WR0Nt/5n/7w3+BbLS15vGbokk9QyZAHl4OazQotxV674uqtokSg4sLK1UZ59dQaysqAo11mTIaCbBIz0xHvDYOFOUbTidggdvtd9hog+2JC7vTRp0VKZrpHl32f7zVA1d96AvjKOncOZ2hVa5bhSIEmosBdpWrCOY7czJA5dJAdHj9oWZGdt6/OvhycU/hK9RNgw1Fu5B8mKyBSXBmd1kWTiqRJ7uJIaIOQWoiv73YQDLM7qoFILkhqYfk1qxo/HzeWzPA3Xrgyq2Odhnhw/ThaXAJ4f2MKJIe4PjCS37yQucYE2EvCT/v/hvdzb/illlnetIbJltoUOjU9EKLCOnpXGfJvR8v/ygrOCmikQqwk/h6WCwz3lii1HMU68zTXHEkI/rG+FiRvIe/AFe8I1RAlB0RwITwxrbM6PTpRvGHKsgvZ3P2ENLOPXM97NkpZwPKhQYPJdf+3X4OfDn9iaQJgjjK8MFMIkDRZbWM+ForN9B7Jve3yY52ivmE8Ij1SVf8yqYzWMTKsJnSsKlBWDzJFOxFmqhKa1+gyGan9Drww0bSAyecgvpvgr/WNpYe4GiYnfCupet2KPnEbWmEMkmZGaMo5/kGUGhaN/9tnHb1IHcz7pBJ5KzseWLewC9ZUMv/Xc1Q5DigEDKNfnUB9WHP6FELGy67tbp2tCD/0EMIPnqH0EwQnAtCkQlV8ufATRrYoFXhwK4YTGmXS/0TWXzsERlhaQ04ezzT+enR2cUhzHtJVbupcbbeYy9/dFXTN9+S6haprvdo8iIKWnQKchzrC+HQrkVv946SSA8kbapMU30Vmcr3UpEG/RePYz7ii1ARZ7ldrna2szHarUdItoyqKw5r2/MOIxHUmU4uIy3eub9HQNSc0XFRv5fCMBlvWXSwehL8vm+gFlYPBfYF1bwBNHT5z/TWqXMO3IlBep7OY6X+UjpdUEhmOPrNmUfwhRbIw/Ks2LzlKLrxfxDMXac3hK6Uon4A/0r+Gjn9s5l7Pp17axUnCaA3TeLWuCuEdU1GQMqV1ZD/TJhvRm5z8EyPKmAzCpyuLh8VZkGwhFjAn/XKQyguYiLARZ8UizleCgv6K/HFCPHfUhrL4D2mTDH/lEAK7CiEKaZiulgZx0GnzON2d5LYrxOSTP2ksvKY4dMU1wwFh/yPESUtbvFLg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:16:00.9877 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffb06548-6e03-482c-64c5-08dd2b598354 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8174 X-Patchwork-Delegate: kuba@kernel.org From: Vlad Dogaru Handle all negative return values as errors, not just -1. The code previously treated -ENOMEM (and potentially other negative values) as valid segment numbers, leading to incorrect behavior. This fix ensures that any negative return value is treated as an error. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c index fed2d913f3b8..50a81d360bb2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c @@ -183,7 +183,7 @@ static int hws_pool_buddy_get_mem_chunk(struct mlx5hws_pool *pool, *seg = -1; /* Find the next free place from the buddy array */ - while (*seg == -1) { + while (*seg < 0) { for (i = 0; i < MLX5HWS_POOL_RESOURCE_ARR_SZ; i++) { buddy = hws_pool_buddy_get_next_buddy(pool, i, order, @@ -194,7 +194,7 @@ static int hws_pool_buddy_get_mem_chunk(struct mlx5hws_pool *pool, } *seg = mlx5hws_buddy_alloc_mem(buddy, order); - if (*seg != -1) + if (*seg >= 0) goto found; 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Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index 06db5e4726ae..d9dc4f2d0dc6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -344,7 +344,7 @@ void mlx5hws_arg_write(struct mlx5hws_send_engine *queue, mlx5hws_send_engine_post_req_wqe(&ctrl, (void *)&wqe_ctrl, &wqe_len); memset(wqe_ctrl, 0, wqe_len); mlx5hws_send_engine_post_req_wqe(&ctrl, (void *)&wqe_arg, &wqe_len); - memcpy(wqe_arg, arg_data, wqe_len); + memcpy(wqe_arg, arg_data, MLX5HWS_ARG_DATA_SIZE); send_attr.id = arg_idx++; mlx5hws_send_engine_post_end(&ctrl, &send_attr); From patchwork Thu Jan 2 18:14:13 2025 Content-Type: text/plain; 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Thu, 2 Jan 2025 10:15:51 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Tariq Toukan Subject: [PATCH net-next 14/15] net/mlx5: HWS, support flow sampler destination Date: Thu, 2 Jan 2025 20:14:13 +0200 Message-ID: <20250102181415.1477316-15-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|SN7PR12MB7370:EE_ X-MS-Office365-Filtering-Correlation-Id: d3db3bbb-e39c-4613-b960-08dd2b5989e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: JxJm1U0lGhz0/tP1NGem67tKHK05QpbUaCeSPk9tHDM0rAdJtLP60/cC9DeirRtfLkYtb3bEPKrciSKymms3M7WyUlKJjcp/rFcER78ffD/PJg/ULnGR8FhhZJQPt9D4Vr/3i9BfwIuR57fXBypDAZOTYcXd4POs/lVffE4YeGvP5/CSk9J68NEy2uhYDpWe8F/vrjeQ2zWmdRI3b9MfLW62EA7PpKHd4QG1qbrbtztYjoJMtYdLUj7M2FxPOqFpoJzR7biK45fo+i9b/XHgbe28j6XLXT7IYZoJFXMs2rMaT/AhpnXjWWTDLtj9m88AkFnP9TYo6mODPcIshS3Hm1FZZEbtZU1GuztlGayPly6IOf/KSwAcuZ1XynPQLhXdvbYHWnouZCvJaguNTv6isSaqT9ZwK1sQpLzys+nZ0sCNRu9Zx+xLcruNXx8eSMYoNQMkzyOv5Zovt0i/yNv/Om1H8B7Q+K803uc0Cirj2uH9S33Zz6d/s/1l7OAfbhB3kNC5LkCMeRyt4TdWfPclIWPJXu/YReCWqq1QdPpWbuEq5T/KqtVaFM8INi+lZ4ouWNl/rymeVmileeeoEl2lKcEZgAReaL6zkkpbERwR/D76mfUe0ZUT5uVn5WuSgOv+DOmaHy0BWptCh8kneLpJsC7RIBkxZbxYXc18BlxKIhSJ9AibrvyVPanRetSWuZ9VRlMdujzTKez87LXhb32ho39Aw4LQGSO/+fonhz64pjrs+QyxUxZoR9bBPsbYVscq3epw6KJY1QMfIYprzyQn6kMcWQyZOIjL3rros6wtWcBL84AqaOr+38VKbGZ1P7qKDwXShBrgoZcZkbGVbFO4JeZc+sbkRFTBSzUlhSYtcmp3nQz8R9j/gtbV7AOoswxHfRXHKRwSGVRIFyBMCZYxeAmblqBkrnMaL7WqtzfA6XV4U9Yfhe1BMQvU0dWBhi3tso9EJVuJrCHX8JvMRmn5I41tcBwYeIteEeVLVWeG8X3qjgwgse+nDQFxWFcw78etVp2IUVD4YSe6o0Zj/L7s5MBos29XjCTk+vyE3jJTi4WnKD5vuuEeuflAUkakY4z6EIYfn4GeO36pIKa2bBxtvTR//g33PXhDHfAnq3oBKhRXUo2K4rekd5cKLPV0oNoqcyNG6sCbInNg30m7jm3unYl/SqCie7xITBWxb4+5Uf/CvO1BlqnWODljTYYEy/07VSXIty3s2qt11nPMYDi8SVFscCO1zvzPXsQcoTspmeSbDlrws4kbsbGRKju0CfZ4iPi10Aw21v8rYNwGRGcN71UGM7oiQy4jfYZzJeyka82indo+6olEBVkS6OTSdNON7yxTq4TPOrN0iB/un8Cmt6cf/FRmgSnp5TZec9WuB4mYPQiNxmKBb3fLIyfZk5tlKM121o8ueW9HrzuslHDe1UUEz85GWjlrHCDITMK3RXuYeXXCVAsPhbLpOiW2yYsS+yTscLq3qkWcg/xEl1DVEy6fMHaAGchiB6MjgwfHphQ= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:16:12.0064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3db3bbb-e39c-4613-b960-08dd2b5989e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7370 X-Patchwork-Delegate: kuba@kernel.org From: Vlad Dogaru Since sampler isn't currently supported via HWS, use a FW island that forwards any packets to the supplied sampler. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/action.c | 52 ++++++++++++++++++- .../mellanox/mlx5/core/steering/hws/action.h | 3 ++ .../mellanox/mlx5/core/steering/hws/cmd.c | 6 +++ 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index 67d4f40cbd83..b5332c54d4fb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -471,6 +471,7 @@ static void hws_action_fill_stc_attr(struct mlx5hws_action *action, break; case MLX5HWS_ACTION_TYP_TBL: case MLX5HWS_ACTION_TYP_DEST_ARRAY: + case MLX5HWS_ACTION_TYP_SAMPLER: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT; attr->action_offset = MLX5HWS_ACTION_OFFSET_HIT; attr->dest_table_id = obj_id; @@ -1873,7 +1874,50 @@ struct mlx5hws_action * mlx5hws_action_create_flow_sampler(struct mlx5hws_context *ctx, u32 sampler_id, u32 flags) { - mlx5hws_err(ctx, "Flow sampler action - unsupported\n"); + struct mlx5hws_cmd_ft_create_attr ft_attr = {0}; + struct mlx5hws_cmd_set_fte_attr fte_attr = {0}; + struct mlx5hws_cmd_forward_tbl *fw_island; + struct mlx5hws_cmd_set_fte_dest dest; + struct mlx5hws_action *action; + int ret; + + if (flags != (MLX5HWS_ACTION_FLAG_HWS_FDB | MLX5HWS_ACTION_FLAG_SHARED)) { + mlx5hws_err(ctx, "Unsupported flags for flow sampler\n"); + return NULL; + } + + ft_attr.type = FS_FT_FDB; + ft_attr.level = ctx->caps->fdb_ft.max_level - 1; + + dest.destination_type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER; + dest.destination_id = sampler_id; + + fte_attr.dests_num = 1; + fte_attr.dests = &dest; + fte_attr.action_flags = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + fte_attr.ignore_flow_level = 1; + + fw_island = mlx5hws_cmd_forward_tbl_create(ctx->mdev, &ft_attr, &fte_attr); + if (!fw_island) + return NULL; + + action = hws_action_create_generic(ctx, flags, + MLX5HWS_ACTION_TYP_SAMPLER); + if (!action) + goto destroy_fw_island; + + ret = hws_action_create_stcs(action, fw_island->ft_id); + if (ret) + goto free_action; + + action->flow_sampler.fw_island = fw_island; + + return action; + +free_action: + kfree(action); +destroy_fw_island: + mlx5hws_cmd_forward_tbl_destroy(ctx->mdev, fw_island); return NULL; } @@ -1912,6 +1956,11 @@ static void hws_action_destroy_hws(struct mlx5hws_action *action) } kfree(action->dest_array.dest_list); break; + case MLX5HWS_ACTION_TYP_SAMPLER: + hws_action_destroy_stcs(action); + mlx5hws_cmd_forward_tbl_destroy(action->ctx->mdev, + action->flow_sampler.fw_island); + break; case MLX5HWS_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: case MLX5HWS_ACTION_TYP_MODIFY_HDR: shared_arg = false; @@ -2429,6 +2478,7 @@ int mlx5hws_action_template_process(struct mlx5hws_action_template *at) case MLX5HWS_ACTION_TYP_DROP: case MLX5HWS_ACTION_TYP_TBL: case MLX5HWS_ACTION_TYP_DEST_ARRAY: + case MLX5HWS_ACTION_TYP_SAMPLER: case MLX5HWS_ACTION_TYP_VPORT: case MLX5HWS_ACTION_TYP_MISS: /* Hit action */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h index 6d1592c49e0c..64b76075f7f8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h @@ -165,6 +165,9 @@ struct mlx5hws_action { size_t num_dest; struct mlx5hws_cmd_set_fte_dest *dest_list; } dest_array; + struct { + struct mlx5hws_cmd_forward_tbl *fw_island; + } flow_sampler; struct { u8 type; u8 start_anchor; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c index 9b71ff80831d..487e75476b0a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c @@ -257,6 +257,12 @@ int mlx5hws_cmd_set_fte(struct mlx5_core_dev *mdev, dest->ext_reformat_id); } break; + case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER: + MLX5_SET(dest_format, in_dests, + destination_type, ifc_dest_type); + MLX5_SET(dest_format, in_dests, destination_id, + dest->destination_id); + break; default: ret = -EOPNOTSUPP; goto out; From patchwork Thu Jan 2 18:14:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13924772 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2048.outbound.protection.outlook.com [40.107.101.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 730F516F0E8 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 15/15] net/mlx5: HWS, set timeout on polling for completion Date: Thu, 2 Jan 2025 20:14:14 +0200 Message-ID: <20250102181415.1477316-16-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|PH7PR12MB6393:EE_ X-MS-Office365-Filtering-Correlation-Id: 62dd2745-ed5f-4d03-b57e-08dd2b598be8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: jd8NzyK0sVEbPFEf7xttCTiSJE6043QLnu+WV8C4PTXRe9JkksW2Ev+e3QIzzbB7UVECAEQPTCsXtcAkNt5sLBXdPvVNQfKSNmHZo43jUfA46Ls/kzufE3+SbYU7gX4/OczepN4YhT2K31xf2+TtIWW5t1JqGkZzRV7KxzjGG/f6XedGL8HMZAHlJCj6jf8e3SpOfDp/T5reefnKhnYpz1jGKnPJq9BxzcUDCjCPSx6BfqbbEmWlzQfL9UBkCOpEexniGqjsmjJsVVw6ExTuNKZAZgJlb6iTIdevN+tsVKAgb4GuBJqurydoBpM+h7v2Ni5FzhQ1jJsmE6woJVb8LSzvbBTpWh2iFSBqywu6cs25JmBKts9VOk8yBkXO74py0WqLnfEuLOt2pdquhwoSppHGKg0kyr5lH/nKPlXLlAoZvwLev044Vcg572EZRpn4cNk4sBU5Uj5KD41Q6F88tfaPcer6AB1cp7eReirEyTws7dj42PJ8KQGAhLmLcGXIZpvLQb+wzb3TuhZQuhjrvbW3gnwOIZXGGZihDh6sr8s6BrsljuDats+zNU/4njxUU7U6izOhRKqzBNj7rwik5Gs1SBj4Wn6LOWOs6SXS0Rd2qpNqERd3227k0K5KdjiGBM/76edbjwuohtjlP5OqM5E5eHseSvxVdtNONk08tC/ry8032mEdM0zsiW0eSv2O7AgyKymJbiyfep92yPG0cCvpCk7UQUbdRLuxB4m0pGE/jzuyNE8vZ5No5sQ1TdGGOoPogyLUviktzFor1fNdMUMbK47TW+9/fTVcxrx0pW11qo0ZBensNR7Zh8M2tcvWAgOC7dGQEPq/DyfWo++N+CLGDR0WmgnL/RCfrJHIyaCJLln/KcsvqMTK7QMlrmZHA6uOCO5jzsxRmBBhdnIMcrKJ/q99kHryLrzCRHmRFRzI87HSVgWkRvy7uGaTesjkpO/lNM5C4QIvUMfXTlwxF+0x1JaT2KgaWcd9y/ijMO84KfCgZozdGoe6KUIukCJQClQs1ck0JKC9L89I7WgS2AZIb3ObZe0FUcWBZHyJPRsw/jqztayfxBfaecY+3Qb5+64l/rGhGNFlZklIZf8R7cZ37aL41xnih3s2aEezdkv913TQUvAQ1mDhuSGc2LTtW/1mmWvE7g2zVclL5JfdBFCMjR6boyj6Bbthn7Qhya7ZAt/ErJPMY3LwCdh97MxNozxP1Sr/p8nSdTGWhtHz4w8xbmOaYUkqFBHH23DBq0MWmJev6LhvbJSukyBpHdL2Mj+HT7mUcia55MZ/EaMXXy1KI2pIH9tX1EeYZEdZO0RTxB6sRXnxmVuVVIRvpMzLYgSLD0Bus/9/Md/3rkntckjjxoxnDeyAa3hD77FNaDKt/UsN8NJZSYmpv6bJ0RF+gZTnPd+0um7uo3wTJsrkywCSwaj8BhlkKcODom1KgQxFmh8OAhguEq6WlCNmFZDkmYtgyw1c09DaTBYfLyNKWA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:16:15.3814 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62dd2745-ed5f-4d03-b57e-08dd2b598be8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6393 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik Consolidate BWC polling for completion into one function and set a time limit on the loop that polls for completion. This can happen only if there is some issue with FW/PCI/HW, such as FW being stuck, PCI issue, etc. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/bwc.c | 26 ++++++++++++------- .../mellanox/mlx5/core/steering/hws/bwc.h | 2 ++ 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index 40d688ed6153..a8d886e92144 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -219,6 +219,8 @@ static int hws_bwc_queue_poll(struct mlx5hws_context *ctx, u32 *pending_rules, bool drain) { + unsigned long timeout = jiffies + + msecs_to_jiffies(MLX5HWS_BWC_POLLING_TIMEOUT * MSEC_PER_SEC); struct mlx5hws_flow_op_result comp[MLX5HWS_BWC_MATCHER_REHASH_BURST_TH]; u16 burst_th = hws_bwc_get_burst_th(ctx, queue_id); bool got_comp = *pending_rules >= burst_th; @@ -254,6 +256,11 @@ static int hws_bwc_queue_poll(struct mlx5hws_context *ctx, } got_comp = !!ret; + + if (unlikely(!got_comp && time_after(jiffies, timeout))) { + mlx5hws_err(ctx, "BWC poll error: polling queue %d - TIMEOUT\n", queue_id); + return -ETIMEDOUT; + } } return err; @@ -338,22 +345,21 @@ hws_bwc_rule_destroy_hws_sync(struct mlx5hws_bwc_rule *bwc_rule, struct mlx5hws_rule_attr *rule_attr) { struct mlx5hws_context *ctx = bwc_rule->bwc_matcher->matcher->tbl->ctx; - struct mlx5hws_flow_op_result completion; + u32 expected_completions = 1; int ret; ret = hws_bwc_rule_destroy_hws_async(bwc_rule, rule_attr); if (unlikely(ret)) return ret; - do { - ret = mlx5hws_send_queue_poll(ctx, rule_attr->queue_id, &completion, 1); - } while (ret != 1); - - if (unlikely(completion.status != MLX5HWS_FLOW_OP_SUCCESS || - (bwc_rule->rule->status != MLX5HWS_RULE_STATUS_DELETED && - bwc_rule->rule->status != MLX5HWS_RULE_STATUS_DELETING))) { - mlx5hws_err(ctx, "Failed destroying BWC rule: completion %d, rule status %d\n", - completion.status, bwc_rule->rule->status); + ret = hws_bwc_queue_poll(ctx, rule_attr->queue_id, &expected_completions, true); + if (unlikely(ret)) + return ret; + + if (unlikely(bwc_rule->rule->status != MLX5HWS_RULE_STATUS_DELETED && + bwc_rule->rule->status != MLX5HWS_RULE_STATUS_DELETING)) { + mlx5hws_err(ctx, "Failed destroying BWC rule: rule status %d\n", + bwc_rule->rule->status); return -EINVAL; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h index 06c2a30c0d4e..f9f569131dde 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h @@ -18,6 +18,8 @@ #define MLX5HWS_BWC_MAX_ACTS 16 +#define MLX5HWS_BWC_POLLING_TIMEOUT 60 + struct mlx5hws_bwc_matcher { struct mlx5hws_matcher *matcher; struct mlx5hws_match_template *mt;