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But it may incur TLB conflict abort. We can handle the abort in kernel, however it is hard to guarantee the recuesive TLB conflct will never happen in the handling itself. Some implementations can handle TLB conflict gracefully without fault handler in kernel so FEAT_BBM level 2 can be enabled on those implementations safely. Look up MIDR to filter out those CPUs. AmpereOne is one of them. Suggested-by: Will Deacon Signed-off-by: Yang Shi --- arch/arm64/include/asm/cpufeature.h | 19 +++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 31 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 8b4e5a3cd24c..33ca9db42741 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -866,6 +866,25 @@ static __always_inline bool system_supports_mpam_hcr(void) return alternative_has_cap_unlikely(ARM64_MPAM_HCR); } +static inline bool system_supports_bbmlv2(void) +{ + return cpus_have_final_boot_cap(ARM64_HAS_BBMLV2); +} + +static inline bool bbmlv2_available(void) +{ + static const struct midr_range support_bbmlv2[] = { + MIDR_ALL_VERSIONS(MIDR_AMPERE1), + MIDR_ALL_VERSIONS(MIDR_AMPERE1A), + {} + }; + + if (is_midr_in_range_list(read_cpuid_id(), support_bbmlv2)) + return true; + + return false; +} + int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); bool try_emulate_mrs(struct pt_regs *regs, u32 isn); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6ce71f444ed8..a60d5fa04828 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1889,6 +1889,11 @@ static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) } #endif +static bool has_bbmlv2(const struct arm64_cpu_capabilities *entry, int scope) +{ + return bbmlv2_available(); +} + #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) @@ -2990,6 +2995,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) }, #endif + { + .desc = "BBM Level 2", + .capability = ARM64_HAS_BBMLV2, + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, + .matches = has_bbmlv2, + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index eb17f59e543c..287bdede53f5 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -14,6 +14,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5 HAS_ADDRESS_AUTH_IMP_DEF HAS_AMU_EXTN HAS_ARMv8_4_TTL +HAS_BBMLV2 HAS_CACHE_DIC HAS_CACHE_IDC HAS_CNP From patchwork Fri Jan 3 01:17:10 2025 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: f3H/ZF11cwbBCkeLp1e9bJNHN+bBCkcIUZUWL2epxy0ijxDBIdkiBoYa3O7YOQh19JN0ytbDZUjvhfziQavvST8vhamx9kY/K68CtNfan0z4sBnYDRAk3+WGi+ezYLhupLRJy82J2yRZ+BW4xeRYENLdjnM2lMTCEywuditfRYK0wCxoooe3S5ihkmzpGzV3D31CKYOgvIFs8Y/vnjT55Paxm+zVfjLP4LsGt9sVOXiIVsFT9DLTN45erC0Uj/pyhd9rCDb7Uj5IhddmhfnG1Z0NNEDeXAEiGZea16to4Xz8G06lfPiWZvnYD9jnvUMWIV30XTqo7FimApS1PqRyFgZl+/mLskv6W1rVs4GAGcDdLvJ9G4mcab+4sf95MOHdBSjIGgPsKJgYOB0EJ6M9hBSuNL/rjP+4lZE91VFXHbZNaQXxlDD3yhJtzr7stKI5qwfFt+0cWYDqBx813LZLa48v531ST51EgHIarkf6eHm7yMnQCwR3/mULxzoCWllB6LTMRVXdcVx44T+iqh/2+dEeQC9io9Wje9SR0SE143WMQ1D1Lrn6eMOWNeXbCGlayyFKt7B4uAobwFeGGzsD0aJhhJz5Y1Q2zDdm+oOz94zbr8XMkpl9BM+EEO7Gu1qV9CPm87n1XQ2haZRCHMAbMufPB9KldXocxqS6BhYg9bDUyxEkxuAx+xQRtCFW5CrRylw3/e1QJqH2Wcu4FlRaIej/YtGCVzqmBjEWznJhGrSq7m0UrGqjHXGrfMp9b/qD/vYgbS3c/nIccbjK4rLxj+udpOBKZuva+I5pYv3Yp4hBHlO3Q2izRtDqr1Hd+VoUSIQA6WxTbSmN/dR3LIcc1BYXtoq8QbmGGKn8xitYRZ5za85RQukNf32CCNs+l5IeWLr9NCAI2ekvoeHTLYgMkF5AfqwyXItlUKc4agp1S/gwfk+6wrpU2xxeSQxm5Pa6QHywbZYYqZucCbIbW0o0mK66PJg73a26gNyEj8uxFYN4FfqmyCQ5FOX0koLM8SaQuRE+WmU/rWoXvxdfwAdPn+cn1PN7qLHixggUUcd76QzTQyAAo9syNyHiHCL0TgPNDvL+WMf8322XfRDZ0qImt75ahw9gSRe31xzPPqH7ZLnzal/gF9W30f+hxSchRzk8gDKEjmBLSmlJ0sJJIder0g5fMKW3dddI6dc4PUmto0lNZIStqXSnENMFBkC4k98jfEGlyFmlhlijbLm6x/Y8RRpCzAVLcxdBicQFdb9IztB5YsdoyHlA/0cQPVAMhINmbXeFGLiGTqZ4+/55O9qc7zQIXI12Q99Ye2flV3E4/u36D/Z2Z6cy1/A7vOYJeHX/X8NDnaEpcYakt5yFp7kJ8675O1DVIovt1lPwcmE1rKy2eBAI2LwK4Km8ndFn/Ys48ti+nuK3b2+PC4MFzPTT+qD818VNy27G38Pilyq0PAHr7pnJwBitOmuh8+c4bKbzwFfCWEOweIMXQxFSZqlI64ScMpqQ7xXbS2bY3Vn3/B3Qo+k2Q59DTds2qNR/sqbNwyHzB5iuYVGqqvayZyA+4zsewY4eMuzvi8LJY2NE6uUOCg54PUqSHBjubjSEBv9fdfNESne1NUZcIBHjv2Ra2cn01Zy9fCDaFsBpDjL/mTA= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 279f35a2-e833-44d6-8ef0-08dd2b9490d2 X-MS-Exchange-CrossTenant-AuthSource: CH0PR01MB6873.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2025 01:18:44.2637 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dKiN/15qmqvTrp5bwukHuJeHDyAeoSzlCxIroVVNi1jhJqawccGZKOBUmMOsUZstL+a4k7UHCO05Cye9fK4JfvZqAkikqBahNLKvrbjjgSg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR01MB6164 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250102_171901_711928_26A6E4D1 X-CRM114-Status: GOOD ( 22.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When rodata=full is specified, kernel linear mapping has to be mapped at PTE level since large page table can't be split due to break-before-make rule on ARM64. This resulted in a couple of problems: - performance degradation - more TLB pressure - memory waste for kernel page table With FEAT_BBM level 2 support, splitting large block page table to smaller ones doesn't need to make the page table entry invalid anymore. This allows kernel split large block mapping on the fly. Add kernel page table split support and use large block mapping by default when FEAT_BBM level 2 is supported for rodata=full. When changing permissions for kernel linear mapping, the page table will be split to PTE level. The machine without FEAT_BBM level 2 will fallback to have kernel linear mapping PTE-mapped when rodata=full. With this we saw significant performance boost with some benchmarks and much less memory consumption on my AmpereOne machine (192 cores, 1P) with 256GB memory. * Memory use after boot Before: MemTotal: 258988984 kB MemFree: 254821700 kB After: MemTotal: 259505132 kB MemFree: 255410264 kB Around 500MB more memory are free to use. The larger the machine, the more memory saved. * Memcached We saw performance degradation when running Memcached benchmark with rodata=full vs rodata=on. Our profiling pointed to kernel TLB pressure. With this patchset we saw ops/sec is increased by around 3.5%, P99 latency is reduced by around 9.6%. The gain mainly came from reduced kernel TLB misses. The kernel TLB MPKI is reduced by 28.5%. The benchmark data is now on par with rodata=on too. * Disk encryption (dm-crypt) benchmark Ran fio benchmark with the below command on a 128G ramdisk (ext4) with disk encryption (by dm-crypt). fio --directory=/data --random_generator=lfsr --norandommap --randrepeat 1 \ --status-interval=999 --rw=write --bs=4k --loops=1 --ioengine=sync \ --iodepth=1 --numjobs=1 --fsync_on_close=1 --group_reporting --thread \ --name=iops-test-job --eta-newline=1 --size 100G The IOPS is increased by 90% - 150% (the variance is high, but the worst number of good case is around 90% more than the best number of bad case). The bandwidth is increased and the avg clat is reduced proportionally. * Sequential file read Read 100G file sequentially on XFS (xfs_io read with page cache populated). The bandwidth is increased by 150%. Keep using PTE mapping when pagealloc debug is enabled. It is not worth the complexity. Kfence can be converted to use page block mapping later. Signed-off-by: Yang Shi --- arch/arm64/include/asm/pgtable.h | 7 +- arch/arm64/mm/mmu.c | 32 +++++- arch/arm64/mm/pageattr.c | 173 +++++++++++++++++++++++++++++-- 3 files changed, 203 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 6986345b537a..2927f59ae9e2 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -749,7 +749,7 @@ static inline bool in_swapper_pgdir(void *addr) ((unsigned long)swapper_pg_dir & PAGE_MASK); } -static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) +static inline void __set_pmd_nosync(pmd_t *pmdp, pmd_t pmd) { #ifdef __PAGETABLE_PMD_FOLDED if (in_swapper_pgdir(pmdp)) { @@ -759,6 +759,11 @@ static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) #endif /* __PAGETABLE_PMD_FOLDED */ WRITE_ONCE(*pmdp, pmd); +} + +static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) +{ + __set_pmd_nosync(pmdp, pmd); if (pmd_valid(pmd)) { dsb(ishst); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index e2739b69e11b..65b5b1ba48a7 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -620,6 +620,19 @@ static inline void arm64_kfence_map_pool(phys_addr_t kfence_pool, pgd_t *pgdp) { #endif /* CONFIG_KFENCE */ +static inline bool force_pte_mapping(void) +{ + /* + * Can't use cpufeature API to determine whether BBM level 2 + * is supported or not since cpufeature have not been + * finalized yet. + */ + return (rodata_full && !bbmlv2_available()) || + debug_pagealloc_enabled() || + arm64_kfence_can_set_direct_map() || + is_realm_world(); +} + static void __init map_mem(pgd_t *pgdp) { static const u64 direct_map_end = _PAGE_END(VA_BITS_MIN); @@ -645,9 +658,21 @@ static void __init map_mem(pgd_t *pgdp) early_kfence_pool = arm64_kfence_alloc_pool(); - if (can_set_direct_map()) + if (force_pte_mapping()) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; + /* + * With FEAT_BBM level 2 we can split large block mapping without + * making it invalid. So kernel linear mapping can be mapped with + * large block instead of PTE level. + * + * Need to break cont for CONT_MAPPINGS when changing permission, + * and need to inspect the adjacent page table entries to make + * them cont again later. It sounds not worth the complexity. + */ + if (rodata_full) + flags |= NO_CONT_MAPPINGS; + /* * Take care not to create a writable alias for the * read-only text and rodata sections of the kernel image. @@ -1342,9 +1367,12 @@ int arch_add_memory(int nid, u64 start, u64 size, VM_BUG_ON(!mhp_range_allowed(start, size, true)); - if (can_set_direct_map()) + if (force_pte_mapping()) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; + if (rodata_full) + flags |= NO_CONT_MAPPINGS; + __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), size, params->pgprot, __pgd_pgtable_alloc, flags); diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 39fd1f7ff02a..ba2360ecb030 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -49,6 +49,145 @@ static int change_page_range(pte_t *ptep, unsigned long addr, void *data) return 0; } +static int __split_linear_mapping_pmd(pud_t *pudp, + unsigned long vaddr, unsigned long end) +{ + pmd_t *pmdp; + unsigned long next; + + pmdp = pmd_offset(pudp, vaddr); + + do { + next = pmd_addr_end(vaddr, end); + + if (pmd_leaf(pmdp_get(pmdp))) { + struct page *pte_page; + unsigned long pfn = pmd_pfn(pmdp_get(pmdp)); + pgprot_t prot = pmd_pgprot(pmdp_get(pmdp)); + pte_t *ptep_new; + int i; + + pte_page = alloc_page(GFP_KERNEL); + if (!pte_page) + return -ENOMEM; + + prot = __pgprot(pgprot_val(prot) | PTE_TYPE_PAGE); + ptep_new = (pte_t *)page_address(pte_page); + for (i = 0; i < PTRS_PER_PTE; ++i, ++ptep_new) + __set_pte_nosync(ptep_new, + pfn_pte(pfn + i, prot)); + + dsb(ishst); + isb(); + + set_pmd(pmdp, pfn_pmd(page_to_pfn(pte_page), + __pgprot(PMD_TYPE_TABLE))); + } + } while (pmdp++, vaddr = next, vaddr != end); + + return 0; +} + +static int __split_linear_mapping_pud(p4d_t *p4dp, + unsigned long vaddr, unsigned long end) +{ + pud_t *pudp; + unsigned long next; + int ret; + + pudp = pud_offset(p4dp, vaddr); + + do { + next = pud_addr_end(vaddr, end); + + if (pud_leaf(pudp_get(pudp))) { + struct page *pmd_page; + unsigned long pfn = pud_pfn(pudp_get(pudp)); + pgprot_t prot = pud_pgprot(pudp_get(pudp)); + pmd_t *pmdp_new; + int i; + unsigned int step; + + pmd_page = alloc_page(GFP_KERNEL); + if (!pmd_page) + return -ENOMEM; + + pmdp_new = (pmd_t *)page_address(pmd_page); + for (i = 0; i < PTRS_PER_PMD; ++i, ++pmdp_new) { + step = (i * PMD_SIZE) >> PAGE_SHIFT; + __set_pmd_nosync(pmdp_new, + pfn_pmd(pfn + step, prot)); + } + + dsb(ishst); + isb(); + + set_pud(pudp, pfn_pud(page_to_pfn(pmd_page), + __pgprot(PUD_TYPE_TABLE))); + } + + ret = __split_linear_mapping_pmd(pudp, vaddr, next); + if (ret) + return ret; + } while (pudp++, vaddr = next, vaddr != end); + + return 0; +} + +static int __split_linear_mapping_p4d(pgd_t *pgdp, + unsigned long vaddr, unsigned long end) +{ + p4d_t *p4dp; + unsigned long next; + int ret; + + p4dp = p4d_offset(pgdp, vaddr); + + do { + next = p4d_addr_end(vaddr, end); + + ret = __split_linear_mapping_pud(p4dp, vaddr, next); + if (ret) + return ret; + } while (p4dp++, vaddr = next, vaddr != end); + + return 0; +} + +static int __split_linear_mapping_pgd(pgd_t *pgdp, + unsigned long vaddr, + unsigned long end) +{ + unsigned long next; + int ret = 0; + + mmap_write_lock(&init_mm); + + do { + next = pgd_addr_end(vaddr, end); + ret = __split_linear_mapping_p4d(pgdp, vaddr, next); + if (ret) + break; + } while (pgdp++, vaddr = next, vaddr != end); + + mmap_write_unlock(&init_mm); + + return ret; +} + +static int split_linear_mapping(unsigned long start, unsigned long end) +{ + int ret; + + if (!system_supports_bbmlv2()) + return 0; + + ret = __split_linear_mapping_pgd(pgd_offset_k(start), start, end); + flush_tlb_kernel_range(start, end); + + return ret; +} + /* * This function assumes that the range is mapped with PAGE_SIZE pages. */ @@ -80,8 +219,9 @@ static int change_memory_common(unsigned long addr, int numpages, unsigned long start = addr; unsigned long size = PAGE_SIZE * numpages; unsigned long end = start + size; + unsigned long l_start; struct vm_struct *area; - int i; + int i, ret; if (!PAGE_ALIGNED(addr)) { start &= PAGE_MASK; @@ -118,7 +258,12 @@ static int change_memory_common(unsigned long addr, int numpages, if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY || pgprot_val(clear_mask) == PTE_RDONLY)) { for (i = 0; i < area->nr_pages; i++) { - __change_memory_common((u64)page_address(area->pages[i]), + l_start = (u64)page_address(area->pages[i]); + ret = split_linear_mapping(l_start, l_start + PAGE_SIZE); + if (WARN_ON_ONCE(ret)) + return ret; + + __change_memory_common(l_start, PAGE_SIZE, set_mask, clear_mask); } } @@ -174,6 +319,9 @@ int set_memory_valid(unsigned long addr, int numpages, int enable) int set_direct_map_invalid_noflush(struct page *page) { + unsigned long l_start; + int ret; + struct page_change_data data = { .set_mask = __pgprot(0), .clear_mask = __pgprot(PTE_VALID), @@ -182,13 +330,21 @@ int set_direct_map_invalid_noflush(struct page *page) if (!can_set_direct_map()) return 0; + l_start = (unsigned long)page_address(page); + ret = split_linear_mapping(l_start, l_start + PAGE_SIZE); + if (WARN_ON_ONCE(ret)) + return ret; + return apply_to_page_range(&init_mm, - (unsigned long)page_address(page), - PAGE_SIZE, change_page_range, &data); + l_start, PAGE_SIZE, change_page_range, + &data); } int set_direct_map_default_noflush(struct page *page) { + unsigned long l_start; + int ret; + struct page_change_data data = { .set_mask = __pgprot(PTE_VALID | PTE_WRITE), .clear_mask = __pgprot(PTE_RDONLY), @@ -197,9 +353,14 @@ int set_direct_map_default_noflush(struct page *page) if (!can_set_direct_map()) return 0; + l_start = (unsigned long)page_address(page); + ret = split_linear_mapping(l_start, l_start + PAGE_SIZE); + if (WARN_ON_ONCE(ret)) + return ret; + return apply_to_page_range(&init_mm, - (unsigned long)page_address(page), - PAGE_SIZE, change_page_range, &data); + l_start, PAGE_SIZE, change_page_range, + &data); } static int __set_memory_enc_dec(unsigned long addr,