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It has 6 clocks like the MT8195, but 2 of them are different. Signed-off-by: Jianjun Wang --- .../bindings/pci/mediatek-pcie-gen3.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1add..b4158a666fb6 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -51,6 +51,7 @@ properties: - mediatek,mt7986-pcie - mediatek,mt8188-pcie - mediatek,mt8195-pcie + - mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8192-pcie - const: airoha,en7581-pcie @@ -197,6 +198,34 @@ allOf: minItems: 1 maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8196-pcie + then: + properties: + clocks: + minItems: 6 + + clock-names: + items: + - const: pl_250m + - const: tl_26m + - const: peri_26m + - const: peri_mem + - const: ahb_apb + - const: low_power + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + - if: properties: compatible: From patchwork Fri Jan 3 06:00:12 2025 Content-Type: text/plain; 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Fri, 03 Jan 2025 14:00:47 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 3 Jan 2025 14:00:46 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 3 Jan 2025 14:00:45 +0800 From: Jianjun Wang To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Ryder Lee , Jianjun Wang , , , , , , Xavier Chang Subject: [PATCH 2/5] PCI: mediatek-gen3: Add MT8196 support Date: Fri, 3 Jan 2025 14:00:12 +0800 Message-ID: <20250103060035.30688-3-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250103060035.30688-1-jianjun.wang@mediatek.com> References: <20250103060035.30688-1-jianjun.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The MT8196 is an ARM platform SoC that has the same PCIe IP as the MT8195. However, it requires additional settings in the pextpcfg registers. Introduce pextpcfg in PCIe driver for these settings. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 88 +++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index be52e3a123ab..ed3c0614486c 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -123,6 +124,17 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) +#define PCIE_RESOURCE_CTRL_REG 0xd2c +#define PCIE_SYS_CLK_RDY_TIME_MASK GENMASK(7, 0) +#define PCIE_SYS_CLK_RDY_TIME_TO_10US 0xa + +/* PEXTPCFG Registers */ +#define PEXTP_CLOCK_CON_REG 0x20 +#define PEXTP_P0P1_LOWPOWER_CK_SEL BIT(0) +#define PEXTP_REQ_CTRL_0_REG 0x7c +#define PEXTP_26M_REQ_FORCE_ON BIT(0) +#define PEXTP_PCIE26M_BYPASS BIT(4) + #define MAX_NUM_PHY_RESETS 3 /* Time in ms needed to complete PCIe reset on EN7581 SoC */ @@ -136,10 +148,14 @@ struct mtk_gen3_pcie; /** * struct mtk_gen3_pcie_pdata - differentiate between host generations * @power_up: pcie power_up callback + * @pre_init: initialize settings before link up + * @cleanup: cleanup when PCIe power down * @phy_resets: phy reset lines SoC data. */ struct mtk_gen3_pcie_pdata { int (*power_up)(struct mtk_gen3_pcie *pcie); + int (*pre_init)(struct mtk_gen3_pcie *pcie); + void (*cleanup)(struct mtk_gen3_pcie *pcie); struct { const char *id[MAX_NUM_PHY_RESETS]; int num_resets; @@ -162,6 +178,7 @@ struct mtk_msi_set { * struct mtk_gen3_pcie - PCIe port information * @dev: pointer to PCIe device * @base: IO mapped register base + * @pextpcfg: pextpcfg_ao IO mapped register base * @reg_base: physical register base * @mac_reset: MAC reset control * @phy_resets: PHY reset controllers @@ -184,6 +201,7 @@ struct mtk_msi_set { struct mtk_gen3_pcie { struct device *dev; void __iomem *base; + void __iomem *pextpcfg; phys_addr_t reg_base; struct reset_control *mac_reset; struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS]; @@ -422,6 +440,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS); } + /* + * The values of some registers are different in RC and EP mode. Therefore, + * call soc->pre_init after the mode change in case it depends on these registers. + */ + if (pcie->soc && pcie->soc->pre_init) + pcie->soc->pre_init(pcie); + /* Set class code */ val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1); val &= ~GENMASK(31, 8); @@ -848,6 +873,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) int i, ret, num_resets = pcie->soc->phy_resets.num_resets; struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); + struct device_node *node; struct resource *regs; u32 num_lanes; @@ -903,6 +929,18 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) pcie->num_lanes = num_lanes; } + node = of_parse_phandle(dev->of_node, "pextpcfg", 0); + if (node) { + pcie->pextpcfg = of_iomap(node, 0); + of_node_put(node); + if (IS_ERR(pcie->pextpcfg)) { + dev_err(dev, "failed to get pextpcfg\n"); + ret = PTR_ERR(pcie->pextpcfg); + pcie->pextpcfg = NULL; + return ret; + } + } + return 0; } @@ -1047,6 +1085,12 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) phy_power_off(pcie->phy); phy_exit(pcie->phy); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + + if (pcie->soc && pcie->soc->cleanup) + pcie->soc->cleanup(pcie); + + if (pcie->pextpcfg) + iounmap(pcie->pextpcfg); } static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie) @@ -1277,6 +1321,49 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = { }, }; +static int mtk_pcie_mt8196_pre_init(struct mtk_gen3_pcie *pcie) +{ + u32 val; + + /* Adjust SYS_CLK_RDY_TIME ot 10us to avoid glitch */ + val = readl_relaxed(pcie->base + PCIE_RESOURCE_CTRL_REG); + val &= ~PCIE_SYS_CLK_RDY_TIME_MASK; + val |= PCIE_SYS_CLK_RDY_TIME_TO_10US; + writel_relaxed(val, pcie->base + PCIE_RESOURCE_CTRL_REG); + + /* Switch to normal clock */ + val = readl_relaxed(pcie->pextpcfg + PEXTP_CLOCK_CON_REG); + val &= ~PEXTP_P0P1_LOWPOWER_CK_SEL; + writel_relaxed(val, pcie->pextpcfg + PEXTP_CLOCK_CON_REG); + + /* Force pcie_26m_req and bypass pcie_26m_ack signal */ + val = readl_relaxed(pcie->pextpcfg + PEXTP_REQ_CTRL_0_REG); + val |= (PEXTP_26M_REQ_FORCE_ON | PEXTP_PCIE26M_BYPASS); + writel_relaxed(val, pcie->pextpcfg + PEXTP_REQ_CTRL_0_REG); + + return 0; +} + +static void mtk_pcie_mt8196_cleanup(struct mtk_gen3_pcie *pcie) +{ + u32 val; + + /* Release pcie_26m_req and pcie_26m_ack signal */ + val = readl_relaxed(pcie->pextpcfg + PEXTP_REQ_CTRL_0_REG); + val &= ~(PEXTP_26M_REQ_FORCE_ON | PEXTP_PCIE26M_BYPASS); + writel_relaxed(val, pcie->pextpcfg + PEXTP_REQ_CTRL_0_REG); +} + +static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8196 = { + .power_up = mtk_pcie_power_up, + .pre_init = mtk_pcie_mt8196_pre_init, + .cleanup = mtk_pcie_mt8196_cleanup, + .phy_resets = { + .id[0] = "phy", + .num_resets = 1, + }, +}; + static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { .power_up = mtk_pcie_en7581_power_up, .phy_resets = { @@ -1290,6 +1377,7 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { static const struct of_device_id mtk_pcie_of_match[] = { { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, + { .compatible = "mediatek,mt8196-pcie", .data = &mtk_pcie_soc_mt8196 }, {}, }; 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Fri, 03 Jan 2025 14:00:48 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 3 Jan 2025 14:00:47 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 3 Jan 2025 14:00:46 +0800 From: Jianjun Wang To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Ryder Lee , Jianjun Wang , , , , , , Xavier Chang Subject: [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s Date: Fri, 3 Jan 2025 14:00:13 +0800 Message-ID: <20250103060035.30688-4-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250103060035.30688-1-jianjun.wang@mediatek.com> References: <20250103060035.30688-1-jianjun.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Disable ASPM L0s support because it does not significantly save power but impacts performance. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index ed3c0614486c..4bd3b39eebe2 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -84,6 +84,9 @@ #define PCIE_MSI_SET_ENABLE_REG 0x190 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) +#define PCIE_LOW_POWER_CTRL_REG 0x194 +#define PCIE_FORCE_DIS_L0S BIT(8) + #define PCIE_PIPE4_PIE8_REG 0x338 #define PCIE_K_FINETUNE_MAX GENMASK(5, 0) #define PCIE_K_FINETUNE_ERR GENMASK(7, 6) @@ -458,6 +461,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) val &= ~PCIE_INTX_ENABLE; writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); + /* + * Disable L0s support because it does not significantly save power + * but impacts performance. + */ + val = readl_relaxed(pcie->base + PCIE_LOW_POWER_CTRL_REG); + val |= PCIE_FORCE_DIS_L0S; + writel_relaxed(val, pcie->base + PCIE_LOW_POWER_CTRL_REG); + /* Disable DVFSRC voltage request */ val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG); val |= PCIE_DISABLE_DVFSRC_VLT_REQ; From patchwork Fri Jan 3 06:00:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 13925162 X-Patchwork-Delegate: kw@linux.com Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E2C11B3929; Fri, 3 Jan 2025 06:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884057; cv=none; b=NTp6hc7uhewTFwOItGAYezRQmvsu4poyL9YUyAekcol/HTiYYKuLFtMnVvd+sbCMJd8NX3wRpPtnyxaVRv+SJ8+OX08iz8qIILsCfeagUbQ2GZFoH7lbGfuzQYU0e9xpRXTFDb+rLD417/VMU5zZdWLEGUjy7f8M/VvX40Q8TrA= ARC-Message-Signature: i=1; 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Fri, 03 Jan 2025 14:00:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 3 Jan 2025 14:00:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 3 Jan 2025 14:00:47 +0800 From: Jianjun Wang To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Ryder Lee , Jianjun Wang , , , , , , Xavier Chang Subject: [PATCH 4/5] PCI: mediatek-gen3: Don't reply AXI slave error Date: Fri, 3 Jan 2025 14:00:14 +0800 Message-ID: <20250103060035.30688-5-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250103060035.30688-1-jianjun.wang@mediatek.com> References: <20250103060035.30688-1-jianjun.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N There are some circumstances where the EP device will not respond to non-posted access from the root port (e.g., MMIO read). In such cases, the root port will reply with an AXI slave error, which will be treated as a System Error (SError), causing a kernel panic and preventing us from obtaining any useful information for further debugging. We have added a new bit in the PCIE_AXI_IF_CTRL_REG register to prevent PCIe AXI0 from replying with a slave error. Setting this bit on an older platform that does not support this feature will have no effect. By preventing AXI0 from replying with a slave error, we can keep the kernel alive and debug using the information from AER. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 4bd3b39eebe2..48f83c2d91f7 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -87,6 +87,9 @@ #define PCIE_LOW_POWER_CTRL_REG 0x194 #define PCIE_FORCE_DIS_L0S BIT(8) +#define PCIE_AXI_IF_CTRL_REG 0x1a8 +#define PCIE_AXI0_SLV_RESP_MASK BIT(12) + #define PCIE_PIPE4_PIE8_REG 0x338 #define PCIE_K_FINETUNE_MAX GENMASK(5, 0) #define PCIE_K_FINETUNE_ERR GENMASK(7, 6) @@ -469,6 +472,15 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) val |= PCIE_FORCE_DIS_L0S; writel_relaxed(val, pcie->base + PCIE_LOW_POWER_CTRL_REG); + /* + * Prevent PCIe AXI0 from replying a slave error, as it will cause kernel panic + * and prevent us from getting useful information. + * Keep the kernel alive and debug using the information from AER. + */ + val = readl_relaxed(pcie->base + PCIE_AXI_IF_CTRL_REG); + val |= PCIE_AXI0_SLV_RESP_MASK; + writel_relaxed(val, pcie->base + PCIE_AXI_IF_CTRL_REG); + /* Disable DVFSRC voltage request */ val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG); val |= PCIE_DISABLE_DVFSRC_VLT_REQ; From patchwork Fri Jan 3 06:00:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 13925166 X-Patchwork-Delegate: kw@linux.com Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54591BFE06; Fri, 3 Jan 2025 06:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884066; cv=none; b=FsrOaEiCebu3iAKq8ZssK3GygWO70k6hGHSh+bZEF6uKTYr2C21HCtz3PjhbKWTXcUCrJoWcZiVeyuTHEqpFAUiRYorLKsbe2FdHfU9eMEmZHrz8l+k79u+CLiVasC2BhNicEmsL+9jwzqAu37QpO+UCrXY/uILIu8zQk+pp+1o= ARC-Message-Signature: i=1; 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Fri, 03 Jan 2025 14:00:50 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 3 Jan 2025 14:00:49 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 3 Jan 2025 14:00:48 +0800 From: Jianjun Wang To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Ryder Lee , Jianjun Wang , , , , , , Xavier Chang Subject: [PATCH 5/5] PCI: mediatek-gen3: Keep PCIe power and clocks if suspend-to-idle Date: Fri, 3 Jan 2025 14:00:15 +0800 Message-ID: <20250103060035.30688-6-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250103060035.30688-1-jianjun.wang@mediatek.com> References: <20250103060035.30688-1-jianjun.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N If the target system sleep state is suspend-to-idle, the bridge is supposed to stay in D0, and the framework will not help to restore its configuration space, so keep its power and clocks during suspend. It's recommended to enable L1ss support, so the link can be changed to L1.2 state during suspend. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 48f83c2d91f7..11da68910502 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1291,6 +1291,19 @@ static int mtk_pcie_suspend_noirq(struct device *dev) int err; u32 val; + /* + * If the target system sleep state is suspend-to-idle, the bridge is supposed to stay in + * D0, and the framework will not help to restore its configuration space, so keep it's + * power and clocks during suspend. + * + * It's recommended to enable L1ss support, so the link can be changed to L1.2 state during + * suspend. + */ + if (pm_suspend_default_s2idle()) { + dev_info(dev, "System enter s2idle state, keep PCIe power and clocks\n"); + return 0; + } + /* Trigger link to L2 state */ err = mtk_pcie_turn_off_link(pcie); if (err) { @@ -1316,6 +1329,11 @@ static int mtk_pcie_resume_noirq(struct device *dev) struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); int err; + if (pm_suspend_default_s2idle()) { + dev_info(dev, "System enter s2idle state, no need to reinitialization\n"); + return 0; + } + err = pcie->soc->power_up(pcie); if (err) return err;