From patchwork Fri Jan 3 09:07:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Divya Koppera X-Patchwork-Id: 13925396 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88A9C1C5F09; Fri, 3 Jan 2025 09:09:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735895357; cv=none; b=C0rcRmFH5DY8NaEr3n76ar0h4PU4ByhIMH6ZTa2ur+0JpZZOCTUY/bcsErU9BKjA6Q/VApp2cUII2JPGDxtutrcT621LBwXOG/T2IIPiqYw5cOQKwPuFWAXBvTpyzSnkYqKI8HpAi8sF7V/QLhL840B+wmmvSQPYouVkRgwjTuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735895357; c=relaxed/simple; bh=INfFyU5nKdRbFettIvyvhrAPh8m5UDTJ0K4DWxzxwE8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bAofNrbV85+Oz9mAWVZxJErebjey+r0UB6liswvTp3uKrkwjc80+tzlgLxJI2eWBSev+Nfy8MY/j0wd6SQJpBaGbLWO3nFDFtHsGvizW5+2MJBU8w1Vvm6yBJ0igjAenoh9Bn76P3N54x/4Vp0r56UzNQRigAwaZ0aANygYL0S0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=aRNTr/wT; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aRNTr/wT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1735895355; x=1767431355; h=from:to:subject:date:message-id:in-reply-to:references: mime-version; bh=INfFyU5nKdRbFettIvyvhrAPh8m5UDTJ0K4DWxzxwE8=; b=aRNTr/wThJKbtVeWl1N/WZeJl9kEkkOpYieOn46w5xbiE/j697iAphfl HuYmYfWnXV8p/weA7gEsBybwMeoH1FG/CSr1Aw57LBJoePetJz596DcLf cgMHScO9ca0EJm6mZh/Qk5hpJOeeEBsB78JfHNRzszizY16C9+5Q9G1CQ aVK6lC4mzCf6SaV5YEMsD/Qnq50qaPMPAW1fuHAsvmQ/SLRCOjatwnlD2 I4IsrVdlaSirRHzJWymTesHZAl8ruGUnz2vb1Nj/H3bzApIW6PWBpM5th st68aMb3baNxD6KFrskRHU+BUw5YGV41c/s4fOrO3XFhMMGLjyluVHteD g==; X-CSE-ConnectionGUID: 9lugowQIRF2Bdg+6ihLSRg== X-CSE-MsgGUID: 6wA70II8TF2HV4eNnFW3hA== X-IronPort-AV: E=Sophos;i="6.12,286,1728975600"; d="scan'208";a="35788954" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jan 2025 02:08:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 3 Jan 2025 02:07:35 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 3 Jan 2025 02:07:31 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next 1/3] net: phy: microchip_rds_ptp: Header file library changes for PEROUT Date: Fri, 3 Jan 2025 14:37:29 +0530 Message-ID: <20250103090731.1355-2-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103090731.1355-1-divya.koppera@microchip.com> References: <20250103090731.1355-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This ptp header file library changes will cover PEROUT macros that are required to generate periodic output from GPIO Signed-off-by: Divya Koppera --- drivers/net/phy/microchip_rds_ptp.h | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/net/phy/microchip_rds_ptp.h b/drivers/net/phy/microchip_rds_ptp.h index e95c065728b5..08058b407639 100644 --- a/drivers/net/phy/microchip_rds_ptp.h +++ b/drivers/net/phy/microchip_rds_ptp.h @@ -130,6 +130,41 @@ #define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1 #define MCHP_RDS_PTP_TSU_HARDRESET BIT(0) +/* PTP GPIO Registers */ +#define MCHP_RDS_PTP_CLK_TRGT_SEC_HI_X(evt) (evt ? 0x1f : 0x15) +#define MCHP_RDS_PTP_CLK_TRGT_SEC_LO_X(evt) (evt ? 0x20 : 0x16) +#define MCHP_RDS_PTP_CLK_TRGT_NS_HI_X(evt) (evt ? 0x21 : 0x17) +#define MCHP_RDS_PTP_CLK_TRGT_NS_LO_X(evt) (evt ? 0x22 : 0x18) + +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI_X(evt) (evt ? 0x23 : 0x19) +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO_X(evt) (evt ? 0x24 : 0x1a) +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI_X(evt) (evt ? 0x25 : 0x1b) +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO_X(evt) (evt ? 0x26 : 0x1c) + +#define MCHP_RDS_PTP_GEN_CFG 0x01 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_X_MASK_(evt) \ + ((evt) ? GENMASK(11, 8) : GENMASK(7, 4)) + +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_X_SET_(evt, value) \ + (((value) & 0xF) << (4 + ((evt) << 2))) +#define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD_X_(evt) ((evt) ? BIT(2) : BIT(0)) +#define MCHP_RDS_PTP_GEN_CFG_POLARITY_X_(evt) ((evt) ? BIT(3) : BIT(1)) + +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_ 13 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100MS_ 12 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50MS_ 11 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10MS_ 10 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5MS_ 9 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1MS_ 8 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500US_ 7 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100US_ 6 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50US_ 5 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10US_ 4 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5US_ 3 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1US_ 2 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500NS_ 1 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100NS_ 0 + /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 4 clock cycles in 250MHz. * The value is calculated as following: (1/1000000)/((2^-32)/4) @@ -138,6 +173,13 @@ #define MCHP_RDS_PTP_FIFO_SIZE 8 #define MCHP_RDS_PTP_MAX_ADJ 31249999 +#define MCHP_RDS_PTP_EVT_A 0 +#define MCHP_RDS_PTP_EVT_B 1 +#define MCHP_RDS_PTP_BUFFER_TIME 2 + +#define MCHP_RDS_PTP_N_GPIO 4 +#define MCHP_RDS_PTP_N_PEROUT 2 + #define BASE_CLK(p) ((p)->clk_base_addr) #define BASE_PORT(p) ((p)->port_base_addr) #define PTP_MMD(p) ((p)->mmd) @@ -176,6 +218,11 @@ struct mchp_rds_ptp_clock { /* Lock for phc */ struct mutex ptp_lock; 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Fri, 3 Jan 2025 02:07:40 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 3 Jan 2025 02:07:36 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next 2/3] net: phy: microchip_t1: Enable GPIO pins specific to lan887x phy for PEROUT signals Date: Fri, 3 Jan 2025 14:37:30 +0530 Message-ID: <20250103090731.1355-3-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103090731.1355-1-divya.koppera@microchip.com> References: <20250103090731.1355-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Adds support for enabling GPIO pins that are required to generate periodic output signals on lan887x phy. Signed-off-by: Divya Koppera --- drivers/net/phy/microchip_t1.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c index 73f28463bc35..b0a34f794f4c 100644 --- a/drivers/net/phy/microchip_t1.c +++ b/drivers/net/phy/microchip_t1.c @@ -273,6 +273,11 @@ /* End offset of samples */ #define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM) +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1 (0xF002) +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8) +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_REF_CLK BIT(9) +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_GPIO2_EN BIT(5) + #define DRIVER_AUTHOR "Nisar Sayed " #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" @@ -1286,6 +1291,19 @@ static int lan887x_phy_init(struct phy_device *phydev) if (IS_ERR(priv->clock)) return PTR_ERR(priv->clock); + /* Enable pin mux for GPIO 2(EVT B) as ref clk */ + /* Enable pin mux for EVT A */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, + LAN887X_MX_CHIP_TOP_REG_CONTROL1, + LAN887X_MX_CHIP_TOP_REG_CONTROL1_REF_CLK | + LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN, + LAN887X_MX_CHIP_TOP_REG_CONTROL1_REF_CLK | + LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN); 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Fri, 3 Jan 2025 02:07:45 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 3 Jan 2025 02:07:41 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next 3/3] net: phy: microchip_rds_ptp : Add PEROUT feature library for RDS PTP supported phys Date: Fri, 3 Jan 2025 14:37:31 +0530 Message-ID: <20250103090731.1355-4-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103090731.1355-1-divya.koppera@microchip.com> References: <20250103090731.1355-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Adds PEROUT feature for RDS PTP supported phys where we can generate periodic output signal on supported GPIO pins Signed-off-by: Divya Koppera --- drivers/net/phy/microchip_rds_ptp.c | 320 ++++++++++++++++++++++++++++ 1 file changed, 320 insertions(+) diff --git a/drivers/net/phy/microchip_rds_ptp.c b/drivers/net/phy/microchip_rds_ptp.c index 2936e46531cf..396975be2a31 100644 --- a/drivers/net/phy/microchip_rds_ptp.c +++ b/drivers/net/phy/microchip_rds_ptp.c @@ -54,6 +54,288 @@ static int mchp_rds_phy_set_bits_mmd(struct mchp_rds_ptp_clock *clock, return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val); } +static int mchp_get_pulsewidth(struct phy_device *phydev, + struct ptp_perout_request *perout_request, + int *pulse_width) +{ + struct timespec64 ts_period; + s64 ts_on_nsec, period_nsec; + struct timespec64 ts_on; + + ts_period.tv_sec = perout_request->period.sec; + ts_period.tv_nsec = perout_request->period.nsec; + + ts_on.tv_sec = perout_request->on.sec; + ts_on.tv_nsec = perout_request->on.nsec; + ts_on_nsec = timespec64_to_ns(&ts_on); + period_nsec = timespec64_to_ns(&ts_period); + + if (period_nsec < 200) { + phydev_warn(phydev, "perout period too small, minimum is 200ns\n"); + return -EOPNOTSUPP; + } + + switch (ts_on_nsec) { + case 200000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_; + break; + case 100000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100MS_; + break; + case 50000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50MS_; + break; + case 10000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10MS_; + break; + case 5000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5MS_; + break; + case 1000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1MS_; + break; + case 500000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500US_; + break; + case 100000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100US_; + break; + case 50000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50US_; + break; + case 10000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10US_; + break; + case 5000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5US_; + break; + case 1000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1US_; + break; + case 500: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500NS_; + break; + case 100: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100NS_; + break; + default: + phydev_warn(phydev, "Using default pulse width of 200ms\n"); + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_; + break; + } + return 0; +} + +static int mchp_general_event_config(struct mchp_rds_ptp_clock *clock, s8 event, + int pulse_width) +{ + int general_config; + + general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK); + if (general_config < 0) + return general_config; + + general_config &= ~(MCHP_RDS_PTP_GEN_CFG_LTC_EVT_X_MASK_(event)); + general_config |= MCHP_RDS_PTP_GEN_CFG_LTC_EVT_X_SET_(event, + pulse_width); + general_config &= ~(MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD_X_(event)); + general_config |= MCHP_RDS_PTP_GEN_CFG_POLARITY_X_(event); + + return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK, general_config); +} + +static int mchp_set_clock_reload(struct mchp_rds_ptp_clock *clock, s8 evt, + s64 period_sec, u32 period_nsec) +{ + int rc; + + rc = mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO_X(evt), + MCHP_RDS_PTP_CLOCK, + lower_16_bits(period_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI_X(evt), + MCHP_RDS_PTP_CLOCK, + upper_16_bits(period_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO_X(evt), + MCHP_RDS_PTP_CLOCK, + lower_16_bits(period_nsec)); + if (rc < 0) + return rc; + + return mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI_X(evt), + MCHP_RDS_PTP_CLOCK, + upper_16_bits(period_nsec) & 0x3fff); +} + +static int mchp_get_event(struct mchp_rds_ptp_clock *clock, int pin) +{ + if (clock->mchp_rds_ptp_event_a < 0 && pin == clock->gpio_event_a) { + clock->mchp_rds_ptp_event_a = pin; + return MCHP_RDS_PTP_EVT_A; + } + + if (clock->mchp_rds_ptp_event_b < 0 && pin == clock->gpio_event_b) { + clock->mchp_rds_ptp_event_b = pin; + return MCHP_RDS_PTP_EVT_B; + } + + return -1; +} + +static int mchp_set_clock_target(struct mchp_rds_ptp_clock *clock, s8 evt, + s64 start_sec, u32 start_nsec) +{ + int rc; + + if (evt < 0) + return -1; + + /* Set the start time */ + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_LO_X(evt), + MCHP_RDS_PTP_CLOCK, + lower_16_bits(start_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_HI_X(evt), + MCHP_RDS_PTP_CLOCK, + upper_16_bits(start_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_LO_X(evt), + MCHP_RDS_PTP_CLOCK, + lower_16_bits(start_nsec)); + if (rc < 0) + return rc; + + return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_HI_X(evt), + MCHP_RDS_PTP_CLOCK, + upper_16_bits(start_nsec) & 0x3fff); +} + +static int mchp_rds_ptp_perout_off(struct mchp_rds_ptp_clock *clock, + s8 gpio_pin) +{ + u16 general_config; + int event; + int rc; + + if (clock->mchp_rds_ptp_event_a == gpio_pin) + event = MCHP_RDS_PTP_EVT_A; + else if (clock->mchp_rds_ptp_event_b == gpio_pin) + event = MCHP_RDS_PTP_EVT_B; + + /* Set target to too far in the future, effectively disabling it */ + rc = mchp_set_clock_target(clock, gpio_pin, 0xFFFFFFFF, 0); + if (rc < 0) + return rc; + + general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK); + general_config |= MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD_X_(event); + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK, general_config); + if (rc < 0) + return rc; + + if (event == MCHP_RDS_PTP_EVT_A) + clock->mchp_rds_ptp_event_a = -1; + + if (event == MCHP_RDS_PTP_EVT_B) + clock->mchp_rds_ptp_event_b = -1; + + return 0; +} + +static int mchp_rds_ptp_perout(struct ptp_clock_info *ptpci, + struct ptp_perout_request *perout, int on) +{ + struct mchp_rds_ptp_clock *clock = container_of(ptpci, + struct mchp_rds_ptp_clock, + caps); + struct phy_device *phydev = clock->phydev; + int ret, event, gpio_pin, pulsewidth; + + /* Reject requests with unsupported flags */ + if (perout->flags & ~PTP_PEROUT_DUTY_CYCLE) + return -EOPNOTSUPP; + + gpio_pin = ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, perout->index); + if (gpio_pin != clock->gpio_event_a && gpio_pin != clock->gpio_event_b) + return -EINVAL; + + if (!on) { + ret = mchp_rds_ptp_perout_off(clock, gpio_pin); + return ret; + } + + ret = mchp_get_pulsewidth(phydev, perout, &pulsewidth); + if (ret < 0) + return ret; + + event = mchp_get_event(clock, gpio_pin); + if (event < 0) + return event; + + /* Configure to pulse every period */ + ret = mchp_general_event_config(clock, event, pulsewidth); + if (ret < 0) + return ret; + + ret = mchp_set_clock_target(clock, event, perout->start.sec, + perout->start.nsec); + if (ret < 0) + return ret; + + return mchp_set_clock_reload(clock, event, perout->period.sec, + perout->period.nsec); +} + +static int mchp_rds_ptpci_enable(struct ptp_clock_info *ptpci, + struct ptp_clock_request *request, int on) +{ + switch (request->type) { + case PTP_CLK_REQ_PEROUT: + return mchp_rds_ptp_perout(ptpci, &request->perout, on); + default: + return -EINVAL; + } +} + +static int mchp_rds_ptpci_verify(struct ptp_clock_info *ptpci, unsigned int pin, + enum ptp_pin_function func, unsigned int chan) +{ + struct mchp_rds_ptp_clock *clock = container_of(ptpci, + struct mchp_rds_ptp_clock, + caps); + + if (!(pin == clock->gpio_event_b && chan == 1) && + !(pin == clock->gpio_event_a && chan == 0)) + return -1; + + switch (func) { + case PTP_PF_NONE: + case PTP_PF_PEROUT: + break; + default: + return -1; + } + + return 0; +} + static int mchp_rds_ptp_flush_fifo(struct mchp_rds_ptp_clock *clock, enum mchp_rds_ptp_fifo_dir dir) { @@ -479,6 +761,20 @@ static int mchp_rds_ptp_ltc_adjtime(struct ptp_clock_info *info, s64 delta) MCHP_RDS_PTP_CMD_CTL_LTC_STEP_NSEC); } + mutex_unlock(&clock->ptp_lock); + info->gettime64(info, &ts); + mutex_lock(&clock->ptp_lock); + + /* Target update is required for pulse generation on events that + * are enabled + */ + if (clock->mchp_rds_ptp_event_a >= 0) + mchp_set_clock_target(clock, MCHP_RDS_PTP_EVT_A, + ts.tv_sec + MCHP_RDS_PTP_BUFFER_TIME, 0); + + if (clock->mchp_rds_ptp_event_b >= 0) + mchp_set_clock_target(clock, MCHP_RDS_PTP_EVT_B, + ts.tv_sec + MCHP_RDS_PTP_BUFFER_TIME, 0); out_unlock: mutex_unlock(&clock->ptp_lock); @@ -989,16 +1285,37 @@ struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd, clock->mmd = mmd; mutex_init(&clock->ptp_lock); + clock->pin_config = devm_kmalloc_array(&phydev->mdio.dev, + MCHP_RDS_PTP_N_GPIO, + sizeof(*clock->pin_config), + GFP_KERNEL); + if (!clock->pin_config) + return ERR_PTR(-ENOMEM); + + for (int i = 0; i < MCHP_RDS_PTP_N_GPIO; ++i) { + struct ptp_pin_desc *p = &clock->pin_config[i]; + + memset(p, 0, sizeof(*p)); + snprintf(p->name, sizeof(p->name), "pin%d", i); + p->index = i; + p->func = PTP_PF_NONE; + } /* Register PTP clock */ clock->caps.owner = THIS_MODULE; snprintf(clock->caps.name, 30, "%s", phydev->drv->name); clock->caps.max_adj = MCHP_RDS_PTP_MAX_ADJ; clock->caps.n_ext_ts = 0; clock->caps.pps = 0; + clock->caps.n_pins = MCHP_RDS_PTP_N_GPIO; + clock->caps.n_per_out = MCHP_RDS_PTP_N_PEROUT; + clock->caps.pin_config = clock->pin_config; clock->caps.adjfine = mchp_rds_ptp_ltc_adjfine; clock->caps.adjtime = mchp_rds_ptp_ltc_adjtime; clock->caps.gettime64 = mchp_rds_ptp_ltc_gettime64; clock->caps.settime64 = mchp_rds_ptp_ltc_settime64; + clock->caps.enable = mchp_rds_ptpci_enable; + clock->caps.verify = mchp_rds_ptpci_verify; + clock->caps.getcrosststamp = NULL; clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->mdio.dev); if (IS_ERR(clock->ptp_clock)) @@ -1021,6 +1338,9 @@ struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd, phydev->mii_ts = &clock->mii_ts; + clock->mchp_rds_ptp_event_a = -1; + clock->mchp_rds_ptp_event_b = -1; + /* Timestamp selected by default to keep legacy API */ phydev->default_timestamp = true;