From patchwork Fri Aug 17 16:38:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10569207 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E18B109C for ; Fri, 17 Aug 2018 16:39:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 115BC2BDD7 for ; Fri, 17 Aug 2018 16:39:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00F6F2BDCE; Fri, 17 Aug 2018 16:39:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A7A62BDCE for ; Fri, 17 Aug 2018 16:39:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727965AbeHQTnU (ORCPT ); Fri, 17 Aug 2018 15:43:20 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:47872 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727037AbeHQTnT (ORCPT ); Fri, 17 Aug 2018 15:43:19 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D1F076149F; Fri, 17 Aug 2018 16:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534523955; bh=OsmSAU1Zg2GuXr0kzyHMLgz9hGKaACf4GCTcZ/iO9II=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=POOJp04uIOt/OX8AAG/yAHkNLP0QUv8IXOhwCrog89zHPlWGoGizcl9SuH+T/U6lv eQEM7uwv8tyKmGWIS6lPNYo9UrgbU+A75u4zK/ps84WWdWgHY3OckUsMdJiwILK7O2 qoynVjULMNDn+Sep2FxRpmAdiocJqIie+w7WC18k= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 962616149F; Fri, 17 Aug 2018 16:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534523954; bh=OsmSAU1Zg2GuXr0kzyHMLgz9hGKaACf4GCTcZ/iO9II=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bwIHNFTwxZ3fdnuZ4e/hzttMViT8eJZHZbAwerhjWSMEwuBo4lz1H4GAXrWYh+5Pa Q8kNa41CPuYsI6h0EG2SVrjHw8Kjng5X+7u3ttanBpRoyBFKvDUJ5eQmpVaThVcRdH ND5fQFKHp/UzH1s/HxpZhppgOKC6uou8SS/BqPKU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 962616149F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v2 1/5] drivers: pinctrl: qcom: add wakeup capability to GPIO Date: Fri, 17 Aug 2018 10:38:45 -0600 Message-Id: <20180817163849.30750-2-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180817163849.30750-1-ilina@codeaurora.org> References: <20180817163849.30750-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on domain can wakeup the SoC, when interrupts and GPIOs are routed to the its interrupt controller. Only select GPIOs that are deemed wakeup capable are routed to specific PDC pins. During low power state, the pinmux interrupt controller may be non-functional but the PDC would be. The PDC can detect the wakeup GPIO is triggered and bring the TLMM to an operational state. Interrupts that are level triggered will be detected at the TLMM when the controller becomes operational. Edge interrupts however need to be replayed again. Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ, but keep it disabled. During suspend, we can enable the PDC IRQ instead of the GPIO IRQ, which may or not be detected. Signed-off-by: Lina Iyer --- Changes in v1: - Trigger GPIO in h/w from PDC IRQ handler - Avoid big tables for GPIO-PDC map, pick from DT instead - Use handler_data --- drivers/pinctrl/qcom/pinctrl-msm.c | 97 ++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 0e22f52b2a19..03ef1d29d078 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -687,11 +687,15 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) const struct msm_pingroup *g; unsigned long flags; u32 val; + struct irq_data *pdc_irqd = irq_get_handler_data(d->irq); g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); + if (pdc_irqd) + irq_set_irq_type(pdc_irqd->irq, type); + /* * For hw without possibility of detecting both edges */ @@ -779,9 +783,13 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; + struct irq_data *pdc_irqd = irq_get_handler_data(d->irq); raw_spin_lock_irqsave(&pctrl->lock, flags); + if (pdc_irqd) + irq_set_irq_wake(pdc_irqd->irq, on); + irq_set_irq_wake(pctrl->irq, on); raw_spin_unlock_irqrestore(&pctrl->lock, flags); @@ -863,6 +871,93 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; } +static irqreturn_t wake_irq_gpio_handler(int irq, void *data) +{ + struct irq_data *irqd = data; + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + if (!irqd_is_level_type(irqd)) { + g = &pctrl->soc->groups[irqd->hwirq]; + raw_spin_lock_irqsave(&pctrl->lock, flags); + val = BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + } + + return IRQ_HANDLED; +} + +static int msm_gpio_pdc_pin_request(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct platform_device *pdev = to_platform_device(pctrl->dev); + unsigned irq; + unsigned long trigger; + const char *pin_name; + int ret; + + pin_name = kasprintf(GFP_KERNEL, "gpio%lu", d->hwirq); + if (!pin_name) + return -ENOMEM; + + irq = platform_get_irq_byname(pdev, pin_name); + if (irq < 0) { + kfree(pin_name); + return 0; + } + + trigger = irqd_get_trigger_type(d) | IRQF_ONESHOT | IRQF_NO_SUSPEND; + ret = request_irq(irq, wake_irq_gpio_handler, trigger, pin_name, d); + if (ret) { + pr_warn("GPIO-%lu could not be set up as wakeup", d->hwirq); + kfree(pin_name); + return ret; + } + + irq_set_handler_data(d->irq, irq_get_irq_data(irq)); + disable_irq(irq); + + return 0; +} + +static int msm_gpio_pdc_pin_release(struct irq_data *d) +{ + struct irq_data *pdc_irqd = irq_get_handler_data(d->irq); + + if (pdc_irqd) { + irq_set_handler_data(d->irq, NULL); + free_irq(pdc_irqd->irq, d); + } + + return 0; +} + +static int msm_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { + dev_err(gc->parent,"unable to lock HW IRQ %lu for IRQ\n", + irqd_to_hwirq(d)); + return -EINVAL; + } + + return msm_gpio_pdc_pin_request(d); +} + +static void msm_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + msm_gpio_pdc_pin_release(d); + gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); +} + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; @@ -887,6 +982,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; + pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; + pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { From patchwork Fri Aug 17 16:38:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10569209 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 532B4109C for ; Fri, 17 Aug 2018 16:39:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 488262BDCE for ; Fri, 17 Aug 2018 16:39:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CD272BDD8; Fri, 17 Aug 2018 16:39:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B27072BDCE for ; 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Fri, 17 Aug 2018 16:39:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534523956; bh=C5JaBqR4HXSX6Nz6LQ9CchmYdKUhr+ne7FvXeOwBfTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HoT+OF/NsvCG10n16cvntsu493WeYqf4wTLBGEvuM4sYjFZw44wks/vn3mTdez5Fq lwvVI9iEihkosf+uwTChnhNhAUnawbtz5Zs2OabGxLLMAvhe3h1oAgfR4X0ZAdc+J7 dKtcEAJ6n7DRQVLp1206iGdtv4h2ECoBJ8z2Igf0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DE51662387 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v2 2/5] dt-bindings: pinctrl: add wakeup capable GPIOs for SDM845 Date: Fri, 17 Aug 2018 10:38:46 -0600 Message-Id: <20180817163849.30750-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180817163849.30750-1-ilina@codeaurora.org> References: <20180817163849.30750-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update the documentation to use interrupts-extended format for specifying the TLMM summary IRQ line that is requested from GIC and the PDC interrupts corresponding to the wakeup capable GPIOs. Update the example to show PDC interrupts for the wakeup capable GPIOs for SDM845. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer --- .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++++++++++++++++++- 1 file changed, 55 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt index 665aadb5ea28..d7408cc74e01 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -13,10 +13,21 @@ SDM845 platform. Value type: Definition: the base address and size of the TLMM register space. -- interrupts: +- interrupts-extended: Usage: required Value type: - Definition: should specify the TLMM summary IRQ. + Definition: should specify the TLMM summary IRQ as the first + interrupt. Optionally, wake up capable GPIOs may list + their corresponding PDC interrupts here. + +- interrupt-names: + Usage: required + Value type: + Definition: the names matching the interrupt definition in the + interrupts-extended property. The first interrupt name + must be "summary-irq" for the TLMM summary IRQ. PDC + interrupts must be described by "gpioN", where N is the + GPIO line corresponding to the PDC IRQ. - interrupt-controller: Usage: required @@ -155,11 +166,52 @@ Example: tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; reg = <0x03400000 0xc00000>; - interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts-extended = <&intc GIC_SPI 208 0>, + <&pdc 510 0>, <&pdc 511 0>, <&pdc 512 0>, <&pdc 513 0>, + <&pdc 514 0>, <&pdc 515 0>, <&pdc 516 0>, <&pdc 517 0>, + <&pdc 518 0>, <&pdc 519 0>, <&pdc 632 0>, <&pdc 639 0>, + <&pdc 521 0>, <&pdc 522 0>, <&pdc 523 0>, <&pdc 524 0>, + <&pdc 525 0>, <&pdc 526 0>, <&pdc 527 0>, <&pdc 630 0>, + <&pdc 637 0>, <&pdc 529 0>, <&pdc 530 0>, <&pdc 531 0>, + <&pdc 532 0>, <&pdc 633 0>, <&pdc 640 0>, <&pdc 534 0>, + <&pdc 535 0>, <&pdc 536 0>, <&pdc 537 0>, <&pdc 538 0>, + <&pdc 539 0>, <&pdc 540 0>, <&pdc 541 0>, <&pdc 542 0>, + <&pdc 543 0>, <&pdc 544 0>, <&pdc 545 0>, <&pdc 546 0>, + <&pdc 547 0>, <&pdc 548 0>, <&pdc 549 0>, <&pdc 550 0>, + <&pdc 551 0>, <&pdc 552 0>, <&pdc 553 0>, <&pdc 554 0>, + <&pdc 555 0>, <&pdc 556 0>, <&pdc 557 0>, <&pdc 631 0>, + <&pdc 638 0>, <&pdc 559 0>, <&pdc 560 0>, <&pdc 561 0>, + <&pdc 562 0>, <&pdc 563 0>, <&pdc 564 0>, <&pdc 565 0>, + <&pdc 566 0>, <&pdc 570 0>, <&pdc 571 0>, <&pdc 572 0>, + <&pdc 573 0>, <&pdc 609 0>, <&pdc 610 0>, <&pdc 611 0>, + <&pdc 612 0>, <&pdc 613 0>, <&pdc 614 0>, <&pdc 615 0>, + <&pdc 617 0>, <&pdc 618 0>, <&pdc 619 0>, <&pdc 620 0>, + <&pdc 621 0>, <&pdc 622 0>, <&pdc 623 0>; + interrupt-names = "summary-irq", + "gpio1", "gpio3", "gpio5", "gpio10", + "gpio11", "gpio20", "gpio22", "gpio24", + "gpio26", "gpio30", "gpio31", "gpio31", + "gpio32", "gpio34", "gpio36", "gpio37", + "gpio38", "gpio39", "gpio40", "gpio41", + "gpio41", "gpio43", "gpio44", "gpio46", + "gpio48", "gpio49", "gpio49", "gpio52", + "gpio53", "gpio54", "gpio56", "gpio57", + "gpio58", "gpio59", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio64", "gpio66", + "gpio68", "gpio71", "gpio73", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio84", + "gpio85", "gpio86", "gpio88", "gpio89", + "gpio89", "gpio91", "gpio92", "gpio95", + "gpio96", "gpio97", "gpio101", "gpio103", + "gpio104", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", + "gpio127", "gpio128", "gpio129", "gpio130", + "gpio132", "gpio133", "gpio145"; qup9_active: qup9-active { mux { From patchwork Fri Aug 17 16:38:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10569211 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 541D4109C for ; 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b=c5GHEexvV5On1/IgjNVsXJ2nAavwa3eBlvP6xzlcdtWQSawCGY3wT1ZbkQO/zo9XR 37Xz4/BPI9ZQk9jJzwPE8E+rEIFvlsZYfhnajHTyKDfc7s10sg6+BrQvPSpbMYMVSx AnlxNjvz9Zw3AlR4/4ffHsDLjgnoLtgkUh6uqZlc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3448A62454 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v2 3/5] drivers: pinctrl: msm: enable PDC interrupt only during suspend Date: Fri, 17 Aug 2018 10:38:47 -0600 Message-Id: <20180817163849.30750-4-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180817163849.30750-1-ilina@codeaurora.org> References: <20180817163849.30750-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP During suspend the system may power down some of the system rails. As a result, the TLMM hw block may not be operational anymore and wakeup capable GPIOs will not be detected. The PDC however will be operational and the GPIOs that are routed to the PDC as IRQs can wake the system up. To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a GPIO trips, use TLMM for active and switch to PDC for suspend. When entering suspend, disable the TLMM wakeup interrupt and instead enable the PDC IRQ and revert upon resume. Signed-off-by: Lina Iyer --- drivers/pinctrl/qcom/pinctrl-msm.c | 60 +++++++++++++++++++++++++++++- drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 03ef1d29d078..17e541f8f09d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -37,6 +37,7 @@ #include "../pinctrl-utils.h" #define MAX_NR_GPIO 300 +#define MAX_PDC_IRQ 1024 #define PS_HOLD_OFFSET 0x820 /** @@ -51,6 +52,7 @@ * @enabled_irqs: Bitmap of currently enabled irqs. * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge * detection. + * @pdc_irqs: Bitmap of wakeup capable irqs. * @soc; Reference to soc_data of platform specific data. * @regs: Base address for the TLMM register map. */ @@ -68,11 +70,14 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(pdc_irqs, MAX_PDC_IRQ); const struct msm_pinctrl_soc_data *soc; void __iomem *regs; }; +static bool in_suspend; + static int msm_get_groups_count(struct pinctrl_dev *pctldev) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -787,8 +792,11 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) raw_spin_lock_irqsave(&pctrl->lock, flags); - if (pdc_irqd) + if (pdc_irqd && !in_suspend) { irq_set_irq_wake(pdc_irqd->irq, on); + on ? set_bit(pdc_irqd->irq, pctrl->pdc_irqs) : + clear_bit(pdc_irqd->irq, pctrl->pdc_irqs); + } irq_set_irq_wake(pctrl->irq, on); @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) } irq_set_handler_data(d->irq, irq_get_irq_data(irq)); + irq_set_handler_data(irq, d); + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); disable_irq(irq); return 0; @@ -1070,6 +1080,54 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) } } +int __maybe_unused msm_pinctrl_suspend_late(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + struct irq_data *irqd; + int i; + + in_suspend = true; + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { + irqd = irq_get_handler_data(i); + /* + * We don't know if the TLMM will be functional + * or not, during the suspend. If its functional, + * we do not want duplicate interrupts from PDC. + * Hence disable the GPIO IRQ and enable PDC IRQ. + */ + if (irqd_is_wakeup_set(irqd)) { + irq_set_irq_wake(irqd->irq, false); + disable_irq(irqd->irq); + enable_irq(i); + } + } + + return 0; +} + +int __maybe_unused msm_pinctrl_resume_late(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + struct irq_data *irqd; + int i; + + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { + irqd = irq_get_handler_data(i); + /* + * The TLMM will be operational now, so disable + * the PDC IRQ. + */ + if (irqd_is_wakeup_set(irq_get_irq_data(i))) { + disable_irq_nosync(i); + irq_set_irq_wake(irqd->irq, true); + enable_irq(irqd->irq); + } + } + in_suspend = false; + + return 0; +} + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 9b9feea540ff..21b56fb5dae9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -123,4 +123,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data); int msm_pinctrl_remove(struct platform_device *pdev); +int msm_pinctrl_suspend_late(struct device *dev); +int msm_pinctrl_resume_late(struct device *dev); + #endif From patchwork Fri Aug 17 16:38:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10569213 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C55713B6 for ; Fri, 17 Aug 2018 16:39:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5EC032BDCE for ; Fri, 17 Aug 2018 16:39:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 525312BDD8; Fri, 17 Aug 2018 16:39:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E52DD2BDCE for ; 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Fri, 17 Aug 2018 16:39:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1534523958; bh=6flkeC8VwR0A6QppwkUCI0AsDYsAguhrxydU1eExRqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kI6RtZ5tKCkIT1clj4InMHKfszCujEMBbly50A1yehvJMDZIBQqZPiGoEvXqzpRmK 2/uAbc1oCdcb42KvQIFwjRZ64MCUAfJZHiHRQdmr5EXpXuTZaL3kq4PFttwha1g8Cj blk+G6m7kntY5G8rEiJIGtArCbWoEPaI8GmC1QjI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8213062527 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v2 4/5] drivers: pinctrl: qcom: sdm845: support GPIO wakeup from suspend Date: Fri, 17 Aug 2018 10:38:48 -0600 Message-Id: <20180817163849.30750-5-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180817163849.30750-1-ilina@codeaurora.org> References: <20180817163849.30750-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP --- drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 2ab7a8885757..cc333b8afb99 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1297,10 +1297,16 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = { { }, }; +static const struct dev_pm_ops msm_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(msm_pinctrl_suspend_late, + msm_pinctrl_resume_late) +}; + static struct platform_driver sdm845_pinctrl_driver = { .driver = { .name = "sdm845-pinctrl", .of_match_table = sdm845_pinctrl_of_match, + .pm = &msm_pinctrl_dev_pm_ops, }, .probe = sdm845_pinctrl_probe, .remove = msm_pinctrl_remove, From patchwork Fri Aug 17 16:38:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10569215 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 88ACE13B6 for ; Fri, 17 Aug 2018 16:39:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E3442BDCE for ; Fri, 17 Aug 2018 16:39:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 720EB2BDD8; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v2 5/5] arm64: dts: qcom: add wake up interrupts for GPIOs for SDM845 Date: Fri, 17 Aug 2018 10:38:49 -0600 Message-Id: <20180817163849.30750-6-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180817163849.30750-1-ilina@codeaurora.org> References: <20180817163849.30750-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GPIOs that are wakeup capable have interrupt lines that are routed to the always-on interrupt controller (PDC) in parallel to the pinctrl. The interrupts listed here are the wake up lines corresponding to GPIOs. Signed-off-by: Lina Iyer --- Changes in v1: - Use interrupt-extended for all TLMM interrupts - Define GPIO-PDC map using interrupt-names --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 57 +++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 87ffc32dc597..2379684373d3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -712,11 +712,66 @@ tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; reg = <0x03400000 0xc00000>; - interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts-extended = <&intc GIC_SPI 208 0>, + <&pdc 510 0>, <&pdc 511 0>, <&pdc 512 0>, + <&pdc 513 0>, <&pdc 514 0>, <&pdc 515 0>, + <&pdc 516 0>, <&pdc 517 0>, <&pdc 518 0>, + <&pdc 519 0>, <&pdc 632 0>, <&pdc 639 0>, + <&pdc 521 0>, <&pdc 522 0>, <&pdc 523 0>, + <&pdc 524 0>, <&pdc 525 0>, <&pdc 526 0>, + <&pdc 527 0>, <&pdc 630 0>, <&pdc 637 0>, + <&pdc 529 0>, <&pdc 530 0>, <&pdc 531 0>, + <&pdc 532 0>, <&pdc 633 0>, <&pdc 640 0>, + <&pdc 534 0>, <&pdc 535 0>, <&pdc 536 0>, + <&pdc 537 0>, <&pdc 538 0>, <&pdc 539 0>, + <&pdc 540 0>, <&pdc 541 0>, <&pdc 542 0>, + <&pdc 543 0>, <&pdc 544 0>, <&pdc 545 0>, + <&pdc 546 0>, <&pdc 547 0>, <&pdc 548 0>, + <&pdc 549 0>, <&pdc 550 0>, <&pdc 551 0>, + <&pdc 552 0>, <&pdc 553 0>, <&pdc 554 0>, + <&pdc 555 0>, <&pdc 556 0>, <&pdc 557 0>, + <&pdc 631 0>, <&pdc 638 0>, <&pdc 559 0>, + <&pdc 560 0>, <&pdc 561 0>, <&pdc 562 0>, + <&pdc 563 0>, <&pdc 564 0>, <&pdc 565 0>, + <&pdc 566 0>, <&pdc 570 0>, <&pdc 571 0>, + <&pdc 572 0>, <&pdc 573 0>, <&pdc 609 0>, + <&pdc 610 0>, <&pdc 611 0>, <&pdc 612 0>, + <&pdc 613 0>, <&pdc 614 0>, <&pdc 615 0>, + <&pdc 617 0>, <&pdc 618 0>, <&pdc 619 0>, + <&pdc 620 0>, <&pdc 621 0>, <&pdc 622 0>, + <&pdc 623 0>; + interrupt-names = "summary-irq", + "gpio1", "gpio3", "gpio5", + "gpio10", "gpio11", "gpio20", + "gpio22", "gpio24", "gpio26", + "gpio30", "gpio31", "gpio31", + "gpio32", "gpio34", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio41", + "gpio43", "gpio44", "gpio46", + "gpio48", "gpio49", "gpio49", + "gpio52", "gpio53", "gpio54", + "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio64", + "gpio66", "gpio68", "gpio71", + "gpio73", "gpio77", "gpio78", + "gpio79", "gpio80", "gpio84", + "gpio85", "gpio86", "gpio88", + "gpio89", "gpio89", "gpio91", + "gpio92", "gpio95", "gpio96", + "gpio97", "gpio101", "gpio103", + "gpio104", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", + "gpio127", "gpio128", "gpio129", + "gpio130", "gpio132", "gpio133", + "gpio145"; qup_i2c0_default: qup-i2c0-default { pinmux {