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Tue, 7 Jan 2025 10:24:29 -0500 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:24:29 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:24:29 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:24:29 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FOIRD030245; Tue, 7 Jan 2025 10:24:20 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , Subject: [PATCH v1 01/15] dt-bindings: iio: adc: ad7768-1: add synchronization over SPI property Date: Tue, 7 Jan 2025 12:24:18 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: GcvyIF9d3WEjJlgW3fwYz7Hsbrv4QkQB X-Proofpoint-GUID: GcvyIF9d3WEjJlgW3fwYz7Hsbrv4QkQB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 Add adi,sync-in-spi property to enable synchronization over SPI. This should be used in the case when the GPIO cannot provide a pulse synchronous with the base MCLK signal. User can choose between SPI, GPIO synchronization or neither of them, but only if a external pulse can be provided, for example, by another device in a multidevice setup. Signed-off-by: Jonathan Santos --- .../bindings/iio/adc/adi,ad7768-1.yaml | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index 3ce59d4d065f..55cec27bfe60 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -47,6 +47,15 @@ properties: in any way, for example if the filter decimation rate changes. As the line is active low, it should be marked GPIO_ACTIVE_LOW. + adi,sync-in-spi: + description: + Enables synchronization of multiple devices over SPI. This property is + used when a signal synchronous to the base MCLK signal cannot be provided + via GPIO. It requires the SYNC_OUT pin to be connected to the SYNC_IN pin + on the ADC. In the case of multiple devices, the SYNC_OUT pin of one device + should be routed to the SYNC_IN pins of the other devices. + type: boolean + reset-gpios: maxItems: 1 @@ -65,7 +74,6 @@ required: - vref-supply - spi-cpol - spi-cpha - - adi,sync-in-gpios patternProperties: "^channel@([0-9]|1[0-5])$": @@ -89,6 +97,20 @@ patternProperties: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + # adi,sync-in-gpios and adi,sync-in-spi are mutually exclusive (neither is also valid) + - if: + required: + - adi,sync-in-gpios + then: + properties: + adi,sync-in-spi: false + - if: + required: + - adi,sync-in-spi + then: + properties: + adi,sync-in-gpios: false + unevaluatedProperties: false examples: From patchwork Tue Jan 7 15:24:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929155 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4B3A1F1312; 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Tue, 07 Jan 2025 10:24:44 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 507FOhlB033998 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 7 Jan 2025 10:24:43 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:24:43 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:24:43 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FOUvi030254; Tue, 7 Jan 2025 10:24:33 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , Subject: [PATCH v1 02/15] Documentation: ABI: add wideband filter type to sysfs-bus-iio Date: Tue, 7 Jan 2025 12:24:30 -0300 Message-ID: <40707fa904ba7b1659554747ff7520139dd6f94e.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: XTHpWR45dDbaeWH-kxHBY_-by4yzT65X X-Proofpoint-GUID: XTHpWR45dDbaeWH-kxHBY_-by4yzT65X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 The Wideband Low Ripple FIR filter is used for AD7768-1 Driver. Document wideband filter option into filter_type_avaialable attribute. Signed-off-by: Jonathan Santos --- Documentation/ABI/testing/sysfs-bus-iio | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index f83bd6829285..c4c21a7bfba1 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2291,6 +2291,8 @@ Description: * "sinc3+pf2" - Sinc3 + device specific Post Filter 2. * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. + * "wideband" - FIR filter with wideband low ripple passband + and sharp transition band. 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Date: Tue, 7 Jan 2025 12:24:53 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: E05zIRDgxvyjff4Wlf1eF606s-5sdROC X-Proofpoint-GUID: E05zIRDgxvyjff4Wlf1eF606s-5sdROC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 Add ABI documentation specific to the ad7768-1 device, detailing the decimation_rate attribute for better clarity and usability. Signed-off-by: Jonathan Santos --- .../ABI/testing/sysfs-bus-iio-adc-ad7768-1 | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-ad7768-1 diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc-ad7768-1 b/Documentation/ABI/testing/sysfs-bus-iio-adc-ad7768-1 new file mode 100644 index 000000000000..065247f07cfb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-adc-ad7768-1 @@ -0,0 +1,13 @@ +What: /sys/bus/iio/devices/iio:deviceX/decimation_rate_available +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Reading returns a range of possible decimation rate values. + +What: /sys/bus/iio/devices/iio:deviceX/decimation_rate +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Sets up the decimation rate for the digital filter. This can + directly impact in the final sampling frequency. Reading returns + the decimation rate. Writing sets the decimation rate. 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Tue, 7 Jan 2025 10:25:18 -0500 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:25:18 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:25:18 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:25:18 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FP7qD030300; Tue, 7 Jan 2025 10:25:10 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 04/15] iio: adc: ad7768-1: Fix conversion result sign Date: Tue, 7 Jan 2025 12:25:07 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: PMijzN3brPbiQqtfpXxYpesdclUjUwkf X-Proofpoint-GUID: PMijzN3brPbiQqtfpXxYpesdclUjUwkf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 From: Sergiu Cuciurean The ad7768-1 is a fully differential ADC, meaning that the voltage conversion result is a signed value. Since the value is a 24 bit one, stored in a 32 bit variable, the sign should be extended in order to get the correct representation. Also the channel description has been updated to signed representation, to match the ADC specifications. Fixes: a5f8c7da3dbe ("iio: adc: Add AD7768-1 ADC basic support") Signed-off-by: Sergiu Cuciurean Reviewed-by: David Lechner --- drivers/iio/adc/ad7768-1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 113703fb7245..c3cf04311c40 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -142,7 +142,7 @@ static const struct iio_chan_spec ad7768_channels[] = { .channel = 0, .scan_index = 0, .scan_type = { - .sign = 'u', + .sign = 's', .realbits = 24, .storagebits = 32, .shift = 8, @@ -371,7 +371,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, ret = ad7768_scan_direct(indio_dev); if (ret >= 0) - *val = ret; + *val = sign_extend32(ret, chan->scan_type.realbits - 1); iio_device_release_direct_mode(indio_dev); if (ret < 0) From patchwork Tue Jan 7 15:25:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929158 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADD421E47D6; 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Tue, 07 Jan 2025 10:25:36 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 507FPZ2S034073 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 7 Jan 2025 10:25:35 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:25:34 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:25:34 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FPJWY030310; Tue, 7 Jan 2025 10:25:22 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , Subject: [PATCH v1 05/15] iio: adc: ad7768-1: set MOSI idle state to high Date: Tue, 7 Jan 2025 12:25:19 -0300 Message-ID: <714ff48341753de0509208e3c553b19c1c43e480.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: oRhyEW2oLvOUPhK3-XGZCKQ4SQUO8YFF X-Proofpoint-GUID: oRhyEW2oLvOUPhK3-XGZCKQ4SQUO8YFF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 malwarescore=0 mlxlogscore=910 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 All supported parts require that the MOSI line stays high while in idle. Configure SPI controller to set MOSI idle state to high. Fixes: a5f8c7da3dbe ("iio: adc: Add AD7768-1 ADC basic support") Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad7768-1.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index c3cf04311c40..463a28d09c2e 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -574,6 +574,15 @@ static int ad7768_probe(struct spi_device *spi) return -ENOMEM; st = iio_priv(indio_dev); + /* + * The ADC SDI line must be kept high when + * data is not being clocked out of the controller. + * Request the SPI controller to make MOSI idle high. + */ + spi->mode |= SPI_MOSI_IDLE_HIGH; + ret = spi_setup(spi); + if (ret < 0) + return ret; st->spi = spi; st->vref = devm_regulator_get(&spi->dev, "vref"); From patchwork Tue Jan 7 15:25:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929159 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 520161F190C; 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Tue, 7 Jan 2025 10:25:32 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 06/15] iio: adc: ad7768-1: Update reg_read function Date: Tue, 7 Jan 2025 12:25:30 -0300 Message-ID: <4c2d06b873def8a9c3c1d4c8dbc829b655218eca.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: IahLJD8IixJSBedbPvwOpS6Wbs3g4-lL X-Proofpoint-GUID: IahLJD8IixJSBedbPvwOpS6Wbs3g4-lL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 From: Sergiu Cuciurean This patch adds an additional parameter to the register read function. By passing the data pointer to the function, the returned value will used only for status check. With this change, the status check won't be confused with a register value check: ret = ad7768_spi_reg_read() if (ret){} Also this change removes the probability to interpret a negative value as a return code (the ADC is a differential one)." Signed-off-by: Sergiu Cuciurean --- drivers/iio/adc/ad7768-1.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 463a28d09c2e..881446462ff5 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -177,7 +177,7 @@ struct ad7768_state { }; static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, - unsigned int len) + unsigned int *data, unsigned int len) { unsigned int shift; int ret; @@ -190,7 +190,9 @@ static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, if (ret < 0) return ret; - return (be32_to_cpu(st->data.d32) >> shift); + *data = (be32_to_cpu(st->data.d32) >> shift); + + return ret; } static int ad7768_spi_reg_write(struct ad7768_state *st, @@ -206,11 +208,11 @@ static int ad7768_spi_reg_write(struct ad7768_state *st, static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { - int regval; + int ret, regval; - regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); - if (regval < 0) - return regval; + ret = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, ®val, 1); + if (ret < 0) + return ret; regval &= ~AD7768_CONV_MODE_MSK; regval |= AD7768_CONV_MODE(mode); @@ -234,9 +236,9 @@ static int ad7768_scan_direct(struct iio_dev *indio_dev) if (!ret) return -ETIMEDOUT; - readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); - if (readval < 0) - return readval; + ret = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, &readval, 3); + if (ret < 0) + return ret; /* * Any SPI configuration of the AD7768-1 can only be * performed in continuous conversion mode. @@ -258,11 +260,9 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, mutex_lock(&st->lock); if (readval) { - ret = ad7768_spi_reg_read(st, reg, 1); + ret = ad7768_spi_reg_read(st, reg, readval, 1); if (ret < 0) goto err_unlock; - *readval = ret; - ret = 0; } else { ret = ad7768_spi_reg_write(st, reg, writeval); } @@ -515,12 +515,13 @@ static int ad7768_buffer_postenable(struct iio_dev *indio_dev) static int ad7768_buffer_predisable(struct iio_dev *indio_dev) { struct ad7768_state *st = iio_priv(indio_dev); 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Tue, 07 Jan 2025 10:25:56 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 507FPsDM034114 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 7 Jan 2025 10:25:54 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:25:54 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:25:54 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FPhUJ030322; Tue, 7 Jan 2025 10:25:46 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 07/15] iio: adc: ad7768-1: Add reset gpio Date: Tue, 7 Jan 2025 12:25:41 -0300 Message-ID: <45cfd15501384a183a97d871b6848fb79fdb7b39.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: nU8_VnvUeg5aqdSo72N2Zft2Gs_jzfTR X-Proofpoint-GUID: nU8_VnvUeg5aqdSo72N2Zft2Gs_jzfTR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 From: Sergiu Cuciurean Depending on the controller, the default state of a gpio can vary. This change excludes the probability that the dafult state of the ADC reset gpio will be HIGH if it will be passed as reference in the deivcetree. Signed-off-by: Sergiu Cuciurean --- drivers/iio/adc/ad7768-1.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 881446462ff5..f73b9aec8b0f 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -161,6 +161,7 @@ struct ad7768_state { struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; + struct gpio_desc *gpio_reset; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* * DMA (thus cache coherency maintenance) may require the @@ -441,6 +442,18 @@ static int ad7768_setup(struct ad7768_state *st) { int ret; + st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_reset)) + return PTR_ERR(st->gpio_reset); + + if (st->gpio_reset) { + gpiod_direction_output(st->gpio_reset, 1); + usleep_range(10, 15); + gpiod_direction_output(st->gpio_reset, 0); + usleep_range(10, 15); + } + /* * Two writes to the SPI_RESET[1:0] bits are required to initiate * a software reset. The bits must first be set to 11, and then From patchwork Tue Jan 7 15:25:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929161 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 590691F2C5C; Tue, 7 Jan 2025 15:26:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736263583; cv=none; b=ImuYjuUqDqGaoYvpQ4enrIxzWfIv3//R6IQxmk7dZEhTTp1F972kRKLX5Z7fsDxbcKdpPs38tpHXI/Hu+9sBJWY1+sgLTAj/orRU0SbtpVoaDdMcOG/I1VLXzAV56oF2yPgpgyCASQe+7B1LfB30S+IuAEjLx9y0yN5xgTXTIQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736263583; c=relaxed/simple; bh=uvreyaRFtATecQwzX+B3aWbnYMOJICETGlSVhmuPhFU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uBpGFMRZKIyFJiwS/6OTLOguBIp+Oc0rlYDgkO7V9U4GiHW4xnKhaPfAUc4pTROM3AUuJYjOvjMjQE5QelzkkfD/ZS/MQmlRenUKlEYSisLWiDJC01uG/myTrCXGLhwSJVKO+w4koJoaCSjFqGX22CsZ1P/UkpFjnESfhPoHH3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=XiN9jICc; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="XiN9jICc" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 507EvDkB013534; Tue, 7 Jan 2025 10:26:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=J02GL Q1ndy2kqxzkYgt1EGsDeF04uTOSF4FUNv/2LDs=; b=XiN9jICcemtwZUrrrA78F QYnB0AEj4tFxheeQ2V1xqi60oluBUExs6L7I1DYrlP17tobQm7GWV6cWNf+3O0C5 ZC/Bip4JjPlZUakPVxALUUODDh9MjSw2szwk/EbYSh1sH3FA5c5w8066BA1cGNvA MTwLHT0YZdZM0So+tIWbK1RpKqYo7OJOxGzELNzaVP8gG90Pvl5exQh+3+nregk8 pdgjnk2Z1DOa+DGt/HWC3fgbfsraF41YsTTTursXdHu0T4mX+3kBJonxU4cU3rBx zRWFFgBIXFHBL3zK67lxesX8mjZ+xRkfplKz9wSQsVFP7kyyPSn3FtndxHlh+1Py w== Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4415f6gdkd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jan 2025 10:26:08 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 507FQ79h034123 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 7 Jan 2025 10:26:07 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:26:07 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:26:07 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FPstS030327; Tue, 7 Jan 2025 10:25:56 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , Subject: [PATCH v1 08/15] iio: adc: ad7768-1: use guard(mutex) to simplify code Date: Tue, 7 Jan 2025 12:25:53 -0300 Message-ID: <245cce4d379d225ab6794fc3326d95f88d2abf1a.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: wT2uPtP26k5tpIiYzo2FTuLy54G5pDUF X-Proofpoint-GUID: wT2uPtP26k5tpIiYzo2FTuLy54G5pDUF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=940 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 Use guard(mutex) from cleanup.h to remove most of the gotos and to make the code simpler and less likely to fail due to forgetting to unlock the resources. Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad7768-1.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index f73b9aec8b0f..cd1b08053105 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -5,6 +5,7 @@ * Copyright 2017 Analog Devices Inc. */ #include +#include #include #include #include @@ -257,20 +258,12 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, unsigned int *readval) { struct ad7768_state *st = iio_priv(indio_dev); - int ret; - mutex_lock(&st->lock); - if (readval) { - ret = ad7768_spi_reg_read(st, reg, readval, 1); - if (ret < 0) - goto err_unlock; - } else { - ret = ad7768_spi_reg_write(st, reg, writeval); - } -err_unlock: - mutex_unlock(&st->lock); + guard(mutex)(&st->lock); + if (readval) + return ad7768_spi_reg_read(st, reg, readval, 1); - return ret; + return ad7768_spi_reg_write(st, reg, writeval); } static int ad7768_set_dig_fil(struct ad7768_state *st, @@ -484,7 +477,7 @@ static irqreturn_t ad7768_trigger_handler(int irq, void *p) struct ad7768_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&st->lock); + guard(mutex)(&st->lock); ret = spi_read(st->spi, &st->data.scan.chan, 3); if (ret < 0) @@ -495,7 +488,6 @@ static irqreturn_t ad7768_trigger_handler(int irq, void *p) err_unlock: iio_trigger_notify_done(indio_dev->trig); - mutex_unlock(&st->lock); return IRQ_HANDLED; } From patchwork Tue Jan 7 15:26:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929162 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83D4B1F3D47; Tue, 7 Jan 2025 15:26:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736263595; cv=none; b=o9VdEm2NY055n+eW+k9ZfYUdc5wiK3OqwpdpCQpZwMAxXIlki/PHTt//U07nrF2WTxCV4dw1Y1hN3apwKvFnZPyUGl2VNgMBq+SjyY63szwkAKIc6+MSFYBKlMNSeIJX+6Yh5UDNKFm2KY0TtpYlpNk4Uf8PPKtp/xc8f3N9atQ= ARC-Message-Signature: i=1; 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Tue, 7 Jan 2025 10:26:16 -0500 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:26:16 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:26:16 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:26:16 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FQ5A7030330; Tue, 7 Jan 2025 10:26:07 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 09/15] iio: adc: ad7768-1: Move buffer allocation to a separate function Date: Tue, 7 Jan 2025 12:26:05 -0300 Message-ID: <319a685855eb4b942e05e456a37319d3f73f7cd4.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: yZihgdy-52SDcHAa39eePCOSx1adu3RK X-Proofpoint-GUID: yZihgdy-52SDcHAa39eePCOSx1adu3RK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 From: Sergiu Cuciurean This change moves the buffer allocation in a separate function, making space for adding another type of iio buffer if needed. Signed-off-by: Sergiu Cuciurean --- drivers/iio/adc/ad7768-1.c | 64 ++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index cd1b08053105..eaa9a12737ac 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -163,6 +163,7 @@ struct ad7768_state { struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; struct gpio_desc *gpio_reset; + int irq; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* * DMA (thus cache coherency maintenance) may require the @@ -569,6 +570,40 @@ static int ad7768_set_channel_label(struct iio_dev *indio_dev, return 0; } +static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev) +{ + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + + st->trig->ops = &ad7768_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); + if (ret) + return ret; + + indio_dev->trig = iio_trigger_get(st->trig); + + init_completion(&st->completion); + + ret = devm_request_irq(indio_dev->dev.parent, st->irq, + &ad7768_interrupt, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return ret; + + return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, + &iio_pollfunc_store_time, + &ad7768_trigger_handler, + &ad7768_buffer_ops); +} + static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; @@ -610,6 +645,7 @@ static int ad7768_probe(struct spi_device *spi) return PTR_ERR(st->mclk); st->mclk_freq = clk_get_rate(st->mclk); + st->irq = spi->irq; mutex_init(&st->lock); @@ -625,37 +661,11 @@ static int ad7768_probe(struct spi_device *spi) return ret; } - st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", - indio_dev->name, - iio_device_id(indio_dev)); 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Tue, 7 Jan 2025 10:26:20 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 10/15] iio: adc: ad7768-1: Add support for variable VCM Date: Tue, 7 Jan 2025 12:26:17 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: Nu4F-qAZ7SdenbZJKj-X2t7PVwsE__ha X-Proofpoint-GUID: Nu4F-qAZ7SdenbZJKj-X2t7PVwsE__ha X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070129 From: Sergiu Cuciurean The VCM output voltage can be used as a common-mode voltage within the amplifier preconditioning circuits external to the AD7768-1. This change exports the VCM as an iio attribute and makes it available for configuration. Signed-off-by: Sergiu Cuciurean --- drivers/iio/adc/ad7768-1.c | 56 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index eaa9a12737ac..574d735f2c3a 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -119,6 +119,17 @@ struct ad7768_clk_configuration { enum ad7768_pwrmode pwrmode; }; +static const char * const ad7768_vcm_modes[] = { + "(AVDD1-AVSS)/2", + "2V5", + "2V05", + "1V9", + "1V65", + "1V1", + "0V9", + "OFF", +}; + static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, @@ -133,12 +144,34 @@ static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, }; +static int ad7768_get_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan); +static int ad7768_set_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan, + unsigned int mode); + +static const struct iio_enum ad7768_vcm_mode_enum = { + .items = ad7768_vcm_modes, + .num_items = ARRAY_SIZE(ad7768_vcm_modes), + .set = ad7768_set_vcm, + .get = ad7768_get_vcm, +}; + +static struct iio_chan_spec_ext_info ad7768_ext_info[] = { + IIO_ENUM("common_mode_voltage", + IIO_SHARED_BY_ALL, + &ad7768_vcm_mode_enum), + IIO_ENUM_AVAILABLE("common_mode_voltage", + IIO_SHARED_BY_ALL, + &ad7768_vcm_mode_enum), + { }, +}; + static const struct iio_chan_spec ad7768_channels[] = { { .type = IIO_VOLTAGE, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info = ad7768_ext_info, .indexed = 1, .channel = 0, .scan_index = 0, @@ -159,6 +192,7 @@ struct ad7768_state { struct clk *mclk; unsigned int mclk_freq; unsigned int samp_freq; + unsigned int common_mode_voltage; struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; @@ -329,6 +363,28 @@ static int ad7768_set_freq(struct ad7768_state *st, return 0; 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Tue, 07 Jan 2025 10:26:53 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 507FQgvD034165 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 7 Jan 2025 10:26:42 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:26:42 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:26:41 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FQVEK030339; Tue, 7 Jan 2025 10:26:33 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 11/15] iio: adc: ad7768-1: Add reg_write_masked function Date: Tue, 7 Jan 2025 12:26:28 -0300 Message-ID: <67649c43050d161621bc0494638bfa71fed82ea8.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: Zvu3n0tMr1no_BdbUm4xbzgnje13JXIO X-Proofpoint-GUID: Zvu3n0tMr1no_BdbUm4xbzgnje13JXIO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=797 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070130 From: Sergiu Cuciurean This commit adds the ad7768_spi_reg_write_masked() which is a helper function for writing specific bits inside a register, without interfering with the other bit values. Signed-off-by: Sergiu Cuciurean --- drivers/iio/adc/ad7768-1.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 574d735f2c3a..675af9ea856d 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -242,6 +242,21 @@ static int ad7768_spi_reg_write(struct ad7768_state *st, return spi_write(st->spi, st->data.d8, 2); } +static int ad7768_spi_reg_write_masked(struct ad7768_state *st, + unsigned int addr, + unsigned int mask, + unsigned int val) +{ + unsigned int reg_val; + int ret; + + ret = ad7768_spi_reg_read(st, addr, ®_val, 1); + if (ret < 0) + return ret; + + return ad7768_spi_reg_write(st, addr, (reg_val & ~mask) | val); +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { From patchwork Tue Jan 7 15:26:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929165 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8650F1F3D5E; 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Tue, 7 Jan 2025 10:26:44 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , Subject: [PATCH v1 12/15] iio: adc: ad7768-1: Add GPIO controller support Date: Tue, 7 Jan 2025 12:26:41 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: yQTgyGMnjppiQwz-ID8p22OaOqKOU_I6 X-Proofpoint-GUID: yQTgyGMnjppiQwz-ID8p22OaOqKOU_I6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070130 From: Sergiu Cuciurean The AD7768-1 has the ability to control other local hardware (such as gain stages),to power down other blocks in the signal chain, or read local status signals over the SPI interface. This change exports the AD7768-1's four gpios and makes them accessible at an upper layer. Signed-off-by: Sergiu Cuciurean --- drivers/iio/adc/ad7768-1.c | 121 +++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 675af9ea856d..9741a6d47942 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -77,6 +79,19 @@ #define AD7768_CONV_MODE_MSK GENMASK(2, 0) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) +/* AD7768_REG_GPIO_CONTROL */ +#define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) +#define AD7768_GPIO_UNIVERSAL_EN BIT(7) + +/* AD7768_REG_GPIO_WRITE */ +#define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_READ */ +#define AD7768_GPIO_READ_MSK GENMASK(3, 0) + +#define AD7768_GPIO_INPUT(x) 0x00 +#define AD7768_GPIO_OUTPUT(x) BIT(x) + #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) @@ -190,6 +205,8 @@ struct ad7768_state { struct regulator *vref; struct mutex lock; struct clk *mclk; + struct gpio_chip gpiochip; + unsigned int gpio_avail_map; unsigned int mclk_freq; unsigned int samp_freq; unsigned int common_mode_voltage; @@ -338,6 +355,106 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return 0; } +static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct ad7768_state *st = gpiochip_get_data(chip); + + guard(mutex)(&st->lock); + return ad7768_spi_reg_write_masked(st, + AD7768_REG_GPIO_CONTROL, + BIT(offset), + AD7768_GPIO_INPUT(offset)); +} + +static int ad7768_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ad7768_state *st = gpiochip_get_data(chip); + + guard(mutex)(&st->lock); + return ad7768_spi_reg_write_masked(st, + AD7768_REG_GPIO_CONTROL, + BIT(offset), + AD7768_GPIO_OUTPUT(offset)); +} + +static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ad7768_state *st = gpiochip_get_data(chip); + unsigned int val; + int ret; + + guard(mutex)(&st->lock); + ret = ad7768_spi_reg_read(st, AD7768_REG_GPIO_CONTROL, &val, 1); + if (ret < 0) + return ret; + + if (val & BIT(offset)) + ret = ad7768_spi_reg_read(st, AD7768_REG_GPIO_WRITE, &val, 1); + else + ret = ad7768_spi_reg_read(st, AD7768_REG_GPIO_READ, &val, 1); + if (ret < 0) + return ret; + + return !!(val & BIT(offset)); +} + +static void ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct ad7768_state *st = gpiochip_get_data(chip); + unsigned int val; + int ret; + + guard(mutex)(&st->lock); + ret = ad7768_spi_reg_read(st, AD7768_REG_GPIO_CONTROL, &val, 1); + if (ret < 0) + return; + + if (val & BIT(offset)) + ad7768_spi_reg_write_masked(st, + AD7768_REG_GPIO_WRITE, + BIT(offset), + (value << offset)); +} + +static int ad7768_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct ad7768_state *st = gpiochip_get_data(chip); + + if (!(st->gpio_avail_map & BIT(offset))) + return -ENODEV; + + st->gpio_avail_map &= ~BIT(offset); + + return 0; +} + +static int ad7768_gpio_init(struct ad7768_state *st) +{ + int ret; + + ret = ad7768_spi_reg_write(st, + AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UNIVERSAL_EN); + if (ret < 0) + return ret; + + st->gpio_avail_map = AD7768_GPIO_CONTROL_MSK; + st->gpiochip.label = "ad7768_1_gpios"; + st->gpiochip.base = -1; + st->gpiochip.ngpio = 4; + st->gpiochip.parent = &st->spi->dev; + st->gpiochip.can_sleep = true; + st->gpiochip.direction_input = ad7768_gpio_direction_input; + st->gpiochip.direction_output = ad7768_gpio_direction_output; + st->gpiochip.get = ad7768_gpio_get; + st->gpiochip.set = ad7768_gpio_set; + st->gpiochip.request = ad7768_gpio_request; + st->gpiochip.owner = THIS_MODULE; + + return gpiochip_add_data(&st->gpiochip, st); +} + static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { @@ -538,6 +655,10 @@ static int ad7768_setup(struct ad7768_state *st) if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); + ret = ad7768_gpio_init(st); + if (ret < 0) + return ret; + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } From patchwork Tue Jan 7 15:26:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929166 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFEBF1F3D35; Tue, 7 Jan 2025 15:27:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736263643; cv=none; b=DrNSHGd/mTzQLv3gBondwiV5a1Kgbx+gtxtgkKrlwLNcC885M5MLa87FKdihrFuXEG2uyBjooCmvB6OuT/ABc6ylsKnt8L0nIZseAWePHcNSgKcgSsUneISbcZctPY/CGCVDwtPteUE8ZXz2950wZAOCvYLdl4OszUo/7ZuVhOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 7 Jan 2025 10:27:04 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:27:04 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:27:04 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:27:04 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FQrtM030347; Tue, 7 Jan 2025 10:26:55 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , Subject: [PATCH v1 13/15] iio: adc: ad7768-1: add multiple scan types to support 16-bits mode Date: Tue, 7 Jan 2025 12:26:53 -0300 Message-ID: <170c5ca1b6c45b2114f248d9085588572d6269b4.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: nNKG1ntmzmcYkbyTRwQzORS6vUYjDtYD X-Proofpoint-GUID: nNKG1ntmzmcYkbyTRwQzORS6vUYjDtYD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070130 When the device is configured to Sinc5 filter and decimation x8, output data is reduced to 16-bits in order to support 1 MHz of sampling frequency due to clock limitation. Use multiple scan types feature to enable the driver to switch scan type in runtime, making possible to support both 24-bit and 16-bit resolution. Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad7768-1.c | 65 ++++++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 9741a6d47942..5e4e7d387f9a 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -134,6 +134,11 @@ struct ad7768_clk_configuration { enum ad7768_pwrmode pwrmode; }; +enum ad7768_scan_type { + AD7768_SCAN_TYPE_NORMAL, + AD7768_SCAN_TYPE_HIGH_SPEED, +}; + static const char * const ad7768_vcm_modes[] = { "(AVDD1-AVSS)/2", "2V5", @@ -145,6 +150,10 @@ static const char * const ad7768_vcm_modes[] = { "OFF", }; +static const int ad7768_mclk_div_rates[4] = { + 16, 8, 4, 2, +}; + static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, @@ -159,6 +168,21 @@ static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, }; +static const struct iio_scan_type ad7768_scan_type[] = { + [AD7768_SCAN_TYPE_NORMAL] = { + .sign = 's', + .realbits = 24, + .storagebits = 32, + .endianness = IIO_BE, + }, + [AD7768_SCAN_TYPE_HIGH_SPEED] = { + .sign = 's', + .realbits = 16, + .storagebits = 32, + .endianness = IIO_BE, + }, +}; + static int ad7768_get_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan); static int ad7768_set_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan, unsigned int mode); @@ -190,13 +214,9 @@ static const struct iio_chan_spec ad7768_channels[] = { .indexed = 1, .channel = 0, .scan_index = 0, - .scan_type = { - .sign = 's', - .realbits = 24, - .storagebits = 32, - .shift = 8, - .endianness = IIO_BE, - }, + .has_ext_scan_type = 1, + .ext_scan_type = ad7768_scan_type, + .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), }, }; @@ -208,6 +228,7 @@ struct ad7768_state { struct gpio_chip gpiochip; unsigned int gpio_avail_map; unsigned int mclk_freq; + unsigned int dec_rate; unsigned int samp_freq; unsigned int common_mode_voltage; struct completion completion; @@ -308,6 +329,15 @@ static int ad7768_scan_direct(struct iio_dev *indio_dev) ret = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, &readval, 3); if (ret < 0) return ret; + + /* + * When the decimation rate is set to x8, the ADC data precision is reduced + * from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA register provides + * 24-bit data, the precision is reduced by right-shifting the read value + * by 8 bits. + */ + if (st->dec_rate == 8) + readval = readval >> 8; /* * Any SPI configuration of the AD7768-1 can only be * performed in continuous conversion mode. @@ -489,6 +519,8 @@ static int ad7768_set_freq(struct ad7768_state *st, if (ret < 0) return ret; + st->dec_rate = ad7768_clk_config[idx].clk_div / + ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, ad7768_clk_config[idx].clk_div); @@ -544,8 +576,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long info) { struct ad7768_state *st = iio_priv(indio_dev); + const struct iio_scan_type *scan_type; int scale_uv, ret; + scan_type = iio_get_current_scan_type(indio_dev, chan); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + switch (info) { case IIO_CHAN_INFO_RAW: ret = iio_device_claim_direct_mode(indio_dev); @@ -554,7 +591,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, ret = ad7768_scan_direct(indio_dev); if (ret >= 0) - *val = sign_extend32(ret, chan->scan_type.realbits - 1); + *val = sign_extend32(ret, scan_type->realbits - 1); iio_device_release_direct_mode(indio_dev); if (ret < 0) @@ -568,7 +605,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return scale_uv; *val = (scale_uv * 2) / 1000; - *val2 = chan->scan_type.realbits; + *val2 = scan_type->realbits; return IIO_VAL_FRACTIONAL_LOG2; @@ -612,11 +649,21 @@ static const struct attribute_group ad7768_group = { .attrs = ad7768_attributes, }; +static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st = iio_priv(indio_dev); + + return st->dec_rate == 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : + AD7768_SCAN_TYPE_NORMAL; +} + static const struct iio_info ad7768_info = { .attrs = &ad7768_group, .read_raw = &ad7768_read_raw, .write_raw = &ad7768_write_raw, .read_label = ad7768_read_label, + .get_current_scan_type = &ad7768_get_current_scan_type, .debugfs_reg_access = &ad7768_reg_access, }; From patchwork Tue Jan 7 15:27:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13929167 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B4C41F2C3D; Tue, 7 Jan 2025 15:27:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736263655; cv=none; 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Tue, 07 Jan 2025 10:27:18 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 507FRHM9034201 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 7 Jan 2025 10:27:17 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Tue, 7 Jan 2025 10:27:16 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:27:16 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FR4Ln030355; Tue, 7 Jan 2025 10:27:06 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , Subject: [PATCH v1 14/15] iio: adc: ad7768-1: add support for Synchronization over SPI Date: Tue, 7 Jan 2025 12:27:03 -0300 Message-ID: <0f9a15e6e2e6b7b2c82ef79d8cb883d9eb6c55dd.1736201898.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: ggKlIxymNY-OcA9FHT-alpdVGCNtTGHn X-Proofpoint-GUID: ggKlIxymNY-OcA9FHT-alpdVGCNtTGHn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070130 The synchronization method using GPIO requires the generated pulse to be truly synchronous with the base MCLK signal. When it is not possible to do that in hardware, the datasheet recommends using synchronization over SPI, where the generated pulse is already synchronous with MCLK. This requires the SYNC_OUT pin to be connected to SYNC_IN pin. Add the option to handle device synchronization over SPI. Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad7768-1.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 5e4e7d387f9a..0b0cb3b396ff 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -235,6 +235,7 @@ struct ad7768_state { struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; struct gpio_desc *gpio_reset; + bool en_spi_sync; int irq; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* @@ -295,6 +296,19 @@ static int ad7768_spi_reg_write_masked(struct ad7768_state *st, return ad7768_spi_reg_write(st, addr, (reg_val & ~mask) | val); } +static int ad7768_send_sync_pulse(struct ad7768_state *st) +{ + if (st->en_spi_sync) + return ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x00); + + if (st->gpio_sync_in) { + gpiod_set_value_cansleep(st->gpio_sync_in, 1); + gpiod_set_value_cansleep(st->gpio_sync_in, 0); + } + + return 0; +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -379,10 +393,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return ret; /* A sync-in pulse is required every time the filter dec rate changes */ - gpiod_set_value(st->gpio_sync_in, 1); - gpiod_set_value(st->gpio_sync_in, 0); - - return 0; + return ad7768_send_sync_pulse(st); } static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) @@ -697,11 +708,21 @@ static int ad7768_setup(struct ad7768_state *st) if (ret) return ret; - st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", - GPIOD_OUT_LOW); + st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", + GPIOD_OUT_LOW); if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); + if (device_property_present(&st->spi->dev, "adi,sync-in-spi")) + st->en_spi_sync = true; + + /* + * GPIO and SPI Synchronization are mutually exclusive. + * Return error if both are enabled + */ + if (st->gpio_sync_in && st->en_spi_sync) + return -EINVAL; + ret = ad7768_gpio_init(st); if (ret < 0) return ret; From patchwork Tue Jan 7 15:27:14 2025 Content-Type: text/plain; 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Tue, 7 Jan 2025 10:27:27 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Tue, 7 Jan 2025 10:27:27 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 507FREPc030360; Tue, 7 Jan 2025 10:27:17 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , PopPaul2021 Subject: [PATCH v1 15/15] iio: adc: ad7768-1: add filter type and decimation rate attributes Date: Tue, 7 Jan 2025 12:27:14 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: yrTqi__9hFnjA_4vyyHUj7siBWqfjx0G X-Proofpoint-GUID: yrTqi__9hFnjA_4vyyHUj7siBWqfjx0G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070130 Separate filter type and decimation rate from the sampling frequency attribute. The new filter type attribute enables SINC3 and WIDEBAND filters, which were previously unavailable. Previously, combining decimation and MCLK divider in the sampling frequency obscured performance trade-offs. Lower MCLK divider settings increase power usage, while lower decimation rates reduce precision by decreasing averaging. By creating a decimation attribute, users gain finer control over performance. The addition of those attributes allows a wider range of sampling frequencies and more access to the device features. Co-developed-by: PopPaul2021 Signed-off-by: PopPaul2021 Signed-off-by: Jonathan Santos --- drivers/iio/adc/ad7768-1.c | 429 +++++++++++++++++++++++++++++++------ 1 file changed, 366 insertions(+), 63 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 0b0cb3b396ff..842acef1410d 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -17,6 +17,7 @@ #include #include #include +#include "linux/util_macros.h" #include #include @@ -75,6 +76,10 @@ #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) +/* AD7768_SINC3_DEC_RATE */ +#define AD7768_SINC3_DEC_RATE_MSB_MSK GENMASK(12, 8) +#define AD7768_SINC3_DEC_RATE_LSB_MSK GENMASK(7, 0) + /* AD7768_REG_CONVERSION */ #define AD7768_CONV_MODE_MSK GENMASK(2, 0) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) @@ -95,6 +100,18 @@ #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) +/* Decimation Rate Limits */ +#define SINC5_DEC_RATE_MIN 8 +#define SINC5_DEC_RATE_MAX 1024 +#define SINC3_DEC_RATE_MIN 32 +#define SINC3_DEC_RATE_MAX 163840 +#define WIDEBAND_DEC_RATE_MIN 32 +#define WIDEBAND_DEC_RATE_MAX 1024 + +enum { + DEC_RATE, +}; + enum ad7768_conv_mode { AD7768_CONTINUOUS, AD7768_ONE_SHOT, @@ -116,22 +133,12 @@ enum ad7768_mclk_div { AD7768_MCLK_DIV_2 }; -enum ad7768_dec_rate { - AD7768_DEC_RATE_32 = 0, - AD7768_DEC_RATE_64 = 1, - AD7768_DEC_RATE_128 = 2, - AD7768_DEC_RATE_256 = 3, - AD7768_DEC_RATE_512 = 4, - AD7768_DEC_RATE_1024 = 5, - AD7768_DEC_RATE_8 = 9, - AD7768_DEC_RATE_16 = 10 -}; - -struct ad7768_clk_configuration { - enum ad7768_mclk_div mclk_div; - enum ad7768_dec_rate dec_rate; - unsigned int clk_div; - enum ad7768_pwrmode pwrmode; +enum ad7768_flt_type { + SINC5, + SINC5_DEC_X8, + SINC5_DEC_X16, + SINC3, + WIDEBAND }; enum ad7768_scan_type { @@ -154,18 +161,16 @@ static const int ad7768_mclk_div_rates[4] = { 16, 8, 4, 2, }; -static const struct ad7768_clk_configuration ad7768_clk_config[] = { - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, +static const int dec_rate_values[6] = { + 32, 64, 128, 256, 512, 1024, +}; + +static const int sinc3_dec_rate_max_values[4] = { + 20480, 40960, 81920, 163840, +}; + +static const char * const ad7768_filter_enum[] = { + "sinc5", "sinc3", "wideband" }; static const struct iio_scan_type ad7768_scan_type[] = { @@ -186,6 +191,23 @@ static const struct iio_scan_type ad7768_scan_type[] = { static int ad7768_get_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan); static int ad7768_set_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan, unsigned int mode); +static int ad7768_get_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan); +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, unsigned int filter); +static ssize_t ad7768_ext_info_write(struct iio_dev *indio_dev, + uintptr_t private, const struct iio_chan_spec *chan, + const char *buf, size_t len); +static ssize_t ad7768_ext_info_read(struct iio_dev *indio_dev, + uintptr_t private, const struct iio_chan_spec *chan, + char *buf); + +static const struct iio_enum ad7768_flt_type_iio_enum = { + .items = ad7768_filter_enum, + .num_items = ARRAY_SIZE(ad7768_filter_enum), + .set = ad7768_set_fil_type_attr, + .get = ad7768_get_fil_type_attr, +}; static const struct iio_enum ad7768_vcm_mode_enum = { .items = ad7768_vcm_modes, @@ -201,6 +223,15 @@ static struct iio_chan_spec_ext_info ad7768_ext_info[] = { IIO_ENUM_AVAILABLE("common_mode_voltage", IIO_SHARED_BY_ALL, &ad7768_vcm_mode_enum), + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_flt_type_iio_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_flt_type_iio_enum), + { + .name = "decimation_rate", + .read = ad7768_ext_info_read, + .write = ad7768_ext_info_write, + .shared = IIO_SHARED_BY_ALL, + .private = DEC_RATE, + }, { }, }; @@ -228,7 +259,9 @@ struct ad7768_state { struct gpio_chip gpiochip; unsigned int gpio_avail_map; unsigned int mclk_freq; + unsigned int mclk_div; unsigned int dec_rate; + enum ad7768_flt_type filter_type; unsigned int samp_freq; unsigned int common_mode_voltage; struct completion completion; @@ -252,6 +285,9 @@ struct ad7768_state { } data __aligned(IIO_DMA_MINALIGN); }; +static int ad7768_set_freq(struct ad7768_state *st, + unsigned int freq); + static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, unsigned int *data, unsigned int len) { @@ -309,6 +345,31 @@ static int ad7768_send_sync_pulse(struct ad7768_state *st) return 0; } +static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) +{ + unsigned int mclk_div_value; + int ret; + + guard(mutex)(&st->lock); + ret = ad7768_spi_reg_read(st, AD7768_REG_POWER_CLOCK, &mclk_div_value, 1); + if (ret) + return ret; + + mclk_div_value &= ~(AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK); + /* Set mclk_div value */ + mclk_div_value |= AD7768_PWR_MCLK_DIV(mclk_div); + /* + * Set power mode based on mclk_div value. + * ECO_MODE is only recommended for MCLK_DIV 16 + */ + if (mclk_div > AD7768_MCLK_DIV_16) + mclk_div_value |= AD7768_PWR_PWRMODE(AD7768_FAST_MODE); + else + mclk_div_value |= AD7768_PWR_PWRMODE(AD7768_ECO_MODE); + + return ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, mclk_div_value); +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -377,23 +438,185 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, return ad7768_spi_reg_write(st, reg, writeval); } -static int ad7768_set_dig_fil(struct ad7768_state *st, - enum ad7768_dec_rate dec_rate) +static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, + unsigned int dec_rate) +{ + unsigned int dec_rate_msb, dec_rate_lsb, max_dec_rate; + int ret; + + guard(mutex)(&st->lock); + /* + * Maximum dec_rate is limited by the MCLK_DIV value + * and by the ODR. The edge case is for MCLK_DIV = 2 + * ODR = 50 SPS. + * max_dec_rate <= MCLK / (2 * 50) + */ + max_dec_rate = st->mclk_freq / 100; + dec_rate = clamp_t(unsigned int, dec_rate, 32, max_dec_rate); + /* + * Calculate the equivalent value to sinc3 decimation ratio + * to be written on the SINC3_DECIMATION_RATE register: + * Value = (DEC_RATE / 32) -1 + */ + dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; + dec_rate_msb = FIELD_GET(AD7768_SINC3_DEC_RATE_MSB_MSK, dec_rate); + dec_rate_lsb = FIELD_GET(AD7768_SINC3_DEC_RATE_LSB_MSK, dec_rate); + + ret = ad7768_spi_reg_write(st, AD7768_REG_SINC3_DEC_RATE_MSB, dec_rate_msb); + if (ret) + return ret; + + ret = ad7768_spi_reg_write(st, AD7768_REG_SINC3_DEC_RATE_LSB, dec_rate_lsb); + if (ret) + return ret; + + st->dec_rate = (dec_rate + 1) * 32; + + return 0; +} + +static int ad7768_set_dec_rate(struct ad7768_state *st, unsigned int dec_rate) { + unsigned int mode, dec_rate_reg; + int ret; + + dec_rate_reg = find_closest(dec_rate, dec_rate_values, + ARRAY_SIZE(dec_rate_values)); + + guard(mutex)(&st->lock); + ret = ad7768_spi_reg_read(st, AD7768_REG_DIGITAL_FILTER, &mode, 1); + if (ret) + return ret; + + mode &= ~AD7768_DIG_FIL_DEC_MSK; + mode |= AD7768_DIG_FIL_DEC_RATE(dec_rate_reg); + ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); + if (ret) + return ret; + + st->dec_rate = dec_rate_values[dec_rate_reg]; + + return 0; +} + +static int ad7768_set_filter_type(struct iio_dev *dev, + enum ad7768_flt_type filter_type) +{ + struct ad7768_state *st = iio_priv(dev); unsigned int mode; int ret; - if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) - mode = AD7768_DIG_FIL_FIL(dec_rate); - else - mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); + guard(mutex)(&st->lock); + ret = ad7768_spi_reg_read(st, AD7768_REG_DIGITAL_FILTER, &mode, 1); + if (ret) + return ret; + + mode &= ~AD7768_DIG_FIL_FIL_MSK; + mode |= AD7768_DIG_FIL_FIL(filter_type); ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); if (ret < 0) return ret; - /* A sync-in pulse is required every time the filter dec rate changes */ - return ad7768_send_sync_pulse(st); + st->filter_type = filter_type; + + return 0; +} + +static int ad7768_configure_dig_fil(struct iio_dev *dev, + enum ad7768_flt_type filter_type, + unsigned int dec_rate) +{ + struct ad7768_state *st = iio_priv(dev); + int ret; + + if (filter_type == SINC3) { + ret = ad7768_set_filter_type(dev, SINC3); + if (ret) + return ret; + + /* recalculate the decimation for this filter mode */ + ret = ad7768_set_sinc3_dec_rate(st, dec_rate); + } else if (filter_type == WIDEBAND) { + ret = ad7768_set_filter_type(dev, filter_type); + if (ret) + return ret; + + /* recalculate the decimation rate */ + ret = ad7768_set_dec_rate(st, dec_rate); + } else { + /* For SINC5 filter */ + /* Decimation 8 and 16 are set in the digital filter field */ + if (dec_rate <= 8) { + ret = ad7768_set_filter_type(dev, SINC5_DEC_X8); + if (ret) + return ret; + + st->dec_rate = 8; + } else if (dec_rate <= 16) { + ret = ad7768_set_filter_type(dev, SINC5_DEC_X16); + if (ret) + return ret; + + st->dec_rate = 16; + } else { + ret = ad7768_set_filter_type(dev, SINC5); + if (ret) + return ret; + + ret = ad7768_set_dec_rate(st, dec_rate); + } + } + + /* Update scale table: scale values vary according to the precision */ + ad7768_fill_scale_tbl(dev); + + return ret; +} + +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int filter) +{ + struct ad7768_state *st = iio_priv(dev); + int ret; + + /* + * Filters of types 0, 1, and 2 correspond to SINC5. + * For SINC3 and wideband filter types, an offset of 2 is added + * to align with the expected register values. + */ + if (filter != SINC5) + filter += 2; + + ret = ad7768_configure_dig_fil(dev, filter, st->dec_rate); + if (ret) + return ret; + + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); +} + +static int ad7768_get_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st = iio_priv(dev); + int ret; + unsigned int mode; + + ret = ad7768_spi_reg_read(st, AD7768_REG_DIGITAL_FILTER, &mode, 1); + if (ret) + return ret; + + mode = FIELD_GET(AD7768_DIG_FIL_FIL_MSK, mode); + /* Filter types from 0 to 2 are represented as SINC5 */ + if (mode < SINC3) + return SINC5; + + /* Remove the offset for the sinc3 and wideband filters + * to get the corresponding attribute enum value + */ + return mode - 2; } static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) @@ -496,46 +719,84 @@ static int ad7768_gpio_init(struct ad7768_state *st) return gpiochip_add_data(&st->gpiochip, st); } +static ssize_t ad7768_ext_info_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, char *buf) +{ + struct ad7768_state *st = iio_priv(indio_dev); + + switch (private) { + case DEC_RATE: + return sysfs_emit(buf, "%d\n", st->dec_rate); + default: + return -EINVAL; + } +} + +static ssize_t ad7768_ext_info_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + int ret = -EINVAL; + long long dec_rate; + struct ad7768_state *st = iio_priv(indio_dev); + + switch (private) { + case DEC_RATE: + ret = kstrtoll(buf, 10, &dec_rate); + if (ret) + return ret; + + ret = ad7768_configure_dig_fil(indio_dev, st->filter_type, dec_rate); + if (ret) + return ret; + + /* Update sampling frequency */ + ret = ad7768_set_freq(st, st->samp_freq); + if (ret) + return ret; + + return len; + default: + return -EINVAL; + } +} + static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { - unsigned int diff_new, diff_old, pwr_mode, i, idx; + unsigned int diff_new, diff_old, i, idx; int res, ret; + freq = clamp_t(unsigned int, freq, 50, 1024000); diff_old = U32_MAX; idx = 0; - res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); + if (freq == 0) + return -EINVAL; + + res = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->dec_rate); /* Find the closest match for the desired sampling frequency */ - for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - diff_new = abs(res - ad7768_clk_config[i].clk_div); + for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + diff_new = abs(res - ad7768_mclk_div_rates[i]); if (diff_new < diff_old) { diff_old = diff_new; idx = i; } } - /* - * Set both the mclk_div and pwrmode with a single write to the - * POWER_CLOCK register - */ - pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | - AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); - ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); - if (ret < 0) - return ret; - - ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); - if (ret < 0) + /* Set both the mclk_div and pwrmode */ + ret = ad7768_set_mclk_div(st, idx); + if (ret) return ret; - st->dec_rate = ad7768_clk_config[idx].clk_div / - ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[idx].clk_div); + ad7768_mclk_div_rates[idx] * st->dec_rate); - return 0; + /* A sync-in pulse is required every time the filter dec rate changes */ + return ad7768_send_sync_pulse(st); } static int ad7768_get_vcm(struct iio_dev *dev, const struct iio_chan_spec *chan) @@ -566,13 +827,16 @@ static ssize_t ad7768_sampling_freq_avail(struct device *dev, { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ad7768_state *st = iio_priv(indio_dev); - unsigned int freq; + unsigned int freq, freq_filtered; int i, len = 0; - for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - freq = DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[i].clk_div); - len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); + freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->dec_rate); + for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + freq = DIV_ROUND_CLOSEST(freq_filtered, + ad7768_mclk_div_rates[i]); + /* Sampling frequency cannot be lower than the minimum of 50 SPS */ + if (freq >= 50) + len += sysfs_emit_at(buf, len, "%d ", freq); } buf[len - 1] = '\n'; @@ -582,6 +846,38 @@ static ssize_t ad7768_sampling_freq_avail(struct device *dev, static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); +static ssize_t decimation_rate_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct ad7768_state *st = iio_priv(indio_dev); + int len = 0; + + /* Return decimation rate available in range format */ + buf[len++] = '['; + if (st->filter_type == SINC3) { + len += sysfs_emit_at(buf, len, "%d ", SINC3_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC3_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC3_DEC_RATE_MAX); + } else if (st->filter_type == WIDEBAND) { + len += sysfs_emit_at(buf, len, "%d ", WIDEBAND_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", WIDEBAND_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", WIDEBAND_DEC_RATE_MAX); + } else { + len += sysfs_emit_at(buf, len, "%d ", SINC5_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC5_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC5_DEC_RATE_MAX); + } + + buf[len - 1] = ']'; + buf[len++] = '\n'; + + return len; +} + +static IIO_DEVICE_ATTR_RO(decimation_rate_available, 0); + static int ad7768_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -653,6 +949,7 @@ static int ad7768_read_label(struct iio_dev *indio_dev, static struct attribute *ad7768_attributes[] = { &iio_dev_attr_sampling_frequency_available.dev_attr.attr, + &iio_dev_attr_decimation_rate_available.dev_attr.attr, NULL }; @@ -678,7 +975,7 @@ static const struct iio_info ad7768_info = { .debugfs_reg_access = &ad7768_reg_access, }; -static int ad7768_setup(struct ad7768_state *st) +static int ad7768_setup(struct ad7768_state *st, struct iio_dev *indio_dev) { int ret; @@ -727,6 +1024,12 @@ static int ad7768_setup(struct ad7768_state *st) if (ret < 0) return ret; + /* + * Set Default Digital Filter configuration: + * SINC5 filter with x32 Decimation rate + */ + ret = ad7768_configure_dig_fil(indio_dev, SINC5, 32); + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } @@ -915,7 +1218,7 @@ static int ad7768_probe(struct spi_device *spi) indio_dev->info = &ad7768_info; indio_dev->modes = INDIO_DIRECT_MODE; - ret = ad7768_setup(st); + ret = ad7768_setup(st, indio_dev); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); return ret;