From patchwork Tue Jan 7 18:14:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13929485 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA9951F37DD for ; Tue, 7 Jan 2025 18:15:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273727; cv=none; b=sPL1RfXidWEb2Ib+nrZ+46DRId8XfR+NpOwzd00bVNK/p7qWD8a0OhD0jYUSPBQQlyVotMj83yxyaimASO0pmoTaVqtpmvxbqQNFSTjKRrux6+nByKFxRi6mj/KHK4KvWh2fHKxaGcY0UNxkhiZSEKcb6kMJZpdSYFwDaqzeVU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273727; c=relaxed/simple; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Uvxq5/jfSUOt/na/R/UIxVSIgpm6RWDrXY5qD/QeENwo9OzOMGesX5JewNlpHNxQHRLvg72Z9+0whTlcOFef6CiRRa1MuIs4BBwyfacgvU6ThuPPdk5bxHnBhIi5hWlTgSrmOzuwO3IQiuMQcaBmm6tvlYNN2meWz6lpsRh8WE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NMPnLP34; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NMPnLP34" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 141E6C4CEDD; Tue, 7 Jan 2025 18:15:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736273727; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NMPnLP34DOZawutaJ3CmChQ3Br7I3ncUAezk/+g2POCBOX5EfpseJhwXqh26VMuEq Vjed1CAaz2cj/Pj4g1tEC/ZZuFElrzN4vI4s6+UIweh/IsfpBkf6AMLwoyTpM18UkG 2gQJnas7LAqqK61NP6mJ7VGEPBDrchgfaE1cOiceIoPqJFFsSHdVmwf8MwIl4WeG51 4ZlkTM8KN40ng3Jfu4uE0Mg1VJ+p5QZ87/mdUwr+RU/0SDGNVyVyS7bA6IUm5EpMTL vP5LwcbTCH+g0vlJN99156hND6enzcl17qJ1cYcINdWD3jshfzi2JvXKzTDca40cCG yqhhq5cELgWEw== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 1/6] PCI: endpoint: Add BAR type BAR_RESIZABLE Date: Tue, 7 Jan 2025 19:14:51 +0100 Message-ID: <20250107181450.3182430-9-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250107181450.3182430-8-cassel@kernel.org> References: <20250107181450.3182430-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3008; i=cassel@kernel.org; h=from:subject; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJr8+W3zEn4GayaHO+wSO/dtIvfyh195rac7jqq/Wj2W rMXVY1TOkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjARmy2MDPdaHl0x1/ypfCXv FtflMNuS+hdHYvOvZG4RzXRMM5olF8jwh19n69dNBeI331hOiDH8dOHM1TrXfX9u8eqkrl7oJ+D 2hgMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A resizable BAR is different from a normal BAR in a few ways: -The minimum size of a resizable BAR is 1 MB. -Each BAR that is resizable has a Capability and Control register in the Resizable BAR Capability structure. These registers contain the supported sizes and the currently selected size of a resizable BAR. The supported sizes is a bitmap of the supported sizes. The selected size is a single value that is equal to one of the supported sizes. A resizable BAR thus has to be configured differently than a BAR_PROGRAMMABLE BAR, which usually sets the BAR size/mask in a vendor specific way. The PCI endpoint framework currently does not support resizable BARs. Add a BAR type BAR_RESIZABLE, so that an EPC driver can support resizable BARs properly. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, an EPC driver will be able to support resizable BARs (we intentionally only support a single supported resizable BAR size). Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epf-core.c | 4 ++++ include/linux/pci-epc.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 50bc2892a36c..394395c7f8de 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -274,6 +274,10 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, if (size < 128) size = 128; + /* According to PCIe base spec, min size for a resizable BAR is 1 MB. */ + if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M) + size = SZ_1M; + if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) { if (size > bar_fixed_size) { dev_err(&epf->dev, diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index e818e3fdcded..e9d5ed23914f 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -188,11 +188,14 @@ struct pci_epc { * enum pci_epc_bar_type - configurability of endpoint BAR * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC. * @BAR_FIXED: The BAR mask is fixed by the hardware. + * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability. + * An EPC driver can currently only set a single supported size. * @BAR_RESERVED: The BAR should not be touched by an EPF driver. */ enum pci_epc_bar_type { BAR_PROGRAMMABLE = 0, BAR_FIXED, + BAR_RESIZABLE, BAR_RESERVED, }; From patchwork Tue Jan 7 18:14:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13929486 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B74AA1EE013 for ; Tue, 7 Jan 2025 18:15:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273730; cv=none; b=FBG8zQGUM1VF02SHzDm11pKncYswtbiUkG9MLfr/BO8lZuoL0uX1kWZBmY8mR+skAk4AG5rzYtW4GC6+T/SNxQ4q4zAfVu7gpcOUqPhf6X2v356cqG/k+ckvAq37OPurPV4p8VTApoWr9ERgA924bBD7T/gjg/9kevFz6zMMSE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273730; c=relaxed/simple; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vadf/rve3Xb29rwFK9s43CBoourRmKEJBjAXPRDv0bkYfH++FlFB/m2Ux5X68o757w1CBgrA2xOII/MrtvgMUnhe4rEIVf24e0DXckNvEOp0GyFljpmY4e3onCmJN29N4uxyW6bgNvGEBDafl+2B/CHxJDApp+Ce414aBzYDaOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oeGaWYE9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oeGaWYE9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56FD2C4CEDE; Tue, 7 Jan 2025 18:15:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736273730; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oeGaWYE9x9us2FW5SbEm9nlltag4bnw6O3KEfx0XjegWF6TzaXbNMJxJfByIpSI51 XQOks49Z9A01nOwRszB6UmGJ7EHcxp47inOGYjaosIRJ2HAjXIWjs6+xtIhmKDdO9/ Tp4L+Q9CBGYCoGhpu9R9TROkDf9wonceY0rHORWPPeWk3zwCdK0erAxwd0F725PzbT RVHIiJLRTDVGC8d6Ggli9z8OuADW32qwlrzvYemLEbWMj4tKbexkqIVd9EMtySxLG9 3EY0Wkko+gniOy/RmloGbIaqtG4OrKw1sLtVp7LWeuEtvTZbCxJ3q9ulSXhbiuk1Ws N1bXMAHv8CYJg== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 2/6] PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability() Date: Tue, 7 Jan 2025 19:14:52 +0100 Message-ID: <20250107181450.3182430-10-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250107181450.3182430-8-cassel@kernel.org> References: <20250107181450.3182430-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1884; i=cassel@kernel.org; h=from:subject; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJr8xWE1ls+XCJh+XfJy3kz65tDIo6+nSa3vHWTzccrk iwnmLRKOkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCR3W8Y/hfP/iR28Pjlulf9 zmmObH1rq1tDaus5D0U9WO+1aL/59lJGhsuPnnx1qU+R3sJSO7OERVnXPPRm8p4ip9/TXvhcWrv /PxMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Move dw_pcie_ep_find_ext_capability() so that it is located next to dw_pcie_ep_find_capability(). Additionally, a follow-up commit requires this to be defined earlier in order to avoid a forward declaration. Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8e07d432e74f..6b494781da42 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -102,6 +102,24 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap) return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_header *hdr) { @@ -690,24 +708,6 @@ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); -static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) -{ - u32 header; - int pos = PCI_CFG_SPACE_SIZE; - - while (pos) { - header = dw_pcie_readl_dbi(pci, pos); - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (!pos) - break; - } - - return 0; -} - static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { unsigned int offset; From patchwork Tue Jan 7 18:14:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13929487 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 649901F1902 for ; Tue, 7 Jan 2025 18:15:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Tue, 7 Jan 2025 18:15:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736273733; bh=v3Kwhm0BhDUuD1HxjafB0VtsUe6IRB51dWNCDvdZGWQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F5TbEccanVoIJ8TMC9T/bSLyYqpJHN+hdXnZKNHWofJ1BW65oBKajK3nTQSTeRyWX vF5dlV1WAjRhnN8hd9hwhiG+y+msgysrGh8Erp0KL7UOTGxJCfgtIL7sMWjKQzc7hI W4Ow55AzV06oHocICNFkxxN8rBzOpJFT2uBIjc6ABCbwV/j3emBkOLc/tnRBMST/wX Ucmf88AHMmJXg8Fx3cVdjNKazCjdfYAcswU7ewa6f+etX6lWKTraA4w5QvVsSVvHVy qqBnP5e3zBg3VO89MQCrRgKJTkUnYfBPZpHTlv5xJdL/VqosvlvZiDaulQEPoTC3gu EPaUK+bD6Ou1w== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 3/6] PCI: dwc: endpoint: Add support for BAR type BAR_RESIZABLE Date: Tue, 7 Jan 2025 19:14:53 +0100 Message-ID: <20250107181450.3182430-11-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250107181450.3182430-8-cassel@kernel.org> References: <20250107181450.3182430-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9696; i=cassel@kernel.org; h=from:subject; bh=v3Kwhm0BhDUuD1HxjafB0VtsUe6IRB51dWNCDvdZGWQ=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJr8xX0ntfnB1gKX/+Rw2r0dmKgkqd/gY72pfRLnQ+DT 16fsftWRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACYi58XwVyzspviaZywKuZfD Z/3f7XfX8J/G17QJfHkb5/0oLFITyWL472icYvN0IUPUnLCWlq/9fHWXj07787x8yY7ba1pab3x Zxg8A X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC databook specifies three different BARn_SIZING_SCHEME_N - Fixed Mask (0) - Programmable Mask (1) - Resizable BAR (2) Each of these sizing schemes have different instructions for how to initialize the BAR. The DWC driver currently does not support resizable BARs. Instead, in order to somewhat support resizable BARs, the DWC EP driver currently has an ugly hack that force sets a resizable BAR to 1 MB, if such a BAR is detected. Additionally, this hack only works if the DWC glue driver also has lied in their EPC features, and claimed that the resizable BAR is a 1 MB fixed size BAR. This is unintuitive (as you somehow need to know that you need to lie in your EPC features), but other than that it is overly restrictive, since a resizable BAR is capable of supporting sizes different than 1 MB. Add proper support for resizable BARs in the DWC EP driver. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, the DWC EP driver will be able to support resizable BARs (we intentionally only support a single supported resizable BAR size). This means that an EPC driver does not need to lie in EPC features, and an EPF driver will be able to set an arbitrary size (not be forced to a 1 MB size), just like BAR_PROGRAMMABLE. Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 192 ++++++++++++++++-- 1 file changed, 177 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 6b494781da42..60380d704397 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -223,6 +223,138 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, ep->bar_to_atu[bar] = 0; } +static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, + enum pci_barno bar) +{ + u32 reg, bar_index; + unsigned int offset, nbars; + int i; + + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (!offset) + return offset; + + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + bar_index = reg & PCI_REBAR_CTRL_BAR_IDX; + if (bar_index == bar) + return offset; + } + + return 0; +} + +static u32 dw_pcie_ep_bar_size_to_rebar_cap(size_t size) +{ + u32 val; + + /* + * According to PCIe base spec, min size for a resizable BAR is 1 MB, + * thus disallow a requested BAR size smaller than 1 MB. + * Disallow a requested BAR size larger than 128 TB. + */ + if (size < SZ_1M || size > (SZ_128G * 1024)) + return 0; + + val = ilog2(size); + val -= 20; + + /* Sizes in REBAR_CAP start at BIT(4). */ + return BIT(val + 4); +} + +static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + unsigned int rebar_offset; + u32 rebar_cap, rebar_ctrl; + + rebar_offset = dw_pcie_ep_get_rebar_offset(pci, bar); + if (!rebar_offset) + return -EINVAL; + + rebar_cap = dw_pcie_ep_bar_size_to_rebar_cap(size); + if (!rebar_cap) + return -EINVAL; + + dw_pcie_dbi_ro_wr_en(pci); + + /* + * You should not write a BAR mask for a resizable BAR. The BAR mask + * is automatically derived by the controller every time the "selected + * size" bits are updated, see "Figure 3-26 Resizable BAR Example for + * 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write + * BIT(0) to set the BAR enable bit. + */ + dw_pcie_ep_writel_dbi2(ep, func_no, reg, BIT(0)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + /* + * Bits 31:0 in PCI_REBAR_CAP define "supported sizes" bits for sizes + * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" + * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. + */ + rebar_ctrl = dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); + rebar_ctrl &= ~GENMASK(31, 16); + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + + /* + * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically + * updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR + * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a. + */ + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap); + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static int dw_pcie_ep_set_bar_programmable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + + dw_pcie_dbi_ro_wr_en(pci); + + dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(struct dw_pcie_ep *ep, + enum pci_barno bar) +{ + const struct pci_epc_features *epc_features = ep->ops->get_features(ep); + + return epc_features->bar[bar].type; +} + static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { @@ -230,9 +362,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar = epf_bar->barno; size_t size = epf_bar->size; + enum pci_epc_bar_type bar_type; int flags = epf_bar->flags; int ret, type; - u32 reg; /* * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs @@ -264,19 +396,30 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, goto config_atu; } - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - dw_pcie_dbi_ro_wr_en(pci); - - dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); - - if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { - dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + bar_type = dw_pcie_ep_get_bar_type(ep, bar); + switch (bar_type) { + case BAR_FIXED: + /* + * There is no need to write a BAR mask for a fixed BAR (except + * to write 1 to the LSB of the BAR mask register, to enable the + * BAR). Write the BAR mask regardless. (The fixed bits in the + * BAR mask register will be read-only anyway.) + */ + fallthrough; + case BAR_PROGRAMMABLE: + ret = dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar); + break; + case BAR_RESIZABLE: + ret = dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar); + break; + default: + ret = -EINVAL; + dev_err(pci->dev, "Invalid BAR type\n"); + break; } - dw_pcie_dbi_ro_wr_dis(pci); + if (ret) + return ret; config_atu: if (!(flags & PCI_BASE_ADDRESS_SPACE)) @@ -710,9 +853,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { + struct dw_pcie_ep *ep = &pci->ep; unsigned int offset; unsigned int nbars; - u32 reg, i; + u32 reg, i, val; offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); @@ -727,9 +871,27 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) * PCIe r6.0, sec 7.8.6.2 require us to support at least one * size in the range from 1 MB to 512 GB. Advertise support * for 1 MB BAR size only. + * + * For a BAR that has been configured via dw_pcie_ep_set_bar(), + * advertise support for only that size instead. */ - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4)); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + /* + * While the RESBAR_CAP_REG_* fields are sticky, the + * RESBAR_CTRL_REG_BAR_SIZE field is non-sticky (it is + * sticky in certain versions of DWC PCIe, but not all). + * + * RESBAR_CTRL_REG_BAR_SIZE is updated automatically by + * the controller when RESBAR_CAP_REG is written, which + * is why RESBAR_CAP_REG is written here. + */ + if (ep->epf_bar[i]) + val = dw_pcie_ep_bar_size_to_rebar_cap(ep->epf_bar[i]->size); + else + val = BIT(4); + + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val); + } } dw_pcie_setup(pci); From patchwork Tue Jan 7 18:14:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13929488 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C4CC1EE7DC for ; Tue, 7 Jan 2025 18:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273736; cv=none; b=Ai2YDsx6QWFLpZh+Na4GZ2Q44WNRThCa6ZXoP0djgw7sVsYwAjV7tSVAlX59jR0ip7wsKxHYa2EyN7A+iKqCt6pIncfGJBNKtZ5Yd1qMSIyhGcInPbMtL6suHyB8SCB/75YMGoX44bA8UKvCdyfiQVzAkneoHK8t617BuZSgeWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273736; c=relaxed/simple; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d0DwtkDaw4n35ac1hykTPbG9ZEDckiVqi37Y57vvSB9sofrYsEPaUynySj9AeefUd4GwEt9pkHr9jRsGlkzry/vZY1tLiIy1uvAHZxJGa84frNfmJHphOHXLTNflWL62RNLcdIAmlzwOlT94TZfgkaE8Oj7Sfb+mixmuBho4pmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iGMENbX0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iGMENbX0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A3137C4CED6; Tue, 7 Jan 2025 18:15:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736273735; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iGMENbX00OTG117OYdUb4LUcy4QZLKAtGLne35SwHpPBgvhZHx+VryWSrzoug/xtO t6hkSIddx+UbaNk97jf+N0N5P3o5zMuISXpkPPTK4NdscqdTHZBqB/K/WGB1fpFW5Z MYdyjpE91/+hfwFSW7s8bu6CB38jsIXud2y/lhz44APCWRsm6RouiLiN3a3ZtGgT2o 3DEpQw0OjdW4oiWE0kMrGLAAlqaSbN8Dz4p6FYvhILDeSKuSgc1DNADVj8bkr4EgGj ar7hIH178SrRoJzxFN5oax0vHrSxtYQDVidg2zfJ8OoPYeRlOn8WU4BKLZ5LeARRM+ jJJZGzoXqGhVQ== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 4/6] PCI: keystone: Describe resizable BARs as resizable BARs Date: Tue, 7 Jan 2025 19:14:54 +0100 Message-ID: <20250107181450.3182430-12-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250107181450.3182430-8-cassel@kernel.org> References: <20250107181450.3182430-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1286; i=cassel@kernel.org; h=from:subject; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJr8xXePDm5TOZYxOzbsyPOemkZvyi8vOKmveAtCf+TB 3WvGOpd6ChlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEFFYwMqxbWXFFZ86MdQ2K TKdsP7au7bb/G1dyem9666y5jJFP1q9mZNidWnrO+zJTZqXiXkM3kwmxzbo+xbc339+6bpVPifL qPVwA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "12.2.2.4.15 PCIe Subsystem BAR Configuration" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf We can see that BAR2 and BAR5 are not Fixed BARs, but actually Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 63bd5003da45..fdc610ec7e5e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -966,10 +966,10 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .msix_capable = true, .bar[BAR_0] = { .type = BAR_RESERVED, }, .bar[BAR_1] = { .type = BAR_RESERVED, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, .align = SZ_1M, }; From patchwork Tue Jan 7 18:14:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13929489 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D4D6199931 for ; Tue, 7 Jan 2025 18:15:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273738; cv=none; b=TRrS3Xqqo6GS17ZIukMVXoEHckYFU5OazucRYr2/o/Ei/hGBYTP8eS/WlBubTPlbCXbKVEpazD6nGM9mSwjbuozGNRpaFT9z+PPZ/arO2Wy2C30yXbN8/cAN6I+K3qzp6MWDz9682QXydkD3CVRbASVM8CXapUb/WtQPDBZ7BD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273738; c=relaxed/simple; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MI0w4wXeDxAmT04aI0vRGiY//QY949SAnmtuq701sr1QJHnuu/Cwq7YO5F/PZMv0rMyGaskYC8gVhQ0RC0S4qrf2oOXgfUZ6yEjIg7389r21Xr2NOGEGpoOK9Ot/BB5E2M/bQGGkwb/OV9W+3JZpw/hO5N9e3TK3QMnG3t8H5YE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dXWQuw4u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dXWQuw4u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17BC0C4CEDD; Tue, 7 Jan 2025 18:15:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736273737; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dXWQuw4uGDguVWZ5O+D4YKYmhD0xqN1zldP77u1wg4DimYCbhQlpWruUhSs0CBaxk C6xp4UCHHE9HuMAVvROfpvD68wHN6PcbyKjbniHUYIJR9uALGKPSaub2CZb0xqXnmk WXr4OlX3M9HTHQvt7cCuGBUQ7FYz96ZwvtkSZEb2imjHMBNH04AJX3iRvQ4IajHW6V XpxqNl8VnZYi93nQFRScg8r2ghWxMmJVd0HFalURMAe1czjcXLNTnIDAVuHWzHJXcK GJnBtb3PRVQ+23yA/NoIgHdU73bkWJ2j3p4i3Q/vfF7KLwZmWXufp1buSznYaHL659 5xEe+tkdGr/OQ== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 5/6] PCI: keystone: Specify correct alignment requirement Date: Tue, 7 Jan 2025 19:14:55 +0100 Message-ID: <20250107181450.3182430-13-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250107181450.3182430-8-cassel@kernel.org> References: <20250107181450.3182430-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1604; i=cassel@kernel.org; h=from:subject; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJr8xVll55u3cHToJPoHTdjd/vSlXL917lzpWp07a8nf T4Ys9Sio5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABOJX8Lw37nZjl/Qzbxc7k2c CLvYme7tL4W6cyZOOtF1mEWwwnalKSPD3qtzowz9diUxme+ureDiZkgTfRQVtuzhgcoJ+vZPS1d xAAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The support for a specific iATU alignment was added in commit 2a9a801620ef ("PCI: endpoint: Add support to specify alignment for buffers allocated to BARs"). This commit specifically mentions both that the alignment by each DWC based EP driver should match CX_ATU_MIN_REGION_SIZE, and that AM65x specifically has a 64 KB alignment. This also matches the CX_ATU_MIN_REGION_SIZE value specified by "12.2.2.4.7 PCIe Subsystem Address Translation" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf This higher value, 1 MB, was obviously an ugly hack used to be able to handle Resizable BARs which have a minimum size of 1 MB. Now when we actually have support for Resizable BARs, let's configure the iATU alignment requirement to the actual requirement. (BARs described as Resizable will still get aligned to 1 MB.) Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-keystone.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fdc610ec7e5e..76a37368ae4f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -970,7 +970,7 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, .bar[BAR_5] = { .type = BAR_RESIZABLE, }, - .align = SZ_1M, + .align = SZ_64K, }; static const struct pci_epc_features* From patchwork Tue Jan 7 18:14:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13929490 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420911DF25C for ; Tue, 7 Jan 2025 18:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273741; cv=none; b=RgFNyS32r2XK59S76yzzNE2sU4eRzWkKpqM0nsPO/qNvpxcunjQs9/UnQyONxhhhbiO2o1+aOWASb02BX4TNfRksp8U1HBdOrxgQaU+z1VwtsU0ztJCvRzJINMEMCrUYmDlyYhiM6tpwNVrDkIMZU1MvZzzNLRt8Ham/3PXm//g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736273741; c=relaxed/simple; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W5lJfamczqeTxO3UrvivzDXe8VadQv99TCR2viUBeIWhc3zw3dom5Za43qAy9lQqtBylWdrT07Pi7ezyJxlxH162BAGc1T9cC3XSEr3R3QsM+3CzWtLUVrlpad3Xp3HywtC/rMbfVwj4Yd60YBo5njUFPLRP2SMEpXOGyuX/Dsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m9epLKEB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m9epLKEB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84EC5C4CED6; Tue, 7 Jan 2025 18:15:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736273740; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m9epLKEB4Ua0wOU1NBLxEUWtamnLKpupf0LIemEnjpkyMiMSs4md8jN2hzrdUEsbN k7wT3PzAW00qFQEKXJBExWjwVdPc0ONgqoMhAmZPsduIr3eHh8Y7hULBQP0nb4b1z7 DJ+2SR0O6yybFeWckPVGq4J+gxkwwtNJaM4xH2tIUdIkw+gfcA46hKYlfWUGpSPRVB ULNSB6pyx17N1rafrODipXv4cL8/Wu/jXDnxfiCt8+Un5HpOVBGbxX8kCfbXzAaGrb mOzusBs/OHIwt15jDMr563IMjPFYQrbYxlPr8SNZRzvZRO9XTP/SKg2KWBMDP0N7K3 6mwVmt16xE4aA== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 6/6] PCI: dw-rockchip: Describe resizable BARs as resizable BARs Date: Tue, 7 Jan 2025 19:14:56 +0100 Message-ID: <20250107181450.3182430-14-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250107181450.3182430-8-cassel@kernel.org> References: <20250107181450.3182430-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2520; i=cassel@kernel.org; h=from:subject; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJr8xWP/59YxzOtaeNWwVce1/qe8drIX/Pk+DdJlOfuT /ebDR2LO0pZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCRz2YM/yOVrx/Z1DTJ9Nd8 9VmOh55c8LWziInhl2mZVl3z4aCQazgjw9aC19+viiXdnalpl/cvY9uM3NVWYd/OLAmaVynj6vd FgBMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM, we can see that none of the BARs are Fixed BARs, but actually Resizable BARs. I couldn't find any reference in the rk3568 TRM, but looking at the downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same, so the BARs on rk3568 must also be Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index ce4b511bff9b..6a307a961756 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, + .bar[BAR_4] = { .type = BAR_RESIZABLE, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; /* @@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, .bar[BAR_4] = { .type = BAR_RESERVED, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; static const struct pci_epc_features *