From patchwork Wed Jan 8 09:50:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930453 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3769417C20F; Wed, 8 Jan 2025 09:51:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329863; cv=none; b=YI30DG9Ir4DumhN1jWyRpKpPm1Sluh0efo23DG00TAcY9l1GAX9QH+LkNcLZ9A3p4u16NYDeOaEpbo1iQY8NdxysgIWncjzqn5HjwseIrhZe8/d14e5MTUeYbUFqo9+EYsdhknLp9BUKFdTkWh3wdjRZxsLoD0tfjKS1tfmrPqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329863; c=relaxed/simple; bh=29cWk1BMgfLD5wAcay/Bq/fTMXy4oV5VbyKl8GHHLpg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pNIoHwln25+cNvMh6G0mZZPQKtPfQOEKipK/QILsIG+epa6HdmXTZ2SFnbDTNn2q2ffS50QvapcnIIRPQ5uQlQ4IpBwR/2U4bEGduQzF4XPlBJUMjMXHC3mgN1+rgNcAcYIKQYWReruzTNEl/hbiOUKNId9MGHuYnuJxZxpumqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fV76BW8a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fV76BW8a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A64EC4CEE0; Wed, 8 Jan 2025 09:51:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329862; bh=29cWk1BMgfLD5wAcay/Bq/fTMXy4oV5VbyKl8GHHLpg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fV76BW8aIOK3acC6C9OCKVX5dMEOa0FTArVi9tby3Nw5mT82wg4yiEtahhiSN/Pb3 QOVy1df/KF6aq8y3L73kxNnHrwpIIi2ZW/L6tcw4K69QuBwb+wuEA7pJYw96NfY7li H9j8kIn4XVGKxYXGPokyuS1kRBJ9vG1e9AbxJGeSkmBPvh0Qujm12beYbpOpSlKZog GGFvAKKJZslHFUUGs7lWP9Mtb2VwgA48IFjXKdcVmRLO85lOE3uOgJR/J73QXw9c3p 7poqPkCp/r1TzrnhCsR21TXqaXndwIogALKvY+4X24XrGhtVNizxs2YY8SZIRymAew 76/PAAfXOcplw== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:40 +0100 Subject: [PATCH v6 1/5] PCI: mediatek-gen3: rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-1-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Replace clk_bulk_prepare() and clk_bulk_enable() with clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index be52e3a123abd0d0086f9f1a603e3abaa18f319f..886d458df40d009424c2ae6f1564f51a669643ad 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -945,12 +945,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -963,17 +957,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_prepare_enable; } return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); From patchwork Wed Jan 8 09:50:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930454 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07F241E0DC3; Wed, 8 Jan 2025 09:51:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329866; cv=none; b=TUWtVFIzZTM6MxFdO1YES2k4CImb7uL15oMjvwVul7j3iJasChyE2C5nX9juV0H2Yd5ZWGWRHa3oDJfbhCZ7WnIu7KeAkvuuck69bvm0YnuuiUuUF2aYtFEYEgyfpLDa/MfCPkuhfrzwoGs1X4O6IXL50asOxUMV2D+5ZLu1lgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329866; c=relaxed/simple; bh=sSr7jnmf2lp/4KRHdrUAbnv/WR37msyTvdSzhf1tJ8Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ip7iLjVAD7OtqaBf+so1SZvzrn0KCDOAmRzK+0QOwSl1GIE8Co/zbxcQ0AwqVdTe4sKt15Si8uZi3Do88OSSbGI6UrB0xSEiNyoNFrv61Sj8gr1zD0oif7QlrBlIFe2I5yagqeLLjJ9zphi1rgtvbkiowQ9z4bezM6HzXJvbk8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FhpNwLdx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FhpNwLdx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46AB0C4CEE0; Wed, 8 Jan 2025 09:51:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329865; bh=sSr7jnmf2lp/4KRHdrUAbnv/WR37msyTvdSzhf1tJ8Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FhpNwLdxaKGsKIUHU1csO8vSGF2k8DXxx5RcT9VlytWKkeOH/ddhgLnwshaJY++hc 7fV09VmGUy2rIYZPgFV/Lf6ENx6LPN7/0PWatYRxwUj9hQUPYQpTJ3vUJT7g4Zm8fL KvtEcULOfm72xr2hWqWqhh6QYOb/HC0ZysDm0iOyGIIFLE3F0y4OxxAx9jM3COLb1A wjOcfU3hdAdpPWDvHr5gKB904jH4xxgMJEmvqI4aUq26GGT0uiC9HeJDboBE9BnZRL s9HFqH1j0u8Igf2ISoz/d+k3VMZdBHbP44gmGlkvVk71yQ4AxqJi8DDUhAJ2tFxsSS uJvs/IEY3C/fg== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:41 +0100 Subject: [PATCH v6 2/5] PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-2-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 In order to make the code more readable, the reset_control_bulk_assert() for PHY reset lines is moved to make it pair with reset_control_bulk_deassert() in mtk_pcie_power_up() and mtk_pcie_en7581_power_up(). The same change is done for reset_control_assert() used to assert MAC reset line. Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 886d458df40d009424c2ae6f1564f51a669643ad..4ce2b9d0dcd54e44cb645603d81865d26b2c8f23 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -125,6 +125,8 @@ #define MAX_NUM_PHY_RESETS 3 +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -913,9 +915,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) u32 val; /* - * Wait for the time needed to complete the bulk assert in - * mtk_pcie_setup for EN7581 SoC. + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + + /* Wait for the time needed to complete the reset lines assert. */ mdelay(PCIE_EN7581_RESET_TIME_MS); err = phy_init(pcie->phy); @@ -982,6 +989,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); if (err) { @@ -1066,14 +1082,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * counter since the bulk is shared. */ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie); From patchwork Wed Jan 8 09:50:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930455 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC5B017C20F; Wed, 8 Jan 2025 09:51:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329870; cv=none; b=CpP9+b2d8Hg6vh9cX47RCY42Eiu92q8x+z3OEWPoIdnkP6pGY1GAs/zbLKgOBsqjOdzgdry+1eD5+NqUIE9CTtS5OSmgKiYG2RcMXvDQYKPB1lptBqmGNeJ8M088jYNJwoRVpfOFinmf/liaV17iNL0s0XO2uTpDvLIbmxn638E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329870; c=relaxed/simple; bh=7c+kocCfpLH6i+F/+/Wlp6DSrIjmG2PsUPjDIxgIlik=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DWt36a+Z0FTewsbamvAXCNhnySWyUgvuYHzc93TZVU+lElICN1frv6pWaHHfGVQJtDcrA47rssAJ8npMoSt6yw8q2VAt0+SScAwUzYoOmB+nj/ktvRuf4mQjOJMAud8IrlHV+7E0xYYA3RUZWcADtvarK8IY4MgVsYP3SjmtXlE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TMuy0ZeE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TMuy0ZeE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A807C4CEE0; Wed, 8 Jan 2025 09:51:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329868; bh=7c+kocCfpLH6i+F/+/Wlp6DSrIjmG2PsUPjDIxgIlik=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TMuy0ZeEb5SXW00QOWOhrfLQH2hZbuw/Drj3LK64kpw8F26vHrWlS/u70M2n1voZc R3bDCZDHmA4kCcAB5eQC/kB4oewxssZkp94dGMebmIp3hXmaZ/3ceka4wrMAYDuSyM jCtVw4ugM3uwyTkreMaMpH919P1MarZ8QJa/Ajsw1P4+fjdSaHWrE47sF61gAisPoX IoEz+EvJt2gFJ8ZDS2f7g/NXazMABtXBPqUaIPpLBn8up2VeSPw6zbzYzBZsFG3Oqy fX4B1xkNVYqnyYUvQJjPU2GNU0aJyCcFub8sHxVuiZsbyu5b8OGVsAnFr/OeGVeSaT IhQYkc+ZPCbgA== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:42 +0100 Subject: [PATCH v6 3/5] PCI: mediatek-gen3: Add comment about initialization order in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-3-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike the other MediaTek Gen3 controllers, the Airoha EN7581 requires PHY initialization and power-on before PHY reset deassert. Reviewed-by: Manivannan Sadhasivam Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 4ce2b9d0dcd54e44cb645603d81865d26b2c8f23..71df8817c1635b04b67233fb43abe2de7770b0f2 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -925,6 +925,10 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) /* Wait for the time needed to complete the reset lines assert. */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* + * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 + * requires PHY initialization and power-on before PHY reset deassert. + */ err = phy_init(pcie->phy); if (err) { dev_err(dev, "failed to initialize PHY\n"); From patchwork Wed Jan 8 09:50:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930456 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C01441F4E5F; Wed, 8 Jan 2025 09:51:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329871; cv=none; b=nbsWsm3o8/kQ+OPTRBvjxz6u222iy7436Clc2exTmtZ5FCjqa0J1+4LIxdDfIowHIIfI5wskZsARYgEdIDzPIobVCf/I+WTJsT5lyXvl6nJo5Qluhx9ZeRzr8Sc9M3kN3rJ00zIdUiRrNeixKaD+N6QjymauvW7RjqqukN0Kdmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329871; c=relaxed/simple; bh=hUb9miYebZT06jePw/BBYK9Z5F6LbG4WTTs+ZWUFqZ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kMbOjJpiKFEP680oIcJNPAXlDCW82G1LYDDMKvdV9+FZ8S+tt6TqHlGLewJKdDLx+hfLD2eE3Udq082vPigDdPY6GDnUQbmBrWVJ4Ax5fxEgyDW3+mAwc+JpJL4NZhfOIJxivYg/fva+aRQyGFEwzeeFJlezixxEJLkP3Jp8+C4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FIan2Zu4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FIan2Zu4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EEA6BC4CEE0; Wed, 8 Jan 2025 09:51:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329871; bh=hUb9miYebZT06jePw/BBYK9Z5F6LbG4WTTs+ZWUFqZ8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FIan2Zu4iLJ6UWsEVg1D8Vk9oQZX58TmLB3RkTg5tFRfKL2Xapx9uy+wJYLoZdUTk Z1nzeInHtMCpNPWkbtUXOkc7gLSnb93jlFm4KUdyOZQM0y0uS7/CKsNywTe1Kd/JrR WrwaFrlDd3Gz77wlCQS9eXxZqXMAgsaEmP6PPId8PGkTXbcz4dQVHxQidyxBc+Te1F W4e9H7GxN+rP27fdl/YSNJvoX7dPu9NdjTp7KKNMHo/PxkIQz1yk8BqZ56dYaTV0Ba UqICKNIVeFK1P9q8Y8lW68qKYCDlIuGd5SPFsnwaOB7CDNZ90G6NHHPFY7FarWCIVX RiGmHj05bm9NA== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:43 +0100 Subject: [PATCH v6 4/5] PCI: mediatek-gen3: Move reset delay in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-4-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal causing occasional PCIe link down issues. In order to overcome the problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and REG_RESET_CONTROL (0x834) registers available in the clock module running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up(). In order to make the code more readable, move the wait for the time needed to complete the PCIe reset from en7581_pci_enable() to mtk_pcie_en7581_power_up(). Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value (100ms) since it has no impact on the driver behavior. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Stephen Boyd Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 1 - drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index e52c5460e927f54c6df152c60560f438f89ec928..513730e5b953f4412b6b12b98c742692de5424c1 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -477,7 +477,6 @@ static int en7581_pci_enable(struct clk_hw *hw) REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); return 0; } diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 71df8817c1635b04b67233fb43abe2de7770b0f2..01e0b53cc1f22fc4b9270a2eb6a55e8948ba2f8b 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -974,6 +974,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callbacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; err_clk_prepare_enable: From patchwork Wed Jan 8 09:50:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13930457 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 988901A2395; Wed, 8 Jan 2025 09:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329874; cv=none; b=OmXB46wcSEtnNKtzSYoHvm8RVtHuZGKPZ3v+16iVKJdbufj00n9Rn9v3puN+8F/ZeFC5ZPFszz7/gQGcj9rtRAxKvdm/vCDVAWhgEH1bMB+RIXC1LurJ5JR0DlrA/N209tZIq01wOWuAvR/L1yt8QGi2L7RlAkdGYgZfObC5TwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736329874; c=relaxed/simple; bh=hPN4D7FTStknqbjGuFANLoFGFT58qAH7862kTNVFYwA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JRGK2RPxznWf3fkVnnwtHVjblW1Qol/khlyTMtq3sFkflvf91gL0QDBo2Zj3oMGnj/7/CIdBYHAuHnH0V8E8C3UhfSpDj1SjSmGnTQV7nRjdp85/wCpr3CBlZ0fDzxnmAlh6MkUTVQMdV3OwahpR8SR9sT1BqTQaAlqQqU6UsSc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=itGVqydC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="itGVqydC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1328C4CEE0; Wed, 8 Jan 2025 09:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736329874; bh=hPN4D7FTStknqbjGuFANLoFGFT58qAH7862kTNVFYwA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=itGVqydCr2lYckymqpdNsd6/HKnE9ZZQ5cRpX4UWKzJExf7kJ3/FnMZcLeLcg2jtu j/QDKg8BsRqnEqa/DioRev+WvSQ9CrzButK5VYMEx68n1K2ETitduLva/aFxYHvSvq Kvdae98yeostOtMyFmIdk2DAUCyRKjEE5yxPNAzcCDeNX4rVuWYuEpQv26Q7yjs5lo uIPw/f6ZhNFnHmSwB0IEjqto4PVUYFiNtyPjok4Flu/sRsh9c+2pD409pmT6XLqbsW JqsjYEFgDiQglzmUwUrT6e/uYYWKa79moUak+9pJvKoHuiyr62dORkWBDr9nhPVb0k IeTBMmBgMgC6A== From: Lorenzo Bianconi Date: Wed, 08 Jan 2025 10:50:44 +0100 Subject: [PATCH v6 5/5] PCI: mediatek-gen3: rely on msleep() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250108-pcie-en7581-fixes-v6-5-21ac939a3b9b@kernel.org> References: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> In-Reply-To: <20250108-pcie-en7581-fixes-v6-0-21ac939a3b9b@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Since mtk_pcie_en7581_power_up() runs in non-atomic context, rely on msleep() routine instead of mdelay(). Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 01e0b53cc1f22fc4b9270a2eb6a55e8948ba2f8b..aa511965eb914f7e58e78194491ca7a23790b99d 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -923,7 +923,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) reset_control_assert(pcie->mac_reset); /* Wait for the time needed to complete the reset lines assert. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 @@ -951,7 +951,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) * Wait for the time needed to complete the bulk de-assert above. * This time is specific for EN7581 SoC. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); pm_runtime_enable(dev); pm_runtime_get_sync(dev);