From patchwork Wed Jan 8 10:41:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13930527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A55A0E7719A for ; Wed, 8 Jan 2025 10:41:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2654110E1A6; Wed, 8 Jan 2025 10:41:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FnMGdPF+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 767DE10E1A6 for ; Wed, 8 Jan 2025 10:41:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736332895; x=1767868895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TOiQN9gR0X70KbMYHao8pUNbPbpb6N9/6yL8l6CKfns=; b=FnMGdPF+JTuNbF0pcvA3wLpD4BhQPtZdmJJn+ga9cVvWgHBqjRyNPBd1 LPEPjm/Ck7j0OYEM+UN+q2wZ3w9kMAs+AZTQGK9Qwn/hNa7kn8t3VT/f4 Y8CXqQ8uz1Ku1Gcpqi57JLL9u1FRDtQf3GBsYGVcBCNQnV0aTEqaCeHof 28PD16n+5qk3+gbP7ZFjzcLCwE17QhkO4/qJfhGwGS5u2ZLXydDmKH02F LByfAj7buwNoNg4Fv+C2j/te5HJ/vxS/pO7qsjXaE2mO3U3seA6InKr7h uc8/O6LuiaCz7UYN+ElrhlFlvYAPKiFqYXs5htWwlyZIw+ySvJhhjOecl w==; X-CSE-ConnectionGUID: qr0gpCDmSTK7idTWhQNjFQ== X-CSE-MsgGUID: ubuqsY43RR6mYxAYXWn8JQ== X-IronPort-AV: E=McAfee;i="6700,10204,11308"; a="36434233" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="36434233" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:31 -0800 X-CSE-ConnectionGUID: 00bvus8oRHOTQ9VLxoSXwQ== X-CSE-MsgGUID: h2sO7942Sd2qx/f/WTxqpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="140395543" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:30 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 1/6] drm/i915/display: convert display reset to struct intel_display * Date: Wed, 8 Jan 2025 12:41:16 +0200 Message-Id: <635fadc88d5d07d06ba78382227a0b3bcc06a073.1736332802.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Going forward, struct intel_display will be the main display device structure. Convert display reset to it as much as possible. Signed-off-by: Jani Nikula Reviewed-by: Matt Roper --- .../drm/i915/display/intel_display_reset.c | 51 ++++++++++--------- .../drm/i915/display/intel_display_reset.h | 6 +-- drivers/gpu/drm/i915/gt/intel_reset.c | 7 ++- 3 files changed, 35 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 093b386c95e8..3da70bdbd9f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -13,24 +13,27 @@ #include "intel_hotplug.h" #include "intel_pps.h" -static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) +static bool gpu_reset_clobbers_display(struct intel_display *display) { - return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && - intel_has_gpu_reset(to_gt(dev_priv))); + struct drm_i915_private *i915 = to_i915(display->drm); + + return (INTEL_INFO(i915)->gpu_reset_clobbers_display && + intel_has_gpu_reset(to_gt(i915))); } -void intel_display_reset_prepare(struct drm_i915_private *dev_priv) +void intel_display_reset_prepare(struct intel_display *display) { - struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx; + struct drm_i915_private *dev_priv = to_i915(display->drm); + struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; struct drm_atomic_state *state; int ret; - if (!HAS_DISPLAY(dev_priv)) + if (!HAS_DISPLAY(display)) return; /* reset doesn't touch the display */ - if (!dev_priv->display.params.force_reset_modeset_test && - !gpu_reset_clobbers_display(dev_priv)) + if (!display->params.force_reset_modeset_test && + !gpu_reset_clobbers_display(display)) return; /* We have a modeset vs reset deadlock, defensively unbreak it. */ @@ -39,7 +42,7 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv) wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Modeset potentially stuck, unbreaking through wedging\n"); intel_gt_set_wedged(to_gt(dev_priv)); } @@ -48,10 +51,10 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv) * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. */ - mutex_lock(&dev_priv->drm.mode_config.mutex); + mutex_lock(&display->drm->mode_config.mutex); drm_modeset_acquire_init(ctx, 0); while (1) { - ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx); + ret = drm_modeset_lock_all_ctx(display->drm, ctx); if (ret != -EDEADLK) break; @@ -61,34 +64,34 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv) * Disabling the crtcs gracefully seems nicer. Also the * g33 docs say we should at least disable all the planes. */ - state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx); + state = drm_atomic_helper_duplicate_state(display->drm, ctx); if (IS_ERR(state)) { ret = PTR_ERR(state); - drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", + drm_err(display->drm, "Duplicating state failed with %i\n", ret); return; } - ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx); + ret = drm_atomic_helper_disable_all(display->drm, ctx); if (ret) { - drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", + drm_err(display->drm, "Suspending crtc's failed with %i\n", ret); drm_atomic_state_put(state); return; } - dev_priv->display.restore.modeset_state = state; + display->restore.modeset_state = state; state->acquire_ctx = ctx; } -void intel_display_reset_finish(struct drm_i915_private *i915) +void intel_display_reset_finish(struct intel_display *display) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; struct drm_atomic_state *state; int ret; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; /* reset doesn't touch the display */ @@ -100,12 +103,12 @@ void intel_display_reset_finish(struct drm_i915_private *i915) goto unlock; /* reset doesn't touch the display */ - if (!gpu_reset_clobbers_display(i915)) { + if (!gpu_reset_clobbers_display(display)) { /* for testing only restore the display */ ret = drm_atomic_helper_commit_duplicated_state(state, ctx); if (ret) { - drm_WARN_ON(&i915->drm, ret == -EDEADLK); - drm_err(&i915->drm, + drm_WARN_ON(display->drm, ret == -EDEADLK); + drm_err(display->drm, "Restoring old state failed with %i\n", ret); } } else { @@ -120,7 +123,7 @@ void intel_display_reset_finish(struct drm_i915_private *i915) ret = __intel_display_driver_resume(display, state, ctx); if (ret) - drm_err(&i915->drm, + drm_err(display->drm, "Restoring old state failed with %i\n", ret); intel_hpd_poll_disable(i915); @@ -130,7 +133,7 @@ void intel_display_reset_finish(struct drm_i915_private *i915) unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); - mutex_unlock(&i915->drm.mode_config.mutex); + mutex_unlock(&display->drm->mode_config.mutex); clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); } diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.h b/drivers/gpu/drm/i915/display/intel_display_reset.h index f06d0d35b86b..9a1fe99bfcd4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.h +++ b/drivers/gpu/drm/i915/display/intel_display_reset.h @@ -6,9 +6,9 @@ #ifndef __INTEL_RESET_H__ #define __INTEL_RESET_H__ -struct drm_i915_private; +struct intel_display; -void intel_display_reset_prepare(struct drm_i915_private *i915); -void intel_display_reset_finish(struct drm_i915_private *i915); +void intel_display_reset_prepare(struct intel_display *display); +void intel_display_reset_finish(struct intel_display *display); #endif /* __INTEL_RESET_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index aae5a081cb53..686be6edd2e3 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1413,11 +1413,14 @@ static void intel_gt_reset_global(struct intel_gt *gt, /* Use a watchdog to ensure that our reset completes */ intel_wedge_on_timeout(&w, gt, 60 * HZ) { - intel_display_reset_prepare(gt->i915); + struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; + + intel_display_reset_prepare(display); intel_gt_reset(gt, engine_mask, reason); - intel_display_reset_finish(gt->i915); + intel_display_reset_finish(display); } if (!test_bit(I915_WEDGED, >->reset.flags)) From patchwork Wed Jan 8 10:41:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13930528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90E23E77188 for ; Wed, 8 Jan 2025 10:41:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C55110E850; 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X-CSE-ConnectionGUID: psTNxsdGSiOuNYV95KDHcw== X-CSE-MsgGUID: Fbbj39NCQFKZBAA5nmLfWA== X-IronPort-AV: E=McAfee;i="6700,10204,11308"; a="47218464" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="47218464" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:37 -0800 X-CSE-ConnectionGUID: HqNDTQ+fTFu3+/yUOewCVA== X-CSE-MsgGUID: 2znhOkoIQ+K7TaE5weGgyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="102978963" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:35 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 2/6] drm/i915: move pending_fb_pin to struct intel_display Date: Wed, 8 Jan 2025 12:41:17 +0200 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" pending_fb_pin is more about display than GPU reset. Move it to struct intel_display. The restore sub-struct already contains reset related members, so move it there. Signed-off-by: Jani Nikula Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++ drivers/gpu/drm/i915/display/intel_display_reset.c | 2 +- drivers/gpu/drm/i915/display/intel_dpt.c | 5 +++-- drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 ++++++---- drivers/gpu/drm/i915/display/intel_overlay.c | 5 ++--- drivers/gpu/drm/i915/i915_gpu_error.h | 2 -- 6 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 554870d2494b..1970d4c15090 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -512,6 +512,8 @@ struct intel_display { /* restore state for suspend/resume and display reset */ struct drm_atomic_state *modeset_state; struct drm_modeset_acquire_ctx reset_ctx; + /* modeset stuck tracking for reset */ + atomic_t pending_fb_pin; u32 saveDSPARB; u32 saveSWF0[16]; u32 saveSWF1[16]; diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 3da70bdbd9f6..1e6421d51c51 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -41,7 +41,7 @@ void intel_display_reset_prepare(struct intel_display *display) smp_mb__after_atomic(); wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); - if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { + if (atomic_read(&display->restore.pending_fb_pin)) { drm_dbg_kms(display->drm, "Modeset potentially stuck, unbreaking through wedging\n"); intel_gt_set_wedged(to_gt(dev_priv)); diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index 8b1f0e92a11c..8254e8a2b82c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -125,6 +125,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, unsigned int alignment) { struct drm_i915_private *i915 = vm->i915; + struct intel_display *display = &i915->display; struct i915_dpt *dpt = i915_vm_to_dpt(vm); intel_wakeref_t wakeref; struct i915_vma *vma; @@ -137,7 +138,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, pin_flags |= PIN_MAPPABLE; wakeref = intel_runtime_pm_get(&i915->runtime_pm); - atomic_inc(&i915->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); for_i915_gem_ww(&ww, err, true) { err = i915_gem_object_lock(dpt->obj, &ww); @@ -167,7 +168,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, dpt->obj->mm.dirty = true; - atomic_dec(&i915->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); intel_runtime_pm_put(&i915->runtime_pm, wakeref); return err ? ERR_PTR(err) : vma; diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index d3a86f9c6bc8..ff5efd4544e3 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -25,6 +25,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, struct i915_address_space *vm) { struct drm_device *dev = fb->dev; + struct intel_display *display = to_intel_display(dev); struct drm_i915_private *dev_priv = to_i915(dev); struct drm_gem_object *_obj = intel_fb_bo(fb); struct drm_i915_gem_object *obj = to_intel_bo(_obj); @@ -42,7 +43,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); for_i915_gem_ww(&ww, ret, true) { ret = i915_gem_object_lock(obj, &ww); @@ -97,7 +98,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, i915_vma_get(vma); err: - atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); return vma; } @@ -111,6 +112,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, unsigned long *out_flags) { struct drm_device *dev = fb->dev; + struct intel_display *display = to_intel_display(dev); struct drm_i915_private *dev_priv = to_i915(dev); struct drm_gem_object *_obj = intel_fb_bo(fb); struct drm_i915_gem_object *obj = to_intel_bo(_obj); @@ -143,7 +145,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, */ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); /* * Valleyview is definitely limited to scanning out the first @@ -219,7 +221,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, if (ret) vma = ERR_PTR(ret); - atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); return vma; } diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index ca30fff61876..60ae5e3bc454 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -793,7 +793,6 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, struct drm_intel_overlay_put_image *params) { struct intel_display *display = overlay->display; - struct drm_i915_private *dev_priv = to_i915(display->drm); struct overlay_registers __iomem *regs = overlay->regs; u32 swidth, swidthsw, sheight, ostride; enum pipe pipe = overlay->crtc->pipe; @@ -808,7 +807,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, if (ret != 0) return ret; - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); vma = intel_overlay_pin_fb(new_bo); if (IS_ERR(vma)) { @@ -896,7 +895,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, out_unpin: i915_vma_unpin(vma); out_pin_section: - atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); return ret; } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h index 78a8928562a9..749e1c55613e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.h +++ b/drivers/gpu/drm/i915/i915_gpu_error.h @@ -224,8 +224,6 @@ struct i915_gpu_error { /* Protected by the above dev->gpu_error.lock. */ struct i915_gpu_coredump *first_error; - atomic_t pending_fb_pin; - /** Number of times the device has been reset (global) */ atomic_t reset_count; From patchwork Wed Jan 8 10:41:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13930529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 813AEE77188 for ; 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X-CSE-ConnectionGUID: mWZtsc5LT2ytuui2BIfOow== X-CSE-MsgGUID: UGvgJJTcSEqvDdaMPoSkgQ== X-IronPort-AV: E=McAfee;i="6700,10204,11308"; a="47218498" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="47218498" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:41 -0800 X-CSE-ConnectionGUID: 9wmGjZmCTZO8hvFuKtH+rQ== X-CSE-MsgGUID: jNUMTz+gS2WTsul8BA+bRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="102978994" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:39 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 3/6] drm/i915: add intel_gt_gpu_reset_clobbers_display() helper Date: Wed, 8 Jan 2025 12:41:18 +0200 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a helper for checking the gpu_reset_clobbers_display flag to make it easier to relocate the flag later. Signed-off-by: Jani Nikula Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 15 +++++++++++---- drivers/gpu/drm/i915/gt/intel_reset.h | 2 ++ drivers/gpu/drm/i915/i915_driver.c | 2 +- 5 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4d30a86016f2..6e6ceb0de019 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -677,7 +677,7 @@ void intel_engines_release(struct intel_gt *gt) * in case we aborted before completely initialising the engines. */ GEM_BUG_ON(intel_gt_pm_is_awake(gt)); - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!intel_gt_gpu_reset_clobbers_display(gt)) intel_gt_reset_all_engines(gt); /* Decouple the backend; but keep the layout for late GPU resets */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index c08fdb65cc69..7d7a93e6db8f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -156,7 +156,7 @@ void intel_gt_pm_init(struct intel_gt *gt) static bool reset_engines(struct intel_gt *gt) { - if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (intel_gt_gpu_reset_clobbers_display(gt)) return false; return intel_gt_reset_all_engines(gt) == 0; diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 686be6edd2e3..0d863aa58fb6 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -986,7 +986,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt) awake = reset_prepare(gt); /* Even if the GPU reset fails, it should still stop the engines */ - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!intel_gt_gpu_reset_clobbers_display(gt)) intel_gt_reset_all_engines(gt); for_each_engine(engine, gt, id) @@ -1106,7 +1106,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt) /* We must reset pending GPU events before restoring our submission */ ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */ - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!intel_gt_gpu_reset_clobbers_display(gt)) ok = intel_gt_reset_all_engines(gt) == 0; if (!ok) { /* @@ -1178,6 +1178,13 @@ static int resume(struct intel_gt *gt) return 0; } +bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + + return INTEL_INFO(i915)->gpu_reset_clobbers_display; +} + /** * intel_gt_reset - reset chip after a hang * @gt: #intel_gt to reset @@ -1234,7 +1241,7 @@ void intel_gt_reset(struct intel_gt *gt, goto error; } - if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (intel_gt_gpu_reset_clobbers_display(gt)) intel_irq_suspend(gt->i915); if (do_reset(gt, stalled_mask)) { @@ -1242,7 +1249,7 @@ void intel_gt_reset(struct intel_gt *gt, goto taint; } - if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (intel_gt_gpu_reset_clobbers_display(gt)) intel_irq_resume(gt->i915); intel_overlay_reset(display); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h index c00de353075c..724ea6d64f33 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.h +++ b/drivers/gpu/drm/i915/gt/intel_reset.h @@ -28,6 +28,8 @@ void intel_gt_handle_error(struct intel_gt *gt, const char *fmt, ...); #define I915_ERROR_CAPTURE BIT(0) +bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt); + void intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask, const char *reason); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index c2ae37d6b94d..be44b66da310 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -201,7 +201,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) static void sanitize_gpu(struct drm_i915_private *i915) { - if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { + if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { struct intel_gt *gt; unsigned int i; From patchwork Wed Jan 8 10:41:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13930530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B915BE77199 for ; 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X-CSE-ConnectionGUID: 6LNmeYjPSrq7imVwm1A2xA== X-CSE-MsgGUID: HYj1ePPDRrGb3x7U7cLwHA== X-IronPort-AV: E=McAfee;i="6700,10204,11308"; a="47218542" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="47218542" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:46 -0800 X-CSE-ConnectionGUID: dB56m56DR4K4Yvt/RRphZQ== X-CSE-MsgGUID: mRbwThGoTWykqDVCwCLLgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="102979022" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:44 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 4/6] drm/i915/display: add intel_display_gpu_reset_clobbers_display() helper Date: Wed, 8 Jan 2025 12:41:19 +0200 Message-Id: <14809d0398a260febbeb0e4bf2c25f97cc3bb8d7.1736332802.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a helper for checking the gpu_reset_clobbers_display flag to make it easier to relocate the flag later. We keep the intel_gt_gpu_reset_clobbers_display() helper to not have to duplicate the gt -> display pointer chase. Signed-off-by: Jani Nikula Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_reset.c | 11 +++++++++-- drivers/gpu/drm/i915/display/intel_display_reset.h | 3 +++ drivers/gpu/drm/i915/gt/intel_reset.c | 3 ++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 1e6421d51c51..93399ace7761 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -13,12 +13,19 @@ #include "intel_hotplug.h" #include "intel_pps.h" +bool intel_display_gpu_reset_clobbers_display(struct intel_display *display) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + + return INTEL_INFO(i915)->gpu_reset_clobbers_display; +} + static bool gpu_reset_clobbers_display(struct intel_display *display) { struct drm_i915_private *i915 = to_i915(display->drm); - return (INTEL_INFO(i915)->gpu_reset_clobbers_display && - intel_has_gpu_reset(to_gt(i915))); + return intel_display_gpu_reset_clobbers_display(display) && + intel_has_gpu_reset(to_gt(i915)); } void intel_display_reset_prepare(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.h b/drivers/gpu/drm/i915/display/intel_display_reset.h index 9a1fe99bfcd4..5acc07aab7b5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.h +++ b/drivers/gpu/drm/i915/display/intel_display_reset.h @@ -6,9 +6,12 @@ #ifndef __INTEL_RESET_H__ #define __INTEL_RESET_H__ +#include + struct intel_display; void intel_display_reset_prepare(struct intel_display *display); void intel_display_reset_finish(struct intel_display *display); +bool intel_display_gpu_reset_clobbers_display(struct intel_display *display); #endif /* __INTEL_RESET_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 0d863aa58fb6..774caaaa4ce5 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1181,8 +1181,9 @@ static int resume(struct intel_gt *gt) bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; - return INTEL_INFO(i915)->gpu_reset_clobbers_display; + return intel_display_gpu_reset_clobbers_display(display); } /** From patchwork Wed Jan 8 10:41:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13930531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2959E77188 for ; Wed, 8 Jan 2025 10:41:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7311710E856; Wed, 8 Jan 2025 10:41:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Q5TV7DWh"; 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d="scan'208";a="47218603" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:50 -0800 X-CSE-ConnectionGUID: YHd79Xr5TP2K0jLWG5eG2g== X-CSE-MsgGUID: Z/7kbrZ1T/2v+WPENbdvBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="102979057" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:48 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 5/6] drm/i915: move gpu_reset_clobbers_display flag to display info Date: Wed, 8 Jan 2025 12:41:20 +0200 Message-Id: <80abf659262f193829e840db3c4d172731f08e33.1736332802.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Arguably it's a display property whether it's impacted by GPU reset. And we don't have to look at i915 device info from display. Reverse the flag usage for gen 4. Only set it for the affected platforms, instead of all gen 4 and disabling for the unaffected. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ drivers/gpu/drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_display_reset.c | 4 +--- drivers/gpu/drm/i915/i915_pci.c | 6 ------ drivers/gpu/drm/i915/intel_device_info.h | 1 - 5 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 68cb7f9b9ef3..365120f3c7e1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -226,6 +226,7 @@ static const struct intel_display_device_info no_display = {}; } #define I830_DISPLAY \ + .gpu_reset_clobbers_display = 1, \ .has_overlay = 1, \ .cursor_needs_physical = 1, \ .overlay_needs_physical = 1, \ @@ -240,6 +241,7 @@ static const struct intel_display_device_info no_display = {}; BIT(TRANSCODER_A) | BIT(TRANSCODER_B) #define I845_DISPLAY \ + .gpu_reset_clobbers_display = 1, \ .has_overlay = 1, \ .overlay_needs_physical = 1, \ .has_gmch = 1, \ @@ -292,6 +294,7 @@ static const struct platform_desc i865g_desc = { }; #define GEN3_DISPLAY \ + .gpu_reset_clobbers_display = 1, \ .has_gmch = 1, \ .has_overlay = 1, \ I9XX_PIPE_OFFSETS, \ @@ -395,6 +398,7 @@ static const struct platform_desc i965g_desc = { PLATFORM(i965g), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, + .gpu_reset_clobbers_display = 1, .has_overlay = 1, .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ @@ -406,6 +410,7 @@ static const struct platform_desc i965gm_desc = { PLATFORM_GROUP(mobile), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, + .gpu_reset_clobbers_display = 1, .has_overlay = 1, .supports_tv = 1, diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 9a333d9e6601..3876ca39b7dd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -124,6 +124,7 @@ struct intel_display_platforms { #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ + func(gpu_reset_clobbers_display); \ func(has_cdclk_crawl); \ func(has_cdclk_squash); \ func(has_ddi); \ diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 93399ace7761..e5c1650346fe 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -15,9 +15,7 @@ bool intel_display_gpu_reset_clobbers_display(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - return INTEL_INFO(i915)->gpu_reset_clobbers_display; + return DISPLAY_INFO(display)->gpu_reset_clobbers_display; } static bool gpu_reset_clobbers_display(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 21006c7f615c..85b325bafafe 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -80,7 +80,6 @@ __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for d #define I830_FEATURES \ GEN(2), \ .is_mobile = 1, \ - .gpu_reset_clobbers_display = true, \ .has_3d_pipeline = 1, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ @@ -96,7 +95,6 @@ __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for d #define I845_FEATURES \ GEN(2), \ .has_3d_pipeline = 1, \ - .gpu_reset_clobbers_display = true, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ .platform_engine_mask = BIT(RCS0), \ @@ -130,7 +128,6 @@ static const struct intel_device_info i865g_info = { #define GEN3_FEATURES \ GEN(3), \ - .gpu_reset_clobbers_display = true, \ .platform_engine_mask = BIT(RCS0), \ .has_3d_pipeline = 1, \ .has_snoop = true, \ @@ -193,7 +190,6 @@ static const struct intel_device_info pnv_m_info = { #define GEN4_FEATURES \ GEN(4), \ - .gpu_reset_clobbers_display = true, \ .platform_engine_mask = BIT(RCS0), \ .has_3d_pipeline = 1, \ .has_snoop = true, \ @@ -223,7 +219,6 @@ static const struct intel_device_info g45_info = { GEN4_FEATURES, PLATFORM(INTEL_G45), .platform_engine_mask = BIT(RCS0) | BIT(VCS0), - .gpu_reset_clobbers_display = false, }; static const struct intel_device_info gm45_info = { @@ -231,7 +226,6 @@ static const struct intel_device_info gm45_info = { PLATFORM(INTEL_GM45), .is_mobile = 1, .platform_engine_mask = BIT(RCS0) | BIT(VCS0), - .gpu_reset_clobbers_display = false, }; #define GEN5_FEATURES \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 9387385cb418..7296e7dcf828 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -148,7 +148,6 @@ enum intel_ppgtt_type { /* Keep has_* in alphabetical order */ \ func(has_64bit_reloc); \ func(has_64k_pages); \ - func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_3d_pipeline); \ func(has_flat_ccs); \ From patchwork Wed Jan 8 10:41:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13930532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED9B6E77199 for ; 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X-CSE-ConnectionGUID: kbRbAw4xS7edxAcghG4QGg== X-CSE-MsgGUID: qifmInSfRxaxPizWdVGf4Q== X-IronPort-AV: E=McAfee;i="6700,10204,11308"; a="47218656" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="47218656" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:54 -0800 X-CSE-ConnectionGUID: R+RmgpBeQXWgI+ASHJSdzA== X-CSE-MsgGUID: 3Gv5EeVXSTa1iU+/cA1EIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="102979100" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.152]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 02:41:53 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 6/6] drm/i915/display: convert intel_ddi_buf_trans.c to struct intel_display Date: Wed, 8 Jan 2025 12:41:21 +0200 Message-Id: <89471eb566ac2d73520124b9bcb36550234d5a03.1736332802.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Going forward, struct intel_display is the main device data structure for display. Switch to it. For MISSING_CASE(), log the PCI ID instead of the platform. This removes the final INTEL_INFO() usage from display. Signed-off-by: Jani Nikula Reviewed-by: Matt Roper --- .../drm/i915/display/intel_ddi_buf_trans.c | 58 +++++++++++-------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 9389b295036e..a238be5bc455 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -3,13 +3,13 @@ * Copyright © 2020 Intel Corporation */ -#include "i915_drv.h" +#include "i915_utils.h" +#include "intel_cx0_phy.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" -#include "intel_cx0_phy.h" /* HDMI/DVI modes ignore everything but the last 2 items. So we share * them for both DP and FDI transports, allowing those ports to @@ -1407,10 +1407,10 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); if (crtc_state->port_clock > 270000) { - if (IS_TIGERLAKE_UY(dev_priv)) { + if (display->platform.tigerlake_uy) { return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, n_entries); } else { @@ -1709,59 +1709,67 @@ mtl_get_c20_buf_trans(struct intel_encoder *encoder, void intel_ddi_buf_trans_init(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER(display) >= 14) { if (intel_encoder_is_c10phy(encoder)) encoder->get_buf_trans = mtl_get_c10_buf_trans; else encoder->get_buf_trans = mtl_get_c20_buf_trans; - } else if (IS_DG2(i915)) { + } else if (display->platform.dg2) { encoder->get_buf_trans = dg2_get_snps_buf_trans; - } else if (IS_ALDERLAKE_P(i915)) { + } else if (display->platform.alderlake_p) { if (intel_encoder_is_combo(encoder)) encoder->get_buf_trans = adlp_get_combo_buf_trans; else encoder->get_buf_trans = adlp_get_dkl_buf_trans; - } else if (IS_ALDERLAKE_S(i915)) { + } else if (display->platform.alderlake_s) { encoder->get_buf_trans = adls_get_combo_buf_trans; - } else if (IS_ROCKETLAKE(i915)) { + } else if (display->platform.rocketlake) { encoder->get_buf_trans = rkl_get_combo_buf_trans; - } else if (IS_DG1(i915)) { + } else if (display->platform.dg1) { encoder->get_buf_trans = dg1_get_combo_buf_trans; - } else if (DISPLAY_VER(i915) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { if (intel_encoder_is_combo(encoder)) encoder->get_buf_trans = tgl_get_combo_buf_trans; else encoder->get_buf_trans = tgl_get_dkl_buf_trans; - } else if (DISPLAY_VER(i915) == 11) { - if (IS_JASPERLAKE(i915)) + } else if (DISPLAY_VER(display) == 11) { + if (display->platform.jasperlake) encoder->get_buf_trans = jsl_get_combo_buf_trans; - else if (IS_ELKHARTLAKE(i915)) + else if (display->platform.elkhartlake) encoder->get_buf_trans = ehl_get_combo_buf_trans; else if (intel_encoder_is_combo(encoder)) encoder->get_buf_trans = icl_get_combo_buf_trans; else encoder->get_buf_trans = icl_get_mg_buf_trans; - } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { + } else if (display->platform.geminilake || display->platform.broxton) { encoder->get_buf_trans = bxt_get_buf_trans; - } else if (IS_COMETLAKE_ULX(i915) || IS_COFFEELAKE_ULX(i915) || IS_KABYLAKE_ULX(i915)) { + } else if (display->platform.cometlake_ulx || + display->platform.coffeelake_ulx || + display->platform.kabylake_ulx) { encoder->get_buf_trans = kbl_y_get_buf_trans; - } else if (IS_COMETLAKE_ULT(i915) || IS_COFFEELAKE_ULT(i915) || IS_KABYLAKE_ULT(i915)) { + } else if (display->platform.cometlake_ult || + display->platform.coffeelake_ult || + display->platform.kabylake_ult) { encoder->get_buf_trans = kbl_u_get_buf_trans; - } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { + } else if (display->platform.cometlake || + display->platform.coffeelake || + display->platform.kabylake) { encoder->get_buf_trans = kbl_get_buf_trans; - } else if (IS_SKYLAKE_ULX(i915)) { + } else if (display->platform.skylake_ulx) { encoder->get_buf_trans = skl_y_get_buf_trans; - } else if (IS_SKYLAKE_ULT(i915)) { + } else if (display->platform.skylake_ult) { encoder->get_buf_trans = skl_u_get_buf_trans; - } else if (IS_SKYLAKE(i915)) { + } else if (display->platform.skylake) { encoder->get_buf_trans = skl_get_buf_trans; - } else if (IS_BROADWELL(i915)) { + } else if (display->platform.broadwell) { encoder->get_buf_trans = bdw_get_buf_trans; - } else if (IS_HASWELL(i915)) { + } else if (display->platform.haswell) { encoder->get_buf_trans = hsw_get_buf_trans; } else { - MISSING_CASE(INTEL_INFO(i915)->platform); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); + + MISSING_CASE(pdev->device); } }