From patchwork Wed Jan 8 13:55:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karolina Stolarek X-Patchwork-Id: 13930978 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 666F61FC7E8 for ; Wed, 8 Jan 2025 13:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.165.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736344552; cv=none; b=ADROYGO6XDLz1rjRxAIKbKzKwYNcSLvmQIllNCQWdE0ZW9ne9YPSFAwEdVv3HFYfKaxejue3hcTkHQLcXvQC+SeY73IsgvToom8de4HCrrU0bisi5qHF6yOEiP/gz10v78SNPjeGiePLVqaYnqDa22xJO++COF8ISUDoCRVXARo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736344552; c=relaxed/simple; bh=cE+CkEfdYfYmu0Pe/5GPYizeJq6asGOES1Wjx2/ScKI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rKh0e3Z/f4DKJGy6Cl6peul4+AECAI6ZXdl5KefOzt9nszqeRlxKdmOkG2TcEF+LrDqMMygcapiSVKahtfrB58MIWAcU3kYVJBm37QpTLBob8lb3rQm1BjWRSP2j3XmCI7yIhbEo/398fWIsNjlUiIoQEwPIcSQe+oqm8yzu7Oo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oracle.com; spf=pass smtp.mailfrom=oracle.com; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b=TApuNS1c; arc=none smtp.client-ip=205.220.165.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oracle.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oracle.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b="TApuNS1c" Received: from pps.filterd (m0246627.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5081u3u8015483; Wed, 8 Jan 2025 13:55:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=E1N2H JvPbEq4aJi2zzN6ZikHJ+Zv4mP4gsJPpOeMWK4=; b=TApuNS1cDsguqynT0JTDd RGGhSdyujm2ds4w6ug6fBvtag7q8Hz5SjZB6PRUqhI4fa0yOuC/RfdEiwU6sYAF2 YgS4Rk8bkw6wXIQgXcL3vBxLvaTrcuJuXs37keNdkuZZqdOA81XOWepTCx4POJfI J/GIhxT1hdBhM8P4GCbtxPeT5TBCwBH8laQbsBfWpefNERRcUz9b6651X3y22L/t 9zb4KAp9aKoqd0hbsI++U+LVaT28+3/nF2/3lbz4OdlafXrHKfPZQ55gGRCRPZDW vbcj/O39qo7flxl6FSMbl+SV/yTKMk1DCvdsWrPYjxo0y5RKgpvQ4XZs/bAR5NO/ Q== Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.appoci.oracle.com [138.1.114.2]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 43xuk074rr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 08 Jan 2025 13:55:48 +0000 (GMT) Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 508C7Dp6026550; Wed, 8 Jan 2025 13:55:47 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 43xuea1g91-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 08 Jan 2025 13:55:47 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 508Dtjww011911; Wed, 8 Jan 2025 13:55:47 GMT Received: from kstolare-e5-ol8.osdevelopmeniad.oraclevcn.com (kstolare-e5-ol8.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.20]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 43xuea1g3k-2; Wed, 08 Jan 2025 13:55:47 +0000 From: Karolina Stolarek To: linux-pci@vger.kernel.org Cc: Bjorn Helgaas , Martin Petersen , Ben Fuller Subject: [PATCH RESEND 1/4] PCI/AER: Use the same log level for all messages Date: Wed, 8 Jan 2025 13:55:31 +0000 Message-ID: X-Mailer: git-send-email 2.43.5 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-08_03,2025-01-08_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2411120000 definitions=main-2501080115 X-Proofpoint-ORIG-GUID: rZuyMjH47WkltiRYA2zTpXJ_BD8liqEz X-Proofpoint-GUID: rZuyMjH47WkltiRYA2zTpXJ_BD8liqEz When reporting an AER error, we check its type multiple times to determine the log level for each message. Do this check only in the top-level function and propagate the result down the call chain. Make aer_print_port_info output to match the level of the reported error. Signed-off-by: Karolina Stolarek --- drivers/pci/pci.h | 2 +- drivers/pci/pcie/aer.c | 64 ++++++++++++++++++++++-------------------- drivers/pci/pcie/dpc.c | 2 +- 3 files changed, 36 insertions(+), 32 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2e40fc63ba31..139ea4f01448 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -546,7 +546,7 @@ struct aer_err_info { }; int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); -void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); +void aer_print_error(struct pci_dev *dev, struct aer_err_info *info, const char *level); #endif /* CONFIG_PCIEAER */ #ifdef CONFIG_PCIEPORTBUS diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 80c5ba8d8296..b13690fd172f 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -672,20 +672,18 @@ static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t) } static void __aer_print_error(struct pci_dev *dev, - struct aer_err_info *info) + struct aer_err_info *info, + const char *level) { const char **strings; unsigned long status = info->status & ~info->mask; - const char *level, *errmsg; + const char *errmsg; int i; - if (info->severity == AER_CORRECTABLE) { + if (info->severity == AER_CORRECTABLE) strings = aer_correctable_error_string; - level = KERN_WARNING; - } else { + else strings = aer_uncorrectable_error_string; - level = KERN_ERR; - } for_each_set_bit(i, &status, 32) { errmsg = strings[i]; @@ -698,11 +696,11 @@ static void __aer_print_error(struct pci_dev *dev, pci_dev_aer_stats_incr(dev, info); } -void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) +void aer_print_error(struct pci_dev *dev, struct aer_err_info *info, + const char *level) { int layer, agent; int id = pci_dev_id(dev); - const char *level; if (!info->status) { pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", @@ -713,8 +711,6 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) layer = AER_GET_LAYER_ERROR(info->severity, info->status); agent = AER_GET_AGENT(info->severity, info->status); - level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; - pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); @@ -722,7 +718,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", dev->vendor, dev->device, info->status, info->mask); - __aer_print_error(dev, info); + __aer_print_error(dev, info, level); if (info->tlp_header_valid) __print_tlp_header(dev, &info->tlp); @@ -735,16 +731,17 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) info->severity, info->tlp_header_valid, &info->tlp); } -static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) +static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info, + const char *level) { u8 bus = info->id >> 8; u8 devfn = info->id & 0xff; - pci_info(dev, "%s%s error message received from %04x:%02x:%02x.%d\n", - info->multi_error_valid ? "Multiple " : "", - aer_error_severity_string[info->severity], - pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), - PCI_FUNC(devfn)); + pci_printk(level, dev, "%s%s error message received from %04x:%02x:%02x.%d\n", + info->multi_error_valid ? "Multiple " : "", + aer_error_severity_string[info->severity], + pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), + PCI_FUNC(devfn)); } #ifdef CONFIG_ACPI_APEI_PCIEAER @@ -767,15 +764,18 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, { int layer, agent, tlp_header_valid = 0; u32 status, mask; + const char *level; struct aer_err_info info; if (aer_severity == AER_CORRECTABLE) { status = aer->cor_status; mask = aer->cor_mask; + level = KERN_WARNING; } else { status = aer->uncor_status; mask = aer->uncor_mask; tlp_header_valid = status & AER_LOG_TLP_MASKS; + level = KERN_ERR; } layer = AER_GET_LAYER_ERROR(aer_severity, status); @@ -787,14 +787,14 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, info.mask = mask; info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); - pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); - __aer_print_error(dev, &info); - pci_err(dev, "aer_layer=%s, aer_agent=%s\n", - aer_error_layer[layer], aer_agent_string[agent]); + pci_printk(level, dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); + __aer_print_error(dev, &info, level); + pci_printk(level, dev, "aer_layer=%s, aer_agent=%s\n", + aer_error_layer[layer], aer_agent_string[agent]); if (aer_severity != AER_CORRECTABLE) - pci_err(dev, "aer_uncor_severity: 0x%08x\n", - aer->uncor_severity); + pci_printk(level, dev, "aer_uncor_severity: 0x%08x\n", + aer->uncor_severity); if (tlp_header_valid) __print_tlp_header(dev, &aer->header_log); @@ -1255,14 +1255,15 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) return 1; } -static inline void aer_process_err_devices(struct aer_err_info *e_info) +static inline void aer_process_err_devices(struct aer_err_info *e_info, + const char *level) { int i; /* Report all before handle them, not to lost records by reset etc. */ for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { if (aer_get_device_error_info(e_info->dev[i], e_info)) - aer_print_error(e_info->dev[i], e_info); + aer_print_error(e_info->dev[i], e_info, level); } for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { if (aer_get_device_error_info(e_info->dev[i], e_info)) @@ -1280,6 +1281,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, { struct pci_dev *pdev = rpc->rpd; struct aer_err_info e_info; + const char *level; pci_rootport_aer_stats_incr(pdev, e_src); @@ -1290,19 +1292,21 @@ static void aer_isr_one_error(struct aer_rpc *rpc, if (e_src->status & PCI_ERR_ROOT_COR_RCV) { e_info.id = ERR_COR_ID(e_src->id); e_info.severity = AER_CORRECTABLE; + level = KERN_WARNING; if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) e_info.multi_error_valid = 1; else e_info.multi_error_valid = 0; - aer_print_port_info(pdev, &e_info); + aer_print_port_info(pdev, &e_info, level); if (find_source_device(pdev, &e_info)) - aer_process_err_devices(&e_info); + aer_process_err_devices(&e_info, level); } if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { e_info.id = ERR_UNCOR_ID(e_src->id); + level = KERN_ERR; if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) e_info.severity = AER_FATAL; @@ -1314,10 +1318,10 @@ static void aer_isr_one_error(struct aer_rpc *rpc, else e_info.multi_error_valid = 0; - aer_print_port_info(pdev, &e_info); + aer_print_port_info(pdev, &e_info, level); if (find_source_device(pdev, &e_info)) - aer_process_err_devices(&e_info); + aer_process_err_devices(&e_info, level); } } diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index 2b6ef7efa3c1..9e48d571d9e7 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -291,7 +291,7 @@ void dpc_process_error(struct pci_dev *pdev) else if (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR && dpc_get_aer_uncorrect_severity(pdev, &info) && aer_get_device_error_info(pdev, &info)) { - aer_print_error(pdev, &info); + aer_print_error(pdev, &info, KERN_ERR); pci_aer_clear_nonfatal_status(pdev); pci_aer_clear_fatal_status(pdev); } From patchwork Wed Jan 8 13:55:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karolina Stolarek X-Patchwork-Id: 13930980 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E79551514F8 for ; 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Wed, 08 Jan 2025 13:55:49 +0000 (GMT) Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 508CiWJY026396; Wed, 8 Jan 2025 13:55:49 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 43xuea1ga0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 08 Jan 2025 13:55:49 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 508Dtjx0011911; Wed, 8 Jan 2025 13:55:48 GMT Received: from kstolare-e5-ol8.osdevelopmeniad.oraclevcn.com (kstolare-e5-ol8.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.20]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 43xuea1g3k-3; Wed, 08 Jan 2025 13:55:48 +0000 From: Karolina Stolarek To: linux-pci@vger.kernel.org Cc: Bjorn Helgaas , Martin Petersen , Ben Fuller Subject: [PATCH RESEND 2/4] PCI/AER: Add Correctable Errors rate limiting Date: Wed, 8 Jan 2025 13:55:32 +0000 Message-ID: <68ef082c855b4e1d094dcfc9a861f43488b64922.1736341506.git.karolina.stolarek@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-08_03,2025-01-08_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2411120000 definitions=main-2501080115 X-Proofpoint-GUID: rfEiCrvnEFDe72j7Q9Cs8T_VHdsS9Qax X-Proofpoint-ORIG-GUID: rfEiCrvnEFDe72j7Q9Cs8T_VHdsS9Qax In the case of a compromised Link integrity, we may see excessive logging of Correctable Errors. This kind of errors is handled by the hardware, so the messages are purely informational. It should suffice to report the error once in a while, and inform how many messages were suppressed over that time. Add a ratelimit_state to control the number of printed Correctable Errors per Root Port and check it each time a Correctable Error is to be reported. Signed-off-by: Karolina Stolarek --- drivers/pci/pcie/aer.c | 44 ++++++++++++++++++++++++++++-------------- include/linux/pci.h | 1 + 2 files changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index b13690fd172f..5c34cc2b5bf3 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -40,6 +40,8 @@ #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ +#define AER_COR_ERR_INTERVAL (2 * HZ) + struct aer_err_source { u32 status; /* PCI_ERR_ROOT_STATUS */ u32 id; /* PCI_ERR_ROOT_ERR_SRC */ @@ -375,6 +377,9 @@ void pci_aer_init(struct pci_dev *dev) dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); + /* Allow Root Port to report a Correctable Error message every 2 seconds */ + ratelimit_state_init(&dev->cor_rs, AER_COR_ERR_INTERVAL, 1); + /* * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event @@ -766,11 +771,13 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, u32 status, mask; const char *level; struct aer_err_info info; + bool no_ratelimit = true; if (aer_severity == AER_CORRECTABLE) { status = aer->cor_status; mask = aer->cor_mask; level = KERN_WARNING; + no_ratelimit = __ratelimit(&dev->cor_rs); } else { status = aer->uncor_status; mask = aer->uncor_mask; @@ -787,17 +794,20 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, info.mask = mask; info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); - pci_printk(level, dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); - __aer_print_error(dev, &info, level); - pci_printk(level, dev, "aer_layer=%s, aer_agent=%s\n", - aer_error_layer[layer], aer_agent_string[agent]); + if (no_ratelimit) { + pci_printk(level, dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", + status, mask); + __aer_print_error(dev, &info, level); + pci_printk(level, dev, "aer_layer=%s, aer_agent=%s\n", + aer_error_layer[layer], aer_agent_string[agent]); - if (aer_severity != AER_CORRECTABLE) - pci_printk(level, dev, "aer_uncor_severity: 0x%08x\n", - aer->uncor_severity); + if (aer_severity != AER_CORRECTABLE) + pci_printk(level, dev, "aer_uncor_severity: 0x%08x\n", + aer->uncor_severity); - if (tlp_header_valid) - __print_tlp_header(dev, &aer->header_log); + if (tlp_header_valid) + __print_tlp_header(dev, &aer->header_log); + } trace_aer_event(dev_name(&dev->dev), (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); @@ -1256,13 +1266,14 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) } static inline void aer_process_err_devices(struct aer_err_info *e_info, - const char *level) + const char *level, + bool no_ratelimit) { int i; /* Report all before handle them, not to lost records by reset etc. */ for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { - if (aer_get_device_error_info(e_info->dev[i], e_info)) + if (aer_get_device_error_info(e_info->dev[i], e_info) && no_ratelimit) aer_print_error(e_info->dev[i], e_info, level); } for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { @@ -1282,6 +1293,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, struct pci_dev *pdev = rpc->rpd; struct aer_err_info e_info; const char *level; + bool no_ratelimit = true; pci_rootport_aer_stats_incr(pdev, e_src); @@ -1298,10 +1310,14 @@ static void aer_isr_one_error(struct aer_rpc *rpc, e_info.multi_error_valid = 1; else e_info.multi_error_valid = 0; - aer_print_port_info(pdev, &e_info, level); + + no_ratelimit = __ratelimit(&pdev->cor_rs); + + if (no_ratelimit) + aer_print_port_info(pdev, &e_info, level); if (find_source_device(pdev, &e_info)) - aer_process_err_devices(&e_info, level); + aer_process_err_devices(&e_info, level, no_ratelimit); } if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { @@ -1321,7 +1337,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, aer_print_port_info(pdev, &e_info, level); if (find_source_device(pdev, &e_info)) - aer_process_err_devices(&e_info, level); + aer_process_err_devices(&e_info, level, no_ratelimit); } } diff --git a/include/linux/pci.h b/include/linux/pci.h index b5eb8bda655d..a736547396ca 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -347,6 +347,7 @@ struct pci_dev { #ifdef CONFIG_PCIEAER u16 aer_cap; /* AER capability offset */ struct aer_stats *aer_stats; /* AER stats for this device */ + struct ratelimit_state cor_rs; /* Correctable Errors Ratelimit */ #endif #ifdef CONFIG_PCIEPORTBUS struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ From patchwork Wed Jan 8 13:55:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karolina Stolarek X-Patchwork-Id: 13930981 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 895891FCCF3 for ; Wed, 8 Jan 2025 13:55:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 08 Jan 2025 13:55:51 +0000 (GMT) Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 508C4Y4T027555; Wed, 8 Jan 2025 13:55:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 43xuea1gb2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 08 Jan 2025 13:55:50 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 508Dtjx2011911; Wed, 8 Jan 2025 13:55:50 GMT Received: from kstolare-e5-ol8.osdevelopmeniad.oraclevcn.com (kstolare-e5-ol8.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.20]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 43xuea1g3k-4; Wed, 08 Jan 2025 13:55:50 +0000 From: Karolina Stolarek To: linux-pci@vger.kernel.org Cc: Bjorn Helgaas , Martin Petersen , Ben Fuller Subject: [PATCH RESEND 3/4] PCI/AER: Increase the rate limit interval after threshold Date: Wed, 8 Jan 2025 13:55:33 +0000 Message-ID: <4bd41a1538e4eb92586ea464a5b221c5f259344f.1736341506.git.karolina.stolarek@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-08_03,2025-01-08_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2411120000 definitions=main-2501080115 X-Proofpoint-GUID: _q_BTNYz6hz1p1I6tar8UwBNDqhCGRPB X-Proofpoint-ORIG-GUID: _q_BTNYz6hz1p1I6tar8UwBNDqhCGRPB In extreme circumstances, the default rate limit might not be enough and a longer timeout is needed. To avoid spamming the logs, update the interval to 30 seconds for the specific Root Port after it observes over 1000 Correctable Errors. Signed-off-by: Karolina Stolarek --- drivers/pci/pcie/aer.c | 22 +++++++++++++++++++++- include/linux/pci.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 5c34cc2b5bf3..98bf8bbadc07 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -40,7 +40,9 @@ #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ +#define AER_COR_ERR_THRESHOLD 1000 #define AER_COR_ERR_INTERVAL (2 * HZ) +#define AER_COR_ERR_LONG_INTERVAL (30 * HZ) struct aer_err_source { u32 status; /* PCI_ERR_ROOT_STATUS */ @@ -670,6 +672,24 @@ static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, } } +static bool report_aer_cor_err(struct pci_dev *pdev) +{ + struct ratelimit_state *rs = &pdev->cor_rs; + struct aer_stats *aer_stats = pdev->aer_stats; + unsigned int total_cor_errs = aer_stats->rootport_total_cor_errs; + + /* A significant number of errors reported, increase the rate limit */ + if (total_cor_errs > AER_COR_ERR_THRESHOLD && !pdev->cor_err_throttled) { + pci_warn(pdev, + "Over %d Correctable Errors reported, increasing the rate limit", + AER_COR_ERR_THRESHOLD); + rs->interval = AER_COR_ERR_LONG_INTERVAL; + pdev->cor_err_throttled = 1; + } + + return __ratelimit(&pdev->cor_rs); +} + static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t) { pci_err(dev, " TLP Header: %08x %08x %08x %08x\n", @@ -1311,7 +1331,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, else e_info.multi_error_valid = 0; - no_ratelimit = __ratelimit(&pdev->cor_rs); + no_ratelimit = report_aer_cor_err(pdev); if (no_ratelimit) aer_print_port_info(pdev, &e_info, level); diff --git a/include/linux/pci.h b/include/linux/pci.h index a736547396ca..6b062b1fcd3c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -348,6 +348,7 @@ struct pci_dev { u16 aer_cap; /* AER capability offset */ struct aer_stats *aer_stats; /* AER stats for this device */ struct ratelimit_state cor_rs; /* Correctable Errors Ratelimit */ + unsigned int cor_err_throttled:1; #endif #ifdef CONFIG_PCIEPORTBUS struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ From patchwork Wed Jan 8 13:55:34 2025 Content-Type: text/plain; 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Wed, 8 Jan 2025 13:55:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 43xuea1gc5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 08 Jan 2025 13:55:52 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 508Dtjx4011911; Wed, 8 Jan 2025 13:55:51 GMT Received: from kstolare-e5-ol8.osdevelopmeniad.oraclevcn.com (kstolare-e5-ol8.allregionaliads.osdevelopmeniad.oraclevcn.com [100.100.254.20]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 43xuea1g3k-5; Wed, 08 Jan 2025 13:55:51 +0000 From: Karolina Stolarek To: linux-pci@vger.kernel.org Cc: Bjorn Helgaas , Martin Petersen , Ben Fuller Subject: [PATCH RESEND 4/4] PCI: Add 'cor_err_reporting_enable' attribute Date: Wed, 8 Jan 2025 13:55:34 +0000 Message-ID: <2c0fb509158d31b89f9a3faa099efa956967c011.1736341506.git.karolina.stolarek@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-08_03,2025-01-08_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2411120000 definitions=main-2501080115 X-Proofpoint-GUID: BW2GzQVqM5cYf_VRmWcMi5tNzn8z__nS X-Proofpoint-ORIG-GUID: BW2GzQVqM5cYf_VRmWcMi5tNzn8z__nS In some cases, the number of Correctable Error messages is overwhelming, and even with the rate limit imposed, they fill up the logs. The system cannot do much about such errors, so a user might wish to silence them completely. Add a sysfs attribute to control reporting of the Correctable Error Messages per device. Signed-off-by: Karolina Stolarek --- Documentation/ABI/testing/sysfs-bus-pci | 7 +++++ drivers/pci/pci-sysfs.c | 42 +++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 5da6a14dc326..dba72ee37ce4 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -479,6 +479,13 @@ Description: The file is writable if the PF is bound to a driver that implements ->sriov_set_msix_vec_count(). +What: /sys/bus/pci/devices/.../cor_err_reporting_enable +Date: December 2024 +Contact: Linux PCI developers +Description: + This file exposes a bit to control sending of Correctable Error + Messages. The value comes from the Device Control register. + What: /sys/bus/pci/devices/.../resourceN_resize Date: September 2022 Contact: Alex Williamson diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 6f1bb7514efb..f7f0d7971ad7 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -186,6 +186,47 @@ static ssize_t resource_show(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RO(resource); +static ssize_t cor_err_reporting_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + u16 reg; + int err; + + err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, ®); + + if (err) + return pcibios_err_to_errno(err); + + return sysfs_emit(buf, "%u\n", reg & PCI_EXP_DEVCTL_CERE); +} + +static ssize_t cor_err_reporting_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pci_dev *pdev = to_pci_dev(dev); + u16 reg; + u8 val; + int err; + + if (kstrtou8(buf, 0, &val) < 0) + return -EINVAL; + + pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, ®); + + reg &= ~PCI_EXP_DEVCTL_CERE; + reg |= val; + err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, reg); + + if (err) + return pcibios_err_to_errno(err); + + return count; +} +static DEVICE_ATTR_RW(cor_err_reporting_enable); + static ssize_t max_link_speed_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -659,6 +700,7 @@ static struct attribute *pcie_dev_attrs[] = { &dev_attr_current_link_width.attr, &dev_attr_max_link_width.attr, &dev_attr_max_link_speed.attr, + &dev_attr_cor_err_reporting_enable.attr, NULL, };