From patchwork Wed Jan 8 15:01:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13931111 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 369811FCFE3 for ; Wed, 8 Jan 2025 14:43:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347399; cv=none; b=dmMbdbi9tH4g8C1K/oa4CXeYNrLlRxvFzj2RpWs0QtdMz+7xcFMcduDW0xxz8WTs7Dxb4Mfg9cdo3sedcFjD7D54ckD203k9Q7YeA+4STvXfl5kazcDvWdwz8W4HncDg/DId1DiQADzcn77tsQENygaISGaxm78E4XGsy2GMjyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347399; c=relaxed/simple; bh=roMx6NLgvG1w2UZlck/tSjXRrw4hdWLyk6vWSzvqPQI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z3Qh06nPxjip4Ldahjfkt86ghotB8tEEtQUFe96u0nR0zGdwMUG8fy+7AQYN97hNVjdHRiaw6ZVD3bCaEua53DvFbCoxGNC+AVji3/8OaCvYBILUhppNeGFXcYq95jluQaAegPS+2/S12TbNWASmp7dpQAVph7/IN2fXX+i1oMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eoffBv/p; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eoffBv/p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736347397; x=1767883397; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=roMx6NLgvG1w2UZlck/tSjXRrw4hdWLyk6vWSzvqPQI=; b=eoffBv/p7mLejb9m1oG16/DZTgPPCGH+XleDI7D1pGW0/ttHoK8GPOYr IW1LmQC473wAWALQRkAJbGtVOEWl6PKFUXSxbEWlndvFO1BuSuqPujL2I 841WROmcS3k8fOekXwaC+FweIRW9i2uJ+/QcruwKYxQQYEyhojmUsLAhe nZeLUcj8HXkOr7dTlAHtiMewYehRM2mRuJm3a9H/oaoAK27idkOhB3BQr yJ67sqqNVEVx8hN7V9hzDqGtmTiFklwMVBz2ScJ/MM7cxzETudag8Jold dW7t6Pw1ea5w+LF/54byGe2JMQ8rpAAZc2efdpb0m+yEOi0uAkK9H25pb A==; X-CSE-ConnectionGUID: Am4t4oafSq620rr8omJgbQ== X-CSE-MsgGUID: 5WZs7MdkQUGQgvsLIHKDiA== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="36737347" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="36737347" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 06:43:17 -0800 X-CSE-ConnectionGUID: 2i5G/sg9RIKwJW2uz0Nc0A== X-CSE-MsgGUID: 59Xo8U8iTim5ohGRbQs+ow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103969389" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa008.jf.intel.com with ESMTP; 08 Jan 2025 06:43:13 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH v7 1/5] hw/core/machine: Reject thread level cache Date: Wed, 8 Jan 2025 23:01:46 +0800 Message-Id: <20250108150150.1258529-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108150150.1258529-1-zhao1.liu@intel.com> References: <20250108150150.1258529-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently, neither i386 nor ARM have real hardware support for per- thread cache, and there is no clear demand for this specific cache topology. Additionally, since supporting this special cache topology on ARM requires extra effort [1], it is unnecessary to support it at this moment, even though per-thread cache might have potential scheduling benefits for VMs without CPU affinity. Therefore, disable thread-level cache topology in the general machine part. At present, i386 has not enabled SMP cache, so disabling the thread parameter does not pose compatibility issues. In the future, if there is a clear demand for this feature, the correct approach would be to add a new control field in MachineClass.smp_props and enable it only for the machines that require it. [1]: https://lore.kernel.org/qemu-devel/Z3efFsigJ6SxhqMf@intel.com/#t Signed-off-by: Zhao Liu --- Changes since Patch v6: * New commit to reject "thread" parameter when parse smp-cache. --- hw/core/machine-smp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index b954eb849027..4e020c358b66 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -321,6 +321,13 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } + if (props->topology == CPU_TOPOLOGY_LEVEL_THREAD) { + error_setg(errp, + "%s level cache not supported by this machine", + CpuTopologyLevel_str(props->topology)); + return false; + } + if (!machine_check_topo_support(ms, props->topology, errp)) { return false; } From patchwork Wed Jan 8 15:01:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13931112 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B75F1FCFE3 for ; Wed, 8 Jan 2025 14:43:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347402; cv=none; b=Mf42m2w8+QmOCRvXRtilmdOvUuxPbI2HrLScbjvu6mRmdrd9jBLnJfZ6pVziwSoruZZTpT3BYyQy/+TtnzH/CuxhslHg0Eat6ShUtOKya6Fhi7tOjdZxEnDpT223Pkpym9FlZtDiy8ZR4qJJDMz60kws2HDzdcgyF32vHPnjkCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347402; c=relaxed/simple; bh=shkMAuvJ+JiK4YmkroyLIrAGyT0tA05DVR9Yl2i03nc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rN1squ0D/j27zftFKoBTUDmoaPSDvi3hflrVLb6xWElWJk0yzYlzARuDTcVP1KcuWzXenl6rtAb7z5RNb6LdBlLbe+4paE43lc6H6hVyiMvjwJ+Geub7MGSGQviEcHk67CkwmFyuW0BhKbQtn8c5N+DfMHcHRB8O5PzyShaCER4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IaMhKVlB; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IaMhKVlB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736347401; x=1767883401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=shkMAuvJ+JiK4YmkroyLIrAGyT0tA05DVR9Yl2i03nc=; b=IaMhKVlB51EfHHSgJrr03Byz3i/HZbNp+UQmXYZ1zuVYQWkyS7NBppib VliINBwIBLNg185F8t7VSFCm/B3EiDS4FgCkweLvD+B8YlItgYzDcrvzb 9NkE4qKZuHTHAaOcCEJK+VBBLKgzLH9yxh4t2r6qIf3FP1ObLVwuQ4W6k 2//HCsjAdAxIWpn4HDYotsqWALOS27FXHwGtSTobAF/Dgfacfer0V+nF9 3I3ae7WyLw5OtLvXQKvAk+fdIc1OSjHgqKMHxBixK7WU1PDqe8nxGK3yG D7oH+hUv+sqyyLFP2BZ63Vxn1hf7l2qdQGhmKTBzlvWULIQVNh4XdSi5M A==; X-CSE-ConnectionGUID: N9F4M68CRjyeokAcJR4Hzw== X-CSE-MsgGUID: OPTjQCEqRWuTnipP7obTaw== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="36737356" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="36737356" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 06:43:21 -0800 X-CSE-ConnectionGUID: IK+/jtcHRViL2nJ9I7BNRA== X-CSE-MsgGUID: QRk5frgmTCG2FQ9lUtPUQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103969393" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa008.jf.intel.com with ESMTP; 08 Jan 2025 06:43:17 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v7 2/5] i386/cpu: Support module level cache topology Date: Wed, 8 Jan 2025 23:01:47 +0800 Message-Id: <20250108150150.1258529-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108150150.1258529-1-zhao1.liu@intel.com> References: <20250108150150.1258529-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow cache to be defined at the module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v6: * Dropped "thread" level cache topology support. --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 660ddafc28b5..4728373fdf03 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -247,6 +247,9 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -255,7 +258,7 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, break; default: /* - * Currently there is no use case for THREAD and MODULE, so use + * Currently there is no use case for THREAD, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); From patchwork Wed Jan 8 15:01:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13931113 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 313F81FF5EC for ; Wed, 8 Jan 2025 14:43:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347406; cv=none; b=LD+y9CIs5KoPLARyQdDF+6cJQPszbPWGTX7A5k8kW28RUMJjqE6hCgmJYO+8pOjYjqw6Xie51MSpEgzEonyF4FGqTTzoYdhajE/J/wVF+y9RmEcaw8d2JdSOCgyeoaeXKqedyziS9joksQVjxklQ25i5s/pNv23nF3TBzXIqFpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347406; c=relaxed/simple; bh=4zIiyRBJx2uUEgy/m5M23r7WgU1QXI3Eb0MeZznc3Pk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HExL7hnaCcMw4t1NOX+e1AmWU4BhD0rYYsghA06lnxz5TdgfbSnybwj80bCJbM/ncW4J/bxPBNh0mXB/f3uUDzn+w0S4zlyu+yHLM4IPWqro7oxqlmiJ1TtrRQ246UFIaxfc1JIqeX8SPD5LShoBEitfwPbAsJAmmQnf/Kp1BNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=oJlPKtHl; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="oJlPKtHl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736347405; x=1767883405; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4zIiyRBJx2uUEgy/m5M23r7WgU1QXI3Eb0MeZznc3Pk=; b=oJlPKtHlezAYLIhTxVtL9l+5gVCg6c+aB5jtmZF0ZgjChezuC3qZYrnI BgvgDmAY8L2QKborDFMkwVxIi/x2He1zlSEzRDRXtoy31z5NbKmjh76mI mgqmsA4hJF/cvWzUR+GBxbe77TjeuONZSngZThSjBmWnsh2SJX293LcVA Cr8kusdUVZ1+Gy4upGgGg9BKzwlGVxvxOw+kZ007mHygXtoZcyZhXW64C OI3XGxb6UVzqoEMm5aPwfDe8iLz+Gr8rjjeGvcVOQx67HjzmbVh41jVum sGbpsPlT/zbNcBwDRuDItBQ+qP9pYascfhi++z4HiDXsqqTdy9SY6xe5q A==; X-CSE-ConnectionGUID: bwwXw/pDQHSUAsdECaeqjA== X-CSE-MsgGUID: 3tfoVB1MS26WsLlGhodqIQ== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="36737379" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="36737379" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 06:43:25 -0800 X-CSE-ConnectionGUID: wY1PHkZiSZCcy+MYM3rw5g== X-CSE-MsgGUID: pZlpAOiwTwKyvRgLs/Qpcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103969397" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa008.jf.intel.com with ESMTP; 08 Jan 2025 06:43:21 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v7 3/5] i386/cpu: Update cache topology with machine's configuration Date: Wed, 8 Jan 2025 23:01:48 +0800 Message-Id: <20250108150150.1258529-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108150150.1258529-1-zhao1.liu@intel.com> References: <20250108150150.1258529-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User will configure smp cache topology via -machine smp-cache. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v3: * Updated MachineState.smp_cache to consume "default" level and did a check to ensure topological hierarchical relationships are correct. --- target/i386/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4728373fdf03..b6d6c4b96d49 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7758,6 +7758,64 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] = 0; } +#ifndef CONFIG_USER_ONLY +static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, + Error **errp) +{ + CPUX86State *env = &cpu->env; + CpuTopologyLevel level; + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level = level; + env->cache_info_amd.l1d_cache->share_level = level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_cpuid4.l1d_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_amd.l1d_cache->share_level); + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level = level; + env->cache_info_amd.l1i_cache->share_level = level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_cpuid4.l1i_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_amd.l1i_cache->share_level); + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level = level; + env->cache_info_amd.l2_cache->share_level = level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_cpuid4.l2_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_amd.l2_cache->share_level); + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level = level; + env->cache_info_amd.l3_cache->share_level = level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_cpuid4.l3_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_amd.l3_cache->share_level); + } + + if (!machine_check_smp_cache(ms, errp)) { + return false; + } + return true; +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -7982,6 +8040,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + /* + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates + * if user didn't set smp_cache. + */ + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 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d="scan'208";a="103969403" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa008.jf.intel.com with ESMTP; 08 Jan 2025 06:43:25 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v7 4/5] i386/pc: Support cache topology in -machine for PC machine Date: Wed, 8 Jan 2025 23:01:49 +0800 Message-Id: <20250108150150.1258529-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108150150.1258529-1-zhao1.liu@intel.com> References: <20250108150150.1258529-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v6: * Deleted the "thread" level from the allowed topology level parameters in the doc. Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 30 +++++++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 53a2f226d038..b9b83d1936ae 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1797,6 +1797,10 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->smp_props.modules_supported = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; mc->default_ram_id = "pc.ram"; pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; diff --git a/qemu-options.hx b/qemu-options.hx index cc694d3b890c..60894fe2b52b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=@var{} memory encryption object to use (default=none)\n" " hmat=on|off controls ACPI HMAT support (default=off)\n" " memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n" - " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n", + " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n" + " smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=]name[,prop=value[,...]]`` @@ -159,6 +160,33 @@ SRST :: -machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512 + + ``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel`` + Define cache properties for SMP system. + + ``cache=cachename`` specifies the cache that the properties will be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=topologylevel`` sets the cache topology level. It accepts + CPU topology levels including ``core``, ``module``, ``cluster``, ``die``, + ``socket``, ``book``, ``drawer`` and a special value ``default``. If + ``default`` is set, then the cache topology will follow the architecture's + default cache topology model. If another topology level is set, the cache + will be shared at corresponding CPU topology level. For example, + ``topology=core`` makes the cache shared by all threads within a core. + The omitting cache will default to using the ``default`` level. + + The default cache topology model for an i386 PC machine is as follows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core ERST DEF("M", HAS_ARG, QEMU_OPTION_M, From patchwork Wed Jan 8 15:01:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13931115 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A551FECC1 for ; Wed, 8 Jan 2025 14:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347414; cv=none; b=LA/ZUiPble1nf6CrDriVOBmYJqNxJ19o1pYD7L474l/N2kYydwX4X0EzmlsiTaDfspnjz2ORwJLYij5hXle2Zv9SX4vGKEu4iK8PMmXJJ6tl66VyyMdJJVkBX4XY9TqEk8bQf8tQ95OwJVTWw02mrdSdaru8j+mI+OznAn9yK/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736347414; c=relaxed/simple; bh=o68AVswZC8MMXvOqV0CQg1sP/nxOf+4m/m/wx22k+98=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UeP/SmM8MRNfCc0e64J4dUehgOTe91Rlraeh92S7YvaphjF307w/kRKXiFwVjju2BDK4qz+xmVfKZ8CUebH2xN95sdnll1UMb0O4CUgCFN2QwYFDLmEr3Q1AZjXI3/YFbqGjMnzd595qBvweq76xs2f2K4LmFGm+uZBF5uV6rNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nRgATMrx; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nRgATMrx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736347413; x=1767883413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o68AVswZC8MMXvOqV0CQg1sP/nxOf+4m/m/wx22k+98=; b=nRgATMrxsna2XJ2Z+t7VATrQdlfFE0liirdQ3h8k4/ZpKr+Frxp8mYxa AYpqtWVz+39QEIApKaMu8nDodHmPTmRrbR9Vn4zYjC373VGYcxz0a4uie prmXaMLuas7zHTU9HeoRy7mQ5UsNCWaRih7cYqz5nfBAA64jxzEnqDNIU MI3Pz7eGrbaH5Ftz3Gm3OgibWQ4ynnN8zCWuGjRlO9C6jlfVTi8mVRPSp 1Nc1Y+xblJOToOW6O2SFvMVSFDnddgWu7wgYonn2efwzDkDeIlCaClsJl JL1jbqQe+xbmRff08t/CQlx+POf4kwtQxZWmhF0XtUEnjtoPFWEtQFHvJ A==; X-CSE-ConnectionGUID: m9I1ZzKITo+VNJ0Zh7pVdA== X-CSE-MsgGUID: PoDcTemWR8eoKq2viibkqQ== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="36737411" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="36737411" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 06:43:33 -0800 X-CSE-ConnectionGUID: A1Fh/xaFStmV8MFQjqItgA== X-CSE-MsgGUID: UeLOM+hbSY6U9SaaFq4sLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="103969407" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa008.jf.intel.com with ESMTP; 08 Jan 2025 06:43:29 -0800 From: Zhao Liu To: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH v7 5/5] i386/cpu: add has_caches flag to check smp_cache configuration Date: Wed, 8 Jan 2025 23:01:50 +0800 Message-Id: <20250108150150.1258529-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108150150.1258529-1-zhao1.liu@intel.com> References: <20250108150150.1258529-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPCompatProps with a new name "has_caches". This way, it remains consistent with the function and style of "has_clusters" in SMPCompatProps. * Dropped my previous TODO with the new flag. --- Changes since Patch v2: * Picked a new patch frome Alireza's ARM smp-cache series. --- hw/core/machine-smp.c | 2 ++ include/hw/boards.h | 3 +++ target/i386/cpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 4e020c358b66..0be0ac044c22 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -332,6 +332,8 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } } + + mc->smp_props.has_caches = true; return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index 2ad711e56dbe..97125b027070 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -156,6 +156,8 @@ typedef struct { * @modules_supported - whether modules are supported by the machine * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are * supported by the machine + * @has_caches - whether cache properties are explicitly specified in the + * user provided smp-cache configuration */ typedef struct { bool prefer_sockets; @@ -166,6 +168,7 @@ typedef struct { bool drawers_supported; bool modules_supported; bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; + bool has_caches; } SMPCompatProps; /** diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b6d6c4b96d49..7bc619236680 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8040,13 +8040,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + MachineClass *mc = MACHINE_GET_CLASS(ms); - /* - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates - * if user didn't set smp_cache. - */ - if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { - return; + if (mc->smp_props.has_caches) { + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } } qemu_register_reset(x86_cpu_machine_reset_cb, cpu);