From patchwork Wed Jan 8 22:42:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13931675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A30EAE77199 for ; Wed, 8 Jan 2025 22:43:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27E4010E964; Wed, 8 Jan 2025 22:43:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.b="L0WKhrNv"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93A4810E964; Wed, 8 Jan 2025 22:43:12 +0000 (UTC) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 508CLcAH028217; Wed, 8 Jan 2025 22:43:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= i+MiiTp0B/IBQUsDOuxU3B2/w2xDLeHcYE/rPPtfMd4=; b=L0WKhrNv4i6irjf6 bj6n8Osa5fiIQDa+dm/Rt0ALsdjqhvZuF2BOclLIHWf8otvvG0bgOX3rPZ/lBBvV V8UNvXb7P4+K6Z30aU5E5F/f+3RdtsG515M68JDeTBk6egMoAsI0veO8B5GKD9ud sxuYMdYOvqTb2RdudBCnHa4VHlpcFkzUfH9w+6TSb1sgW72hrQ/KWBC6ixCzXpfl J2lTFY/ztv9zos13xBSFoIjMYZAxK8LDc9VCeCT+BUfApQ1cUdRJOr8MVY9UfPlc pTR03XtEdJC80fiQSV3V6wpAvPxqKnNluf7GN5rjv97y2Q3r0ssdvOcVTXa759rQ IEtF/Q== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 441sa29daf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Jan 2025 22:43:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 508Mh578014421 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Jan 2025 22:43:05 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 14:43:00 -0800 From: Akhil P Oommen Date: Thu, 9 Jan 2025 04:12:38 +0530 Subject: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85 MIME-Version: 1.0 Message-ID: <20250109-x1e-speedbin-b4-v1-1-009e812b7f2a@quicinc.com> References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> In-Reply-To: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla CC: , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736376174; l=1972; i=quic_akhilpo@quicinc.com; s=20240726; h=from:subject:message-id; bh=yntijMR5igf8+SRnFWzw0pLwjuicULmhUrZvX1BBQ/E=; b=HGzU4wvF/VvJlzEq3P0hvKND+fDdczwCryAAzQiP+qmO581Xo3hs+5tlT/h7MAK7yXRrXrGA6 dbUsSgLD31nArOfnC/bKvhp68wvPZCDB5HpiLV8oE9DxIX1onOtv8j2 X-Developer-Key: i=quic_akhilpo@quicinc.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: quCIZFjrmV5xQmaPWEL7mBz-bFCWiPqK X-Proofpoint-ORIG-GUID: quCIZFjrmV5xQmaPWEL7mBz-bFCWiPqK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 adultscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501080186 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Adreno X1-85 has an additional bit which is at a non-contiguous location in qfprom. Add support for this new "hi" bit along with the speedbin mappings. --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { .gmu_cgc_mode = 0x00020202, }, .address_space_size = SZ_256G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 263, 1 }, + { 315, 0 }, + ), .preempt_record_size = 4192 * SZ_1K, }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) int adreno_read_speedbin(struct device *dev, u32 *speedbin) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 hi_bits = 0; + int ret; + + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + if (ret) + return ret; + + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); + if (ret != -ENOENT) + return ret; + + *speedbin |= (hi_bits << 8); + return 0; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, From patchwork Wed Jan 8 22:42:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13931676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9BCFE77199 for ; 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Wed, 08 Jan 2025 22:43:11 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 508MhAYh031469 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Jan 2025 22:43:10 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 14:43:05 -0800 From: Akhil P Oommen Date: Thu, 9 Jan 2025 04:12:39 +0530 Subject: [PATCH RFC 2/4] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner MIME-Version: 1.0 Message-ID: <20250109-x1e-speedbin-b4-v1-2-009e812b7f2a@quicinc.com> References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> In-Reply-To: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla CC: , , , , , Akhil P Oommen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Akhil P Oommen --- include/dt-bindings/power/qcom-rpmpd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index df599bf462207267a412eac8e01634189a696a59..5bc4735fb3e6e06ec62a352e2d40503b01084fd8 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -240,6 +240,7 @@ #define RPMH_REGULATOR_LEVEL_TURBO_L2 432 #define RPMH_REGULATOR_LEVEL_TURBO_L3 448 #define RPMH_REGULATOR_LEVEL_TURBO_L4 452 +#define RPMH_REGULATOR_LEVEL_TURBO_L5 456 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 From patchwork Wed Jan 8 22:42:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13931677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3785AE77199 for ; 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Wed, 08 Jan 2025 22:43:17 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 508MhFqR020870 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Jan 2025 22:43:15 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 14:43:10 -0800 From: Akhil P Oommen Date: Thu, 9 Jan 2025 04:12:40 +0530 Subject: [PATCH RFC 3/4] dt-bindings: nvmem: qfprom: Add X1E80100 compatible MIME-Version: 1.0 Message-ID: <20250109-x1e-speedbin-b4-v1-3-009e812b7f2a@quicinc.com> References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> In-Reply-To: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla CC: , , , , , Akhil P Oommen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Akhil P Oommen --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 9755b31946bf9d4c1055a993145d06c274b61a37..25f07f93345af83015b2c2917993e460cfd6799e 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -47,6 +47,7 @@ properties: - qcom,sm8450-qfprom - qcom,sm8550-qfprom - qcom,sm8650-qfprom + - qcom,x1e80100-qfprom - const: qcom,qfprom reg: From patchwork Wed Jan 8 22:42:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13931678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6855E77199 for ; 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Wed, 08 Jan 2025 22:43:22 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 508MhLGc020970 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Jan 2025 22:43:21 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 14:43:16 -0800 From: Akhil P Oommen Date: Thu, 9 Jan 2025 04:12:41 +0530 Subject: [PATCH RFC 4/4] arm64: dts: qcom: x1e80100: Update GPU OPP table MIME-Version: 1.0 Message-ID: <20250109-x1e-speedbin-b4-v1-4-009e812b7f2a@quicinc.com> References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> In-Reply-To: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla CC: , , , , , Akhil P Oommen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 444723ab4f11d15cb7c0f9829ec8123b76e4ebeb..0a4f179ef2eb2de11485580d797457f823f3c528 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3325,6 +3325,9 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>, <&gpu_speed_bin_hi>; + nvmem-cell-names = "speed_bin", "speed_bin_hi"; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -3337,11 +3340,28 @@ zap-shader { gpu_opp_table: opp-table { compatible = "operating-points-v2-adreno", "operating-points-v2"; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x01>; + }; + + opp-1375000000 { + opp-hz = /bits/ 64 <1375000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x01>; + }; + opp-1250000000 { opp-hz = /bits/ 64 <1250000000>; opp-level = ; opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; }; opp-1175000000 { @@ -3349,6 +3369,7 @@ opp-1175000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; }; opp-1100000000 { @@ -3356,6 +3377,7 @@ opp-1100000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; }; opp-1000000000 { @@ -3363,6 +3385,7 @@ opp-1000000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82b5ffd>; + opp-supported-hw = <0x03>; }; opp-925000000 { @@ -3370,6 +3393,7 @@ opp-925000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82b5ffd>; + opp-supported-hw = <0x03>; }; opp-800000000 { @@ -3377,6 +3401,7 @@ opp-800000000 { opp-level = ; opp-peak-kBps = <12449219>; qcom,opp-acd-level = <0xa82c5ffd>; + opp-supported-hw = <0x03>; }; opp-744000000 { @@ -3384,6 +3409,7 @@ opp-744000000 { opp-level = ; opp-peak-kBps = <10687500>; qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x03>; }; opp-687000000 { @@ -3391,6 +3417,7 @@ opp-687000000 { opp-level = ; opp-peak-kBps = <8171875>; qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x03>; }; opp-550000000 { @@ -3398,6 +3425,7 @@ opp-550000000 { opp-level = ; opp-peak-kBps = <6074219>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0x03>; }; opp-390000000 { @@ -3405,6 +3433,7 @@ opp-390000000 { opp-level = ; opp-peak-kBps = <3000000>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0x03>; }; opp-300000000 { @@ -3412,6 +3441,7 @@ opp-300000000 { opp-level = ; opp-peak-kBps = <2136719>; qcom,opp-acd-level = <0xc02b5ffd>; + opp-supported-hw = <0x03>; }; }; }; @@ -5992,6 +6022,23 @@ frame@1780d000 { }; }; + efuse@221c8000 { + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@119 { + reg = <0x119 0x2>; + bits = <7 8>; + }; + + gpu_speed_bin_hi: gpu_speed_bin_hi@11b { + reg = <0x11b 0x1>; + bits = <7 1>; + }; + }; + pmu@24091000 { compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>;