From patchwork Thu Jan 9 09:06:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13932216 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48574204089 for ; Thu, 9 Jan 2025 09:07:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413633; cv=none; b=cwU4cNmw2+5kVEfiYzAf4RDDv9a/obuwhsuev//2l2Eo3TRlfrZwrRAI6OIwwtCMQlr3cK6b1IS9foIqGwAAwwTVLuISbgZVDfr9hR4IRfvircpEci2tDd6j1EfnIuJ4mADhvD231pDS7Ybk5s3tVP3ADHlJcwcbwp6J7uV0Vw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413633; c=relaxed/simple; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m/4pT7GZPE5ZppR6yD+uE255txjIeU/l4FLDmEWF+BVDCfMhdfFWqFSle2quupoCisLCPQVRCkdFal7lLuYAXt34hrPSBzRI99hkgamn+WNlbACnABosbmb9zfgQZq4D10sixTn1L3G3eFmRtHS9ZC7PQlfKaRxwjgFL33oX7Zs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GmvQ8RTu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GmvQ8RTu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 35F08C4CED2; Thu, 9 Jan 2025 09:07:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736413632; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GmvQ8RTuwYo9O7BH14/xi+qUJ+oydkzX4DHh9cBYeCTrgTvjQKAue4rC1oh3ZxEPF pftqBA0/ydmu7hkhqlABl6DHFBjgxoXZ+Hk+2T/apydUCruVgIM2H6kinCHxaePqSq 9HjYmvKmMMzmpI62gGg/++Pi3TmGmbI+D8Jw8trZdyKAHt5DoNDVaFs2eLnSlUn/JU I7K2x+k0sn4f5Hj8EYjO1RmplUpT+HuUS+VK/vOKEIr7TS70qNSto/Aiwk97ba1ZtJ Mtzx5whiY9t8SH4XBWVJ849LHicYVqS8ynPX/z6j++4y4777SikKph+pmZFYg55Xnh Ov6OZ6j3Dt8LQ== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 1/6] PCI: endpoint: Add BAR type BAR_RESIZABLE Date: Thu, 9 Jan 2025 10:06:53 +0100 Message-ID: <20250109090652.110905-9-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250109090652.110905-8-cassel@kernel.org> References: <20250109090652.110905-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3008; i=cassel@kernel.org; h=from:subject; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLrJ27cMifhZ7BqcrzDIr130y5+K3f0mdtyuuuo9qPZa 81eVDVO6ShlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEVrxi+MW09t6Xp7mPnzEc ncq4e78p35KvO2xNVy8vLFt0L+uym81lhn9WifdPb0/Oy+kRCplmmV0c/351CnNaf6KZ2Nq6hS1 PPnMCAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A resizable BAR is different from a normal BAR in a few ways: -The minimum size of a resizable BAR is 1 MB. -Each BAR that is resizable has a Capability and Control register in the Resizable BAR Capability structure. These registers contain the supported sizes and the currently selected size of a resizable BAR. The supported sizes is a bitmap of the supported sizes. The selected size is a single value that is equal to one of the supported sizes. A resizable BAR thus has to be configured differently than a BAR_PROGRAMMABLE BAR, which usually sets the BAR size/mask in a vendor specific way. The PCI endpoint framework currently does not support resizable BARs. Add a BAR type BAR_RESIZABLE, so that an EPC driver can support resizable BARs properly. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, an EPC driver will be able to support resizable BARs (we intentionally only support a single supported resizable BAR size). Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epf-core.c | 4 ++++ include/linux/pci-epc.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 50bc2892a36c..394395c7f8de 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -274,6 +274,10 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, if (size < 128) size = 128; + /* According to PCIe base spec, min size for a resizable BAR is 1 MB. */ + if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M) + size = SZ_1M; + if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) { if (size > bar_fixed_size) { dev_err(&epf->dev, diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index e818e3fdcded..e9d5ed23914f 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -188,11 +188,14 @@ struct pci_epc { * enum pci_epc_bar_type - configurability of endpoint BAR * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC. * @BAR_FIXED: The BAR mask is fixed by the hardware. + * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability. + * An EPC driver can currently only set a single supported size. * @BAR_RESERVED: The BAR should not be touched by an EPF driver. */ enum pci_epc_bar_type { BAR_PROGRAMMABLE = 0, BAR_FIXED, + BAR_RESIZABLE, BAR_RESERVED, }; From patchwork Thu Jan 9 09:06:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13932217 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEBC221518F for ; Thu, 9 Jan 2025 09:07:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413636; cv=none; b=QmZqAqpIl+v34laCyURheW9D38wPHLEfRLRWRbIlNDGvyLHh9l2+zTjpbYk6lIwDoRPKhPB2DzSsnL999OpRyoRRN4ql4JaT7tzdvBGXf3cbIkQb8AgRAnas+J/P59f0At3/Ws0B9N6i9nnOomClTMkK4XsTPT/2G9Ypt1gVoQg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413636; c=relaxed/simple; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JDA24WWmFQSA8n9Awt3ZErBalKlz/zkN4D31pX4GBPLkjI3FxFgYHmrjxccsK4+6MTKTTC7HtQYhcUkHkbht8sO1m2l0gHK2FlNWneqzbQen3eSV8DFy0UV5IkD7n6SCNJPy/my/iVnV8E+umEyZiVx+3Y9ZOcw7ubVSMJAVlAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WtutVlZy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WtutVlZy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 829C2C4AF09; Thu, 9 Jan 2025 09:07:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736413635; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WtutVlZyRIACTOtnvwlvjvrTHx5y8mnjHkFwWplImlUcKof5nJbBtKpi97qbZ4XyU hZszVFUh07Pu5JQZQprk0uhrUQmz5+j/60BQkySIR6y8XGzFqeA6tFnI4+7GfBgoiU pAE5fGWiTbPRJ3v8QzaSjCgNXhW4zOoYviQeHth1HiXiAnXA/Zq2nDqeS8Bc7N32FH pof8KKAWMqaGZ0m6K44q8gBo3BxItA085OexnxgrSNiVrTzt0tB5OCuA1d35c5t46L jQEiN6F0gUS8JykpfHwLOrNvyRupKPWJXn0iZ/T3MTI0vF3V25p5FHHB1JBickrHcS KLF5YVPka6ldg== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 2/6] PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability() Date: Thu, 9 Jan 2025 10:06:54 +0100 Message-ID: <20250109090652.110905-10-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250109090652.110905-8-cassel@kernel.org> References: <20250109090652.110905-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1884; i=cassel@kernel.org; h=from:subject; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLrJ24UWm/5cImE5d8lL+fNrG8OiTj6dprc8tZNNh+vS LKcYNIq6ShlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBE9EoYGQ7Oy9jYz8Tqe3f3 co6bAQlWrS5T7/BcOiZVx+kukyDzt4qRYXN0eXmk+VxXp7s9qwXuzJ0TrPTn7YXIutsXVHIj0xO msQIA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Move dw_pcie_ep_find_ext_capability() so that it is located next to dw_pcie_ep_find_capability(). Additionally, a follow-up commit requires this to be defined earlier in order to avoid a forward declaration. Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8e07d432e74f..6b494781da42 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -102,6 +102,24 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap) return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_header *hdr) { @@ -690,24 +708,6 @@ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); -static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) -{ - u32 header; - int pos = PCI_CFG_SPACE_SIZE; - - while (pos) { - header = dw_pcie_readl_dbi(pci, pos); - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (!pos) - break; - } - - return 0; -} - static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { unsigned int offset; From patchwork Thu Jan 9 09:06:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13932218 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A481A215768 for ; Thu, 9 Jan 2025 09:07:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413639; cv=none; b=gnnXsREAzSDk3iZHt81wWxqXsKvHZV/xSw0cmUbq8BaF8V7KsMeIK/JdipBEwJ+lMYFDwlDLH38nrR9LOQfi9ARJmL6oIJbe4N7WKxDG7IumiMNdIxEe94+ewqIIeZTfK5B/w3+dQEVo1qia83MTht1GpA9xcydgMJ1jczeAW1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413639; c=relaxed/simple; bh=WBoKAd8mzv5KeyyvPTgG9tmLqlfUPnd6fxvriJg9AUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p7pCe4BVnJoBuf5pEqPrYpEn+PySp77eXtbmRARJMGkdbHXt5k/7BxV2VRD92Mvfc3gDI/iKm69hfrCaN2e+TYCyBXf63AHlO3HvsG/U0xZ6O2XJn3J5sohZ9Gu90/IyIm4r8VtTttHfdr61V2XixkDjZNAoA4q3JZTp8FdgvgQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IIqDjRaw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IIqDjRaw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4509CC4CEED; Thu, 9 Jan 2025 09:07:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736413638; bh=WBoKAd8mzv5KeyyvPTgG9tmLqlfUPnd6fxvriJg9AUA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IIqDjRawLF0NsGJZOjzx6cDRynZeACnuWvbhqraqfn9/ECv5KreVAdAoRdgsJkI8y lH34cuY45iwHi2OfQKzRBXznwAhgHqPMTVEpoRB2GON8nuLH8DbGfyma3rE25TGdG2 7BhyqaxtKagN5uita4SS/8EBse2ZmWfEKYxIlAhBRwF6AX1Sea8t6Yed4H3K6+jws+ uEyn4zqPYSC5fl7R/ZN26awG9lq4xaJycnlW/UxRgFN0SmnP1udK2NoQtv55BDt7vW s9yTWI6Oj438qOsGi71hSn68okaIq74XVja41GK5DRmnVPoXRQNdCVA6L2g+pRqTT5 g7j7Q1OEEtP2Q== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 3/6] PCI: dwc: endpoint: Add support for BAR type BAR_RESIZABLE Date: Thu, 9 Jan 2025 10:06:55 +0100 Message-ID: <20250109090652.110905-11-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250109090652.110905-8-cassel@kernel.org> References: <20250109090652.110905-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9701; i=cassel@kernel.org; h=from:subject; bh=WBoKAd8mzv5KeyyvPTgG9tmLqlfUPnd6fxvriJg9AUA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLrJ27kNrXV2C/tcm95ueC2a4s2LFuqadf/zevlr2ll3 a5XnvNN6yhlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBENk9hZFippdc5/cGBKnub 8GsdfJGrz6b6H9r7dZPg7MWuPVeETXMZ/hmxLbwUb+T59vfGBfxfezdmr/60dfWkz0vEnp84fy7 plzwrAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC databook specifies three different BARn_SIZING_SCHEME_N - Fixed Mask (0) - Programmable Mask (1) - Resizable BAR (2) Each of these sizing schemes have different instructions for how to initialize the BAR. The DWC driver currently does not support resizable BARs. Instead, in order to somewhat support resizable BARs, the DWC EP driver currently has an ugly hack that force sets a resizable BAR to 1 MB, if such a BAR is detected. Additionally, this hack only works if the DWC glue driver also has lied in their EPC features, and claimed that the resizable BAR is a 1 MB fixed size BAR. This is unintuitive (as you somehow need to know that you need to lie in your EPC features), but other than that it is overly restrictive, since a resizable BAR is capable of supporting sizes different than 1 MB. Add proper support for resizable BARs in the DWC EP driver. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, the DWC EP driver will be able to support resizable BARs (we intentionally only support a single supported resizable BAR size). This means that an EPC driver does not need to lie in EPC features, and an EPF driver will be able to set an arbitrary size (not be forced to a 1 MB size), just like BAR_PROGRAMMABLE. Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 192 ++++++++++++++++-- 1 file changed, 177 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 6b494781da42..ad521d908627 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -223,6 +223,138 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, ep->bar_to_atu[bar] = 0; } +static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, + enum pci_barno bar) +{ + u32 reg, bar_index; + unsigned int offset, nbars; + int i; + + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (!offset) + return offset; + + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + bar_index = reg & PCI_REBAR_CTRL_BAR_IDX; + if (bar_index == bar) + return offset; + } + + return 0; +} + +static u32 dw_pcie_ep_bar_size_to_rebar_cap(size_t size) +{ + u32 val; + + /* + * According to PCIe base spec, min size for a resizable BAR is 1 MB, + * thus disallow a requested BAR size smaller than 1 MB. + * Disallow a requested BAR size larger than 128 TB. + */ + if (size < SZ_1M || (u64)size > (SZ_128G * 1024)) + return 0; + + val = ilog2(size); + val -= 20; + + /* Sizes in REBAR_CAP start at BIT(4). */ + return BIT(val + 4); +} + +static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + unsigned int rebar_offset; + u32 rebar_cap, rebar_ctrl; + + rebar_offset = dw_pcie_ep_get_rebar_offset(pci, bar); + if (!rebar_offset) + return -EINVAL; + + rebar_cap = dw_pcie_ep_bar_size_to_rebar_cap(size); + if (!rebar_cap) + return -EINVAL; + + dw_pcie_dbi_ro_wr_en(pci); + + /* + * You should not write a BAR mask for a resizable BAR. The BAR mask + * is automatically derived by the controller every time the "selected + * size" bits are updated, see "Figure 3-26 Resizable BAR Example for + * 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write + * BIT(0) to set the BAR enable bit. + */ + dw_pcie_ep_writel_dbi2(ep, func_no, reg, BIT(0)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + /* + * Bits 31:0 in PCI_REBAR_CAP define "supported sizes" bits for sizes + * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" + * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. + */ + rebar_ctrl = dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); + rebar_ctrl &= ~GENMASK(31, 16); + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + + /* + * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically + * updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR + * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a. + */ + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap); + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static int dw_pcie_ep_set_bar_programmable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + + dw_pcie_dbi_ro_wr_en(pci); + + dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(struct dw_pcie_ep *ep, + enum pci_barno bar) +{ + const struct pci_epc_features *epc_features = ep->ops->get_features(ep); + + return epc_features->bar[bar].type; +} + static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { @@ -230,9 +362,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar = epf_bar->barno; size_t size = epf_bar->size; + enum pci_epc_bar_type bar_type; int flags = epf_bar->flags; int ret, type; - u32 reg; /* * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs @@ -264,19 +396,30 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, goto config_atu; } - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - dw_pcie_dbi_ro_wr_en(pci); - - dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); - - if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { - dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + bar_type = dw_pcie_ep_get_bar_type(ep, bar); + switch (bar_type) { + case BAR_FIXED: + /* + * There is no need to write a BAR mask for a fixed BAR (except + * to write 1 to the LSB of the BAR mask register, to enable the + * BAR). Write the BAR mask regardless. (The fixed bits in the + * BAR mask register will be read-only anyway.) + */ + fallthrough; + case BAR_PROGRAMMABLE: + ret = dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar); + break; + case BAR_RESIZABLE: + ret = dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar); + break; + default: + ret = -EINVAL; + dev_err(pci->dev, "Invalid BAR type\n"); + break; } - dw_pcie_dbi_ro_wr_dis(pci); + if (ret) + return ret; config_atu: if (!(flags & PCI_BASE_ADDRESS_SPACE)) @@ -710,9 +853,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { + struct dw_pcie_ep *ep = &pci->ep; unsigned int offset; unsigned int nbars; - u32 reg, i; + u32 reg, i, val; offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); @@ -727,9 +871,27 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) * PCIe r6.0, sec 7.8.6.2 require us to support at least one * size in the range from 1 MB to 512 GB. Advertise support * for 1 MB BAR size only. + * + * For a BAR that has been configured via dw_pcie_ep_set_bar(), + * advertise support for only that size instead. */ - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4)); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + /* + * While the RESBAR_CAP_REG_* fields are sticky, the + * RESBAR_CTRL_REG_BAR_SIZE field is non-sticky (it is + * sticky in certain versions of DWC PCIe, but not all). + * + * RESBAR_CTRL_REG_BAR_SIZE is updated automatically by + * the controller when RESBAR_CAP_REG is written, which + * is why RESBAR_CAP_REG is written here. + */ + if (ep->epf_bar[i]) + val = dw_pcie_ep_bar_size_to_rebar_cap(ep->epf_bar[i]->size); + else + val = BIT(4); + + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val); + } } dw_pcie_setup(pci); From patchwork Thu Jan 9 09:06:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13932219 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32453215172 for ; Thu, 9 Jan 2025 09:07:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413641; cv=none; b=shgkXVbQUPecWH3SSmslhaJruNDa3JzmICPT++r2QVY0sFYGrEOA+RDW6SD8xTWVF6qIemu0S8LEBFO4LKJSAhJd5oJHReIXkXhDNl1cHNXljZ5WOB9YMvECd8yKdTFTAWnaYT5ubCDsqkPq2mKMBGxxj/xjSc+1S6qXa1sLQAw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413641; c=relaxed/simple; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cJVAM9bngGp90uOmfHj8+chty/L8cY2x8xg8lZ1bJeg7pP5ba1P4IQ0X3KW225qdIdESpg0o8mcbP1m9IJ4AwFDX/GkcqvcIRTedtb7WNw4Md8HOd/fcidYAftAUbz4MHqsnFbHcaahZAq65ty0xsNjmKMuWzTIV63spsH+NOJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p+CYZ2Hp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p+CYZ2Hp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8243C4CED2; Thu, 9 Jan 2025 09:07:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736413640; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p+CYZ2HpzwuL9iuRFV+jVselwwSqzqWw9d7hi9EKARqvc44d0pkTtm77lfVrNsYdH SpsFX+5LRVGY/f1AVqj7umhg/+wr02txG7TddALCd+CSsvKDcuA2L1LaGQGaZ1tHWz 031K/bxdxPdQ7pDjtgBS6prtoL6jS1wC6KNGCy1EkSFWlfmmwKrG3mOL9T/kmkpKtw Rgk/ZkvHKoZic8LeH1uo7UF61Jl7/KWtEq9jIRNk0LmK3zfpTz8qWpiXCJd18Bf+A7 Cg7DgvE5wxhvK/YZDCfy+X1B5zEDdqfiC1Fz+KKkcAUpUlBl2X6241/hlmajp2tyYF RmnnHr0WW0oBA== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 4/6] PCI: keystone: Describe resizable BARs as resizable BARs Date: Thu, 9 Jan 2025 10:06:56 +0100 Message-ID: <20250109090652.110905-12-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250109090652.110905-8-cassel@kernel.org> References: <20250109090652.110905-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1286; i=cassel@kernel.org; h=from:subject; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLrJ2568+TkMpljEbNvz44466Vl/KLw8oqb9oK3JPxPH tS9Yqh3oaOUhUGMi0FWTJHF94fL/uJu9ynHFe/YwMxhZQIZwsDFKQATSWhnZJiymunz309/nOUc WTh2a8y66DFp4pbqaxJ2H3mvvmF48VWVkWGS2cllgUuUVkxetfKCkP+qk2tCu+S0ltRyaui1Tp1 iXMkEAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "12.2.2.4.15 PCIe Subsystem BAR Configuration" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf We can see that BAR2 and BAR5 are not Fixed BARs, but actually Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 63bd5003da45..fdc610ec7e5e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -966,10 +966,10 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .msix_capable = true, .bar[BAR_0] = { .type = BAR_RESERVED, }, .bar[BAR_1] = { .type = BAR_RESERVED, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, .align = SZ_1M, }; From patchwork Thu Jan 9 09:06:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13932220 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BCBC204089 for ; Thu, 9 Jan 2025 09:07:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413643; cv=none; b=srzKT7E90+egKhx5FyFGjpio42Nd7GTv9hn5+CtYCzLkTt5zMlexF3ff8dAJWgWC4I9cr0aZOZFoMy1QcDoRr+NC591o4w/n62tGniK2Hhl3xHMLJOYoTKcheqPUKV7Vw6e+3KknbVx4N9sA2YVmoCmXFIMUd8QFOrmwRRZaPtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413643; c=relaxed/simple; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DgwosGci/XkmbCD8T33kH12QAHZXoAuEbszS7o4vKIfH9wXEhv/saEI6pKmeMFowNWFJovNB9YMZ3wEIp9KMXFOiIt1MKygyPvTzUp7DXJMemVTro6K8QRNlg0jyBys2SqrzLe7dkAHG20G89JqA6/G7m5gy9jvyoxFTwlYZ024= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TSjPlr8H; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TSjPlr8H" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67B60C4CED2; Thu, 9 Jan 2025 09:07:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736413643; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TSjPlr8HkUsMiIkLjMpY1K8jgvNRKvQg55njPzFFYp+TvpM34uk/uxT2tK+9KojFP MdBMHXqweaTcRUzwzjsFr30q1r1kP36tKsNQ/lgBjDQpSxndJDUedKaM+szLXFySj8 m19JQk/LqAY3oz/zc8XbgOQKRW6hXUo8YO7i/mwY7HtDfjy7oBtwjdvXSttlFZP/BC G42JVo01mx1Iis4rFjyMEXnZ/hM05TvZctS3+fBlubBiSfTJZ6yClUqn2/LTHHBl6e CabSr0HG4Lyk5lKqJEI+KBunYpD4ZFc3IvLwnZvqlfWOYhh8bEVwQq1pwb5zEQI3uO AcSTAFcKEn/Pg== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 5/6] PCI: keystone: Specify correct alignment requirement Date: Thu, 9 Jan 2025 10:06:57 +0100 Message-ID: <20250109090652.110905-13-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250109090652.110905-8-cassel@kernel.org> References: <20250109090652.110905-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1604; i=cassel@kernel.org; h=from:subject; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLrJ26SXXq6dQdPg06id9yM3e1LV8r1X+fOlarRtb+e9 PlgzFKLjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEwk4REjw+yTXy0sDxTOXbGm 7rzAsnShSbsM75sIHuqP3Lqc//etMAZGhs7j93v+//nzRkFI6lCq9/tDh7ZcW6Or8erJfyEDvtl GgfwA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The support for a specific iATU alignment was added in commit 2a9a801620ef ("PCI: endpoint: Add support to specify alignment for buffers allocated to BARs"). This commit specifically mentions both that the alignment by each DWC based EP driver should match CX_ATU_MIN_REGION_SIZE, and that AM65x specifically has a 64 KB alignment. This also matches the CX_ATU_MIN_REGION_SIZE value specified by "12.2.2.4.7 PCIe Subsystem Address Translation" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf This higher value, 1 MB, was obviously an ugly hack used to be able to handle Resizable BARs which have a minimum size of 1 MB. Now when we actually have support for Resizable BARs, let's configure the iATU alignment requirement to the actual requirement. (BARs described as Resizable will still get aligned to 1 MB.) Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-keystone.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fdc610ec7e5e..76a37368ae4f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -970,7 +970,7 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, .bar[BAR_5] = { .type = BAR_RESIZABLE, }, - .align = SZ_1M, + .align = SZ_64K, }; static const struct pci_epc_features* From patchwork Thu Jan 9 09:06:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13932221 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D6AC215072 for ; Thu, 9 Jan 2025 09:07:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413646; cv=none; b=aJhXnhrv1MSS41JPrhc9pyr6IrT/tSV9ygUeIpUTcW2uBgCGjoCTkJSyjqlm2xnUieNCcfQ6lEL9RZTxL4ZVNGqD+z6naoKyZm7yMguWGikLl/ygJuAjkMLwSOe/Me3Ym2gB3JsOtiqBzqmpNMf80YgyqeHFjJF6qWS5tz5YqFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736413646; c=relaxed/simple; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I1801Ov2HtQF2oeB30ImJXBT7g2jUciAyS2Scmum77FcZhvHvoKfRrdCzJGVOx6vHP727C/yW0BlhQl/xoVNIGpAbcVqi1hk7UD+KGSt2FsXJ6V28wMuduipzGQC9MRMAo04Thol0jmK4Za4BKl9s4zt9P5JVNAB30zTY7fMCGs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X18kmc8A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X18kmc8A" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0F90C4CED2; Thu, 9 Jan 2025 09:07:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736413646; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X18kmc8A6vFgxxnB7m37j4OZRb4cTcp4oI70EwmaR/7qGXk/yLNUPPQpoiDAziJnv q2Ntlqhpiupa4cr2eGxa46Ji4zoJFL0bLrxBYcsnkq6hYFywMBLrWD9GGXjiqmJpwx kBKAZKp36NWquCvevCnOQkjLRfE86y8UY4WSr44mJqJ03qTHYt4ApDiqjIO7y5z4z+ eVgcZ4StE+uGGYLxVum6j9SoP3ou+P6pwIYxY4nv7UmvEC1kJXk6MdzF9sKJmn86oR ITS+GtImU3s2yx9TLAIv0JfjTKThybIf5oDfaNysHrxLFzwz4p7mlyA+El0wcuM75l XBXKhGks0xS5Q== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 6/6] PCI: dw-rockchip: Describe resizable BARs as resizable BARs Date: Thu, 9 Jan 2025 10:06:58 +0100 Message-ID: <20250109090652.110905-14-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250109090652.110905-8-cassel@kernel.org> References: <20250109090652.110905-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2520; i=cassel@kernel.org; h=from:subject; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLrJ246/n9iHc+0po1bBV95XOt7xmsjf82T498kUZ67P 91vNnQs7ihlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEvikx/OH15mtycl+6LmPH 5d2xpo5+f3WCVzNdFWYW2n32mnPX/ReMDHs8D19b2zv3/f+sw+yaT60NhMsC7ma/6KgN1a2Qdov N4AQA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM, we can see that none of the BARs are Fixed BARs, but actually Resizable BARs. I couldn't find any reference in the rk3568 TRM, but looking at the downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same, so the BARs on rk3568 must also be Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index ce4b511bff9b..6a307a961756 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, + .bar[BAR_4] = { .type = BAR_RESIZABLE, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; /* @@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, .bar[BAR_4] = { .type = BAR_RESERVED, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; static const struct pci_epc_features *