From patchwork Thu Jan 9 10:25:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Divya Koppera X-Patchwork-Id: 13932308 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8965B217648; Thu, 9 Jan 2025 10:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736418202; cv=none; b=oVuS7oo7mobE1O9nYJqBLXRwTk4LDe3uVzTa+Urzia6UGwW85BlyBSZG/8yNxyac7tKnhFW25GUS2NZmtJt385gmUuERP0BeZUj9w/i+S9VC6y/phv6dZRFfQqMaehY11G7Dun5EJFDtsc1e9XfDiPQufFYTRwdL5wYsi+sG/Kw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736418202; c=relaxed/simple; bh=mJZJKnF0bdMm1BwL33UrjHSgsES8q4dVpDzbwRZ6TjE=; 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Thu, 9 Jan 2025 03:22:37 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 9 Jan 2025 03:22:33 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next v2 1/3] net: phy: microchip_rds_ptp: Header file library changes for PEROUT Date: Thu, 9 Jan 2025 15:55:31 +0530 Message-ID: <20250109102533.15621-2-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250109102533.15621-1-divya.koppera@microchip.com> References: <20250109102533.15621-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This ptp header file library changes will cover PEROUT macros that are required to generate periodic output from pin out Signed-off-by: Divya Koppera --- v1 -> v2 - Removed redundant Macros - Given proper naming to event and pin --- drivers/net/phy/microchip_rds_ptp.h | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/net/phy/microchip_rds_ptp.h b/drivers/net/phy/microchip_rds_ptp.h index e95c065728b5..2a3c566b028f 100644 --- a/drivers/net/phy/microchip_rds_ptp.h +++ b/drivers/net/phy/microchip_rds_ptp.h @@ -130,6 +130,38 @@ #define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1 #define MCHP_RDS_PTP_TSU_HARDRESET BIT(0) +#define MCHP_RDS_PTP_CLK_TRGT_SEC_HI 0x15 +#define MCHP_RDS_PTP_CLK_TRGT_SEC_LO 0x16 +#define MCHP_RDS_PTP_CLK_TRGT_NS_HI 0x17 +#define MCHP_RDS_PTP_CLK_TRGT_NS_LO 0x18 + +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI 0x19 +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO 0x1a +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI 0x1b +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO 0x1c + +#define MCHP_RDS_PTP_GEN_CFG 0x01 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8) + +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(value) (((value) & 0xF) << 4) +#define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD BIT(0) +#define MCHP_RDS_PTP_GEN_CFG_POLARITY BIT(1) + +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_ 13 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100MS_ 12 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50MS_ 11 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10MS_ 10 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5MS_ 9 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1MS_ 8 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500US_ 7 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100US_ 6 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50US_ 5 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10US_ 4 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5US_ 3 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1US_ 2 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500NS_ 1 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100NS_ 0 + /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 4 clock cycles in 250MHz. * The value is calculated as following: (1/1000000)/((2^-32)/4) @@ -138,6 +170,10 @@ #define MCHP_RDS_PTP_FIFO_SIZE 8 #define MCHP_RDS_PTP_MAX_ADJ 31249999 +#define MCHP_RDS_PTP_BUFFER_TIME 2 +#define MCHP_RDS_PTP_N_PIN 4 +#define MCHP_RDS_PTP_N_PEROUT 1 + #define BASE_CLK(p) ((p)->clk_base_addr) #define BASE_PORT(p) ((p)->port_base_addr) #define PTP_MMD(p) ((p)->mmd) @@ -176,6 +212,9 @@ struct mchp_rds_ptp_clock { /* Lock for phc */ struct mutex ptp_lock; u8 mmd; + int mchp_rds_ptp_event; + int event_pin; + struct ptp_pin_desc *pin_config; }; struct mchp_rds_ptp_rx_ts { From patchwork Thu Jan 9 10:25:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Divya Koppera X-Patchwork-Id: 13932307 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A3DB217655; Thu, 9 Jan 2025 10:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736418201; cv=none; b=RqVspzYWHWmvX/Qk+TCVfviJ1XlsY+QlDEQNfkbW8IjvVFZaVEeiLU0exjXQvA7PQuf3R4ABYA8Oqk01OaI1myuJ1+x4CNcBx8FgZbQYCYlMoqAo7WX35sKgMoh39PaVgxNb2n1fqjnoY6bCHATJ/zTSDfx0L9DhknOjNGYdD30= ARC-Message-Signature: i=1; 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Thu, 9 Jan 2025 03:22:42 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 9 Jan 2025 03:22:38 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next v2 2/3] net: phy: microchip_t1: Enable pin out specific to lan887x phy for PEROUT signal Date: Thu, 9 Jan 2025 15:55:32 +0530 Message-ID: <20250109102533.15621-3-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250109102533.15621-1-divya.koppera@microchip.com> References: <20250109102533.15621-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Adds support for enabling pin out that is required to generate periodic output signal on lan887x phy. Signed-off-by: Divya Koppera --- v1 -> v2 - Added support of periodic output only for the pinout that is specific to PEROUT --- drivers/net/phy/microchip_t1.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c index 73f28463bc35..551a057c516e 100644 --- a/drivers/net/phy/microchip_t1.c +++ b/drivers/net/phy/microchip_t1.c @@ -273,6 +273,9 @@ /* End offset of samples */ #define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM) +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002 +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8) + #define DRIVER_AUTHOR "Nisar Sayed " #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" @@ -1286,6 +1289,15 @@ static int lan887x_phy_init(struct phy_device *phydev) if (IS_ERR(priv->clock)) return PTR_ERR(priv->clock); + /* Enable pin mux for EVT */ + phy_modify_mmd(phydev, MDIO_MMD_VEND1, + LAN887X_MX_CHIP_TOP_REG_CONTROL1, + LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN, + LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN); 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Thu, 9 Jan 2025 03:22:46 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 9 Jan 2025 03:22:42 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next v2 3/3] net: phy: microchip_rds_ptp : Add PEROUT feature library for RDS PTP supported phys Date: Thu, 9 Jan 2025 15:55:33 +0530 Message-ID: <20250109102533.15621-4-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250109102533.15621-1-divya.koppera@microchip.com> References: <20250109102533.15621-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Adds PEROUT feature for RDS PTP supported phys where we can generate periodic output signal on supported pin out Signed-off-by: Divya Koppera --- v1 -> v2 - Added support of periodic output only for the pinout that is specific to PEROUT --- drivers/net/phy/microchip_rds_ptp.c | 294 ++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/drivers/net/phy/microchip_rds_ptp.c b/drivers/net/phy/microchip_rds_ptp.c index 2936e46531cf..b32b6ae162b3 100644 --- a/drivers/net/phy/microchip_rds_ptp.c +++ b/drivers/net/phy/microchip_rds_ptp.c @@ -54,6 +54,267 @@ static int mchp_rds_phy_set_bits_mmd(struct mchp_rds_ptp_clock *clock, return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val); } +static int mchp_get_pulsewidth(struct phy_device *phydev, + struct ptp_perout_request *perout_request, + int *pulse_width) +{ + struct timespec64 ts_period; + s64 ts_on_nsec, period_nsec; + struct timespec64 ts_on; + + ts_period.tv_sec = perout_request->period.sec; + ts_period.tv_nsec = perout_request->period.nsec; + + ts_on.tv_sec = perout_request->on.sec; + ts_on.tv_nsec = perout_request->on.nsec; + ts_on_nsec = timespec64_to_ns(&ts_on); + period_nsec = timespec64_to_ns(&ts_period); + + if (period_nsec < 200) { + phydev_warn(phydev, "perout period small, minimum is 200ns\n"); + return -EOPNOTSUPP; + } + + switch (ts_on_nsec) { + case 200000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_; + break; + case 100000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100MS_; + break; + case 50000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50MS_; + break; + case 10000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10MS_; + break; + case 5000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5MS_; + break; + case 1000000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1MS_; + break; + case 500000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500US_; + break; + case 100000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100US_; + break; + case 50000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50US_; + break; + case 10000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10US_; + break; + case 5000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5US_; + break; + case 1000: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1US_; + break; + case 500: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500NS_; + break; + case 100: + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100NS_; + break; + default: + phydev_warn(phydev, "Using default pulse width of 200ms\n"); + *pulse_width = MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_; + break; + } + return 0; +} + +static int mchp_general_event_config(struct mchp_rds_ptp_clock *clock, + int pulse_width) +{ + int general_config; + + general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK); + if (general_config < 0) + return general_config; + + general_config &= ~MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK; + general_config |= MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(pulse_width); + general_config &= ~MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD; + general_config |= MCHP_RDS_PTP_GEN_CFG_POLARITY; + + return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK, general_config); +} + +static int mchp_set_clock_reload(struct mchp_rds_ptp_clock *clock, + s64 period_sec, u32 period_nsec) +{ + int rc; + + rc = mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO, + MCHP_RDS_PTP_CLOCK, + lower_16_bits(period_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI, + MCHP_RDS_PTP_CLOCK, + upper_16_bits(period_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO, + MCHP_RDS_PTP_CLOCK, + lower_16_bits(period_nsec)); + if (rc < 0) + return rc; + + return mchp_rds_phy_write_mmd(clock, + MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI, + MCHP_RDS_PTP_CLOCK, + upper_16_bits(period_nsec) & 0x3fff); +} + +static int mchp_set_clock_target(struct mchp_rds_ptp_clock *clock, + s64 start_sec, u32 start_nsec) +{ + int rc; + + /* Set the start time */ + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_LO, + MCHP_RDS_PTP_CLOCK, + lower_16_bits(start_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_HI, + MCHP_RDS_PTP_CLOCK, + upper_16_bits(start_sec)); + if (rc < 0) + return rc; + + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_LO, + MCHP_RDS_PTP_CLOCK, + lower_16_bits(start_nsec)); + if (rc < 0) + return rc; + + return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_HI, + MCHP_RDS_PTP_CLOCK, + upper_16_bits(start_nsec) & 0x3fff); +} + +static int mchp_rds_ptp_perout_off(struct mchp_rds_ptp_clock *clock) +{ + u16 general_config; + int rc; + + /* Set target to too far in the future, effectively disabling it */ + rc = mchp_set_clock_target(clock, 0xFFFFFFFF, 0); + if (rc < 0) + return rc; + + general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK); + general_config |= MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD; + rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG, + MCHP_RDS_PTP_CLOCK, general_config); + if (rc < 0) + return rc; + + clock->mchp_rds_ptp_event = -1; + + return 0; +} + +static bool mchp_get_event(struct mchp_rds_ptp_clock *clock, int pin) +{ + if (clock->mchp_rds_ptp_event < 0 && pin == clock->event_pin) { + clock->mchp_rds_ptp_event = pin; + return true; + } + + return false; +} + +static int mchp_rds_ptp_perout(struct ptp_clock_info *ptpci, + struct ptp_perout_request *perout, int on) +{ + struct mchp_rds_ptp_clock *clock = container_of(ptpci, + struct mchp_rds_ptp_clock, + caps); + struct phy_device *phydev = clock->phydev; + int ret, event_pin, pulsewidth; + + /* Reject requests with unsupported flags */ + if (perout->flags & ~PTP_PEROUT_DUTY_CYCLE) + return -EOPNOTSUPP; + + event_pin = ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, + perout->index); + if (event_pin != clock->event_pin) + return -EINVAL; + + if (!on) { + ret = mchp_rds_ptp_perout_off(clock); + return ret; + } + + if (!mchp_get_event(clock, event_pin)) + return -EINVAL; + + ret = mchp_get_pulsewidth(phydev, perout, &pulsewidth); + if (ret < 0) + return ret; + + /* Configure to pulse every period */ + ret = mchp_general_event_config(clock, pulsewidth); + if (ret < 0) + return ret; + + ret = mchp_set_clock_target(clock, perout->start.sec, + perout->start.nsec); + if (ret < 0) + return ret; + + return mchp_set_clock_reload(clock, perout->period.sec, + perout->period.nsec); +} + +static int mchp_rds_ptpci_enable(struct ptp_clock_info *ptpci, + struct ptp_clock_request *request, int on) +{ + switch (request->type) { + case PTP_CLK_REQ_PEROUT: + return mchp_rds_ptp_perout(ptpci, &request->perout, on); + default: + return -EINVAL; + } +} + +static int mchp_rds_ptpci_verify(struct ptp_clock_info *ptpci, unsigned int pin, + enum ptp_pin_function func, unsigned int chan) +{ + struct mchp_rds_ptp_clock *clock = container_of(ptpci, + struct mchp_rds_ptp_clock, + caps); + + if (!(pin == clock->event_pin && chan == 0)) + return -1; + + switch (func) { + case PTP_PF_NONE: + case PTP_PF_PEROUT: + break; + default: + return -1; + } + + return 0; +} + static int mchp_rds_ptp_flush_fifo(struct mchp_rds_ptp_clock *clock, enum mchp_rds_ptp_fifo_dir dir) { @@ -479,6 +740,16 @@ static int mchp_rds_ptp_ltc_adjtime(struct ptp_clock_info *info, s64 delta) MCHP_RDS_PTP_CMD_CTL_LTC_STEP_NSEC); } + mutex_unlock(&clock->ptp_lock); + info->gettime64(info, &ts); + mutex_lock(&clock->ptp_lock); + + /* Target update is required for pulse generation on events that + * are enabled + */ + if (clock->mchp_rds_ptp_event >= 0) + mchp_set_clock_target(clock, + ts.tv_sec + MCHP_RDS_PTP_BUFFER_TIME, 0); out_unlock: mutex_unlock(&clock->ptp_lock); @@ -989,16 +1260,37 @@ struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd, clock->mmd = mmd; mutex_init(&clock->ptp_lock); + clock->pin_config = devm_kmalloc_array(&phydev->mdio.dev, + MCHP_RDS_PTP_N_PIN, + sizeof(*clock->pin_config), + GFP_KERNEL); + if (!clock->pin_config) + return ERR_PTR(-ENOMEM); + + for (int i = 0; i < MCHP_RDS_PTP_N_PIN; ++i) { + struct ptp_pin_desc *p = &clock->pin_config[i]; + + memset(p, 0, sizeof(*p)); + snprintf(p->name, sizeof(p->name), "pin%d", i); + p->index = i; + p->func = PTP_PF_NONE; + } /* Register PTP clock */ clock->caps.owner = THIS_MODULE; snprintf(clock->caps.name, 30, "%s", phydev->drv->name); clock->caps.max_adj = MCHP_RDS_PTP_MAX_ADJ; clock->caps.n_ext_ts = 0; clock->caps.pps = 0; + clock->caps.n_pins = MCHP_RDS_PTP_N_PIN; + clock->caps.n_per_out = MCHP_RDS_PTP_N_PEROUT; + clock->caps.pin_config = clock->pin_config; clock->caps.adjfine = mchp_rds_ptp_ltc_adjfine; clock->caps.adjtime = mchp_rds_ptp_ltc_adjtime; clock->caps.gettime64 = mchp_rds_ptp_ltc_gettime64; clock->caps.settime64 = mchp_rds_ptp_ltc_settime64; + clock->caps.enable = mchp_rds_ptpci_enable; + clock->caps.verify = mchp_rds_ptpci_verify; + clock->caps.getcrosststamp = NULL; clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->mdio.dev); if (IS_ERR(clock->ptp_clock)) @@ -1021,6 +1313,8 @@ struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd, phydev->mii_ts = &clock->mii_ts; + clock->mchp_rds_ptp_event = -1; + /* Timestamp selected by default to keep legacy API */ phydev->default_timestamp = true;