From patchwork Thu Jan 9 10:35:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13932347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB85FE7719C for ; Thu, 9 Jan 2025 10:35:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D47910ED54; Thu, 9 Jan 2025 10:35:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GwTB9LhX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E6F510ED52; Thu, 9 Jan 2025 10:35:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736418949; x=1767954949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=72P25/YYp+jxX9CJiC6wnnDT8iOXmAfcqBNpZkgbPkQ=; b=GwTB9LhX0lCrt6h0CLT3RfSSiA7FYOUMEG/jOQjKUh3AKadSiWnsYaLo f1MnrvcN3pJl4w85PaeE0T4JDS2JTGpmJ9/a1taSffBl9afXaUNCMr3MJ FkESDEpoLujF454Dbt8QiMIqCTGXfcly48CVSB508sdJNyZ6KeIScH7zT 8xeriH237pD2bK/jHh8pXhu6BM3Bap//DJft5Hb2LlzGwrds6S4OccIGB EGnS+47phRWPLm2FBtZTzvMHkcpM264MCi0iuZTZcasLDOheTJWd+snP4 9FUyAC0Gm4v9pOG8NwKzSbzMywVwnZgXU6QcaYqxeYwI33iwXF06FzOFT g==; X-CSE-ConnectionGUID: 7LaC7VGERsSzQ3201OT8+Q== X-CSE-MsgGUID: v3uOGYLHR529U9CZB70uYQ== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="48034984" X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="48034984" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:48 -0800 X-CSE-ConnectionGUID: zV+5mkrzRqOfYTdFFcyZtw== X-CSE-MsgGUID: oO7LYEBeS8CNJ6lDNh/sTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="103333008" Received: from fpallare-mobl4.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.185]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:47 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 1/4] drm/i915/psr: Add new function for writing sink panel replay enable bit Date: Thu, 9 Jan 2025 12:35:29 +0200 Message-ID: <20250109103532.2093356-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250109103532.2093356-1-jouni.hogander@intel.com> References: <20250109103532.2093356-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to DP/eDP specification only DP_PANEL_REPLAY_ENABLE has to be set prior link training. For this purpose add a new function which sets this bit on sink side if Panel Replay is supported by the sink and the source. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_psr.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 64c00a8a6850..e592bc01c7fb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -827,6 +827,13 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); } +void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) +{ + if (CAN_PANEL_REPLAY(intel_dp)) + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); +} + static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 956be263c09e..3b2643b83e06 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -30,6 +30,7 @@ bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, void intel_psr_init_dpcd(struct intel_dp *intel_dp); void intel_psr_enable_sink(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp); void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_psr_post_plane_update(struct intel_atomic_state *state, From patchwork Thu Jan 9 10:35:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13932348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9ACB8E77197 for ; Thu, 9 Jan 2025 10:35:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 35D6A10ED5A; Thu, 9 Jan 2025 10:35:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gdabgmtp"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C43110ED56; Thu, 9 Jan 2025 10:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736418950; x=1767954950; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dxBzcNn2jqYUBiyfcNoE897ge8Y4viF1POsFRq5Y86E=; b=gdabgmtpMXltBzVyeVukT56fP+0QMDjUGRZIOjdhNRQn25ac4SCjVtDH e4pKH5panLknyiEXpf2wcd/OLQwhEmjLV559Sa8tJoXSem0AzaGMZ74G9 DjG9xN4kDOPRbk7UMGUX5eJUzW1RdfLypnXcbBYi3+OaQpWrsBWRgUq2x 0WRcFx/EUh516kF1iL3qFkt2ibs7/mRwAKqQfTWDpNGmJf43R4mL1SuFY TTXrrcytxAaFYxlgZH+/nUMXDuUh6TShmFyckS67YAJjQAWLBfbkfITot rXtb+aQQFagP3zZEQR5GxfEF4aENeYx4B34fvY8Ipq77awNKKqO5RFITp Q==; X-CSE-ConnectionGUID: 748sJf4GRWyL5KuNiAN2nQ== X-CSE-MsgGUID: PRXEWFO4SOuh5g8kbiAcfQ== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="48034987" X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="48034987" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:50 -0800 X-CSE-ConnectionGUID: 1hy64ExnSmC4wvPdaA61rw== X-CSE-MsgGUID: 5FSISMjTSg6oKchUF9a2zQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="103333021" Received: from fpallare-mobl4.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.185]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:48 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 2/4] drm/i915/psr: Enable Panel Replay on sink always when it's supported Date: Thu, 9 Jan 2025 12:35:30 +0200 Message-ID: <20250109103532.2093356-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250109103532.2093356-1-jouni.hogander@intel.com> References: <20250109103532.2093356-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we are configuring Panel Replay on sink when it get's enabled. This means we need to do full modeset when enabling Panel Replay. This is required as DP specification is saying sink Panel Replay needs to be configured before link training. Avoid full modeset by enabling Panel Replay on sink always when it's supported by the sink and the source. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4f9c50996446..b0ea56e166c5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2890,8 +2890,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state); /* Panel replay has to be enabled in sink dpcd before link training. */ - if (crtc_state->has_panel_replay) - intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); + intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); if (DISPLAY_VER(display) >= 14) mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); From patchwork Thu Jan 9 10:35:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13932349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61361E7719B for ; Thu, 9 Jan 2025 10:35:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA09510ED5D; Thu, 9 Jan 2025 10:35:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TO/MuPR5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 002ED10ED59; Thu, 9 Jan 2025 10:35:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736418951; x=1767954951; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4TsDjtS8yTMLjjAUclP9EGVd4u0ZoIc4M3nEUDHdSjI=; b=TO/MuPR5VM2u8zcwOtC8z+MTMCh3rW++k27y81xTQ9ScZu1H0Hr+HuLD k1PfIXE6ORjjGQaQGQ640vM5YfCJmfD64A6oiy3cOF/Fyceavm77fmAZw fsMRkLAD0CshACQ/TjNHKHKIL5e23OGJhgdaDwX9hpyHy72Een2o6wGeq LniBw7DavWg4WqI11PGfRKI/mMnCmiT04Po4sSzSwCUPzATBHewOHIdqw jyELYl2GUSGuHTtMMUO+j85zTzeUO19oJ9/5Ac1q4wsWyYaXfdFPlUFHm /odiROOPTzFtEtDimj4cwHQ6AnDIvLPOYEiuVZ1uk04rt/eu82jixq1+6 Q==; X-CSE-ConnectionGUID: S7j6eiIgQL2AMYRrSQrl1Q== X-CSE-MsgGUID: WdKaD3GBRRqtZMYPUi+Lbw== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="48034989" X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="48034989" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:51 -0800 X-CSE-ConnectionGUID: ZaUFEn/STlWYjzP4qYl/qg== X-CSE-MsgGUID: FeJ/YAQvSOGZtL/qzOjH5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="103333028" Received: from fpallare-mobl4.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.185]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:50 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 3/4] drm/i915/psr: Make intel_psr_enable_sink as local static function Date: Thu, 9 Jan 2025 12:35:31 +0200 Message-ID: <20250109103532.2093356-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250109103532.2093356-1-jouni.hogander@intel.com> References: <20250109103532.2093356-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Intel_psr_enable_sink is not used outside intel_psr.c. Convert it as local static function. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- drivers/gpu/drm/i915/display/intel_psr.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e592bc01c7fb..f969abc56256 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -814,8 +814,8 @@ static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); } -void intel_psr_enable_sink(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static void intel_psr_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { intel_psr_enable_sink_alpm(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 3b2643b83e06..5f1671d02d76 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -28,8 +28,6 @@ bool intel_encoder_can_psr(struct intel_encoder *encoder); bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_psr_init_dpcd(struct intel_dp *intel_dp); -void intel_psr_enable_sink(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp); void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc); From patchwork Thu Jan 9 10:35:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13932350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6228E77197 for ; Thu, 9 Jan 2025 10:35:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7893E10ED59; Thu, 9 Jan 2025 10:35:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XXWIxHLy"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E15410ED59; Thu, 9 Jan 2025 10:35:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736418953; x=1767954953; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FBXqk+wD31EZZsGUXH8dTqD60lGlgdE/RNhvtE2bd8o=; b=XXWIxHLymHKuOTcS0P2xB7O/s+XbJ0cFyBWvBqOKLYHRgAI5q4P2zm46 ALS5M7L/Mcy6bPcWcNx6K2kvmgvZKoDmuGHIImG+jTKHe/Q6Gn5Hn8OAE xHZoVdcKqkD3lW3a4aEHre8CLxirfWOrVk1I4XBeSwqMwq5df416zEYxP TmK3E8y+ZX7cUvC06OjQzA2DPau19fyZDjnBvT+tPjuzJ0jdrFXjFSGkE MkpN1i9+97esm07iohtBb1ODTEblh0e0ApDLYpLeulgWQGCrKdlFOtIw3 6hxQc/mKh7e5SpEwGp8U0bn02xDpSWWxGMUiaCG12CwG6jpy1y6pwx7U5 w==; X-CSE-ConnectionGUID: xiParz0RTSq9G5FCrStcuA== X-CSE-MsgGUID: /3ky0JYWQ6uQ/9sW9JU3pQ== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="48034991" X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="48034991" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:53 -0800 X-CSE-ConnectionGUID: MSmil3ymT1y2xPhOoabKvA== X-CSE-MsgGUID: 4kMbUslnSPi/ijyxfAfyPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,301,1728975600"; d="scan'208";a="103333036" Received: from fpallare-mobl4.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.185]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 02:35:51 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 4/4] drm/i915/psr: Allow changing Panel Replay mode without full modeset Date: Thu, 9 Jan 2025 12:35:32 +0200 Message-ID: <20250109103532.2093356-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250109103532.2093356-1-jouni.hogander@intel.com> References: <20250109103532.2093356-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we are forcing full modeset if Panel Replay mode is changed. This is not necessary as long as we are not changing sink PANEL REPLAY ENABLE bit in PANEL REPLAY ENABLE AND CONFIGURATION 1 register. This can be achieved by entering Panel Replay inactive mode (Live Frame mode) when Panel Replay is disabled and keep PANEL REPLAY ENABLE bit in PANEL REPLAY ENABLE AND CONFIGURATION 1 enabled always if panel is just supporting Panel Replay. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 14 ----------- drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++++++++------- 2 files changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 21319f753a34..35499eb296b3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5638,20 +5638,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_CSC(output_csc); } - /* - * Panel replay has to be enabled before link training. PSR doesn't have - * this requirement -> check these only if using panel replay - */ - if (current_config->active_planes && - (current_config->has_panel_replay || - pipe_config->has_panel_replay)) { - PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_sel_update); - PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); - PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); - PIPE_CONF_CHECK_BOOL(has_panel_replay); - } - PIPE_CONF_CHECK_BOOL(double_wide); if (dev_priv->display.dpll.mgr) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f969abc56256..3494620d1c44 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1998,18 +1998,25 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, if (!psr_interrupt_error_check(intel_dp)) return; - if (intel_dp->psr.panel_replay_enabled) { + if (intel_dp->psr.panel_replay_enabled) drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); - } else { + else drm_dbg_kms(display->drm, "Enabling PSR%s\n", intel_dp->psr.sel_update_enabled ? "2" : "1"); - /* - * Panel replay has to be enabled before link training: doing it - * only for PSR here. - */ - intel_psr_enable_sink(intel_dp, crtc_state); - } + /* + * Enabling here only for PSR. Panel Replay enable bit is already + * written at this point. See + * intel_psr_panel_replay_enable_sink. Modifiers/options: + * - Selective Update + * - Region Early Transport + * - Selective Update Region Scanline Capture + * - VSC_SDP_CRC + * - HPD on different Errors + * - CRC verification + * are written for PSR and Panel Replay here. + */ + intel_psr_enable_sink(intel_dp, crtc_state); if (intel_dp_is_edp(intel_dp)) intel_snps_phy_update_psr_power_state(&dig_port->base, true); @@ -2815,6 +2822,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; needs_to_disable |= new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled; + needs_to_disable |= new_crtc_state->has_panel_replay != + psr->panel_replay_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled;