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Thu, 9 Jan 2025 06:39:32 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v4 1/4] Documentation/ABI: Add document for Mellanox PMC driver Date: Thu, 9 Jan 2025 09:39:20 -0500 Message-ID: <9a9e69bd99cad3ad8d1847a6e4e10aff80c6df50.1736413033.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CB:EE_|MW6PR12MB8898:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cef7a26-cb60-4c21-13d5-08dd30bb7592 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: RPIoWs4OqG+qo33R38LMIVKZBXL30bP491MueD4BU7AmxpCwJxVwnR9CWCdK7D4/GF3z17wdNXBZc7IrgH+XVIzXh2OOKtynWvrROvPBoBZthRhDdFbaV4l7O4pmP6dHo6XjN1y/JfAOpGTgz2+4MN9nJTkLoFsmOSem56zxkZy+4K2QlTTVxDg8BmtbxXrw5BJrDwhQG50PbnlCPZODbXefismUsKSDM0001NL7zsd2j6LkrTIFfXbhydWYpbmZ028TAHbFVQBVpupMlQglpq9G5l3n8E6sollwhM9JYQnqkGn21xPUoF0Jp3g6gGMAYOQhVwEKBvjUmxFfLH423ZSfzuSH0mqok72YNMPvaOyJmIE58E5kCtzbjut+vuaSF3CxaXONCNTvYOqr7zAv+v82isCpuP53OK1r5JH3JqAoCLiO12q3PZpXkhamrnQQ1RMO8VRD3YX6lA+RvIYbhctyQTs+1mAJ0q9Y1XcZt3TfUol+IudtP7VXiQueMbTb3tvd7kIh233qAjxtle9MrQj7djVRfV73IvQJqQU8kwjYduw/X+B69qmUByr1POE+e7V79745rs/VT6DAAHbykNPZ3/5n3Xar3jTFjZP66wAYLRX7Uarq/Ly2va9IWno+oy3HyDhZrAuknrI50HwQVzleyHHa44Ax3SKrBwvnLPJnz3CjEZATPMafezmnhTRf2ouRvVji4L3cfFEgAg3ew9oa8V4Neq0ZlazyGSfOlfUkBLOZ2XoJgQs2b/6wgUA9voQH5vZnP5NfFJ1gwRg09Au8xk6iKtCnNqxjxjBL5rXtvkH5qwuRtgBL8tZrwfDm3qLDcAFoX0BYaZAwEFiC5eGUlvyCxejq4fS/ZfYhud7kGHm12nZwUdtWklR2tycBg0PWtE0cB4j1dgmOaJrfSpApStWayB1d0Md54fyOti40DB4S2VDGpc3NqL5ipFISlE8rdXEr9pN0CzMY+E0wY4M5D8ap34v08K6wmUheNJGWUKBdG8/sAYRFvMSv5nCNh8I6B7B/QGKzfM5k5X8KpioKPijV4WnX3rhEl9hKGF9gHf8zuKjWr+mvqVc9KWhkgfamszMRrNeDdPPvFj3NII0XWdyPUAXKZUcvbmee+RsjTriL/XhqgAIvRlxm7t+QxBBOAQLD5G81pMTQav+EbpBZe+TrIY8DjZYwf9Qcbx8KvA0zcvptDTlS3EBelrik8tEFEHqDa1HvEdn2b/Gb1wkUVb/sMlGGLn7PZ/++YeAtCNmPbPR1Lk4qmPpfKZrxoX1puhqjkvV1OFj508QITRNOMlyIpzTB0Alr9BS9m44nFA+gm+OaaQvq12hVaA2LjXFpVdDv6um73nWHwXRkoTIN5UJtbYnjuEYbJig4Roeq2zyxWldZRMDry5uuewmd+LvstZL2pDaHe85sLFlp+bmRz9DKvFsxppok/6fcba3c+ve4Ol6aACHMHXHn8xruFcggZXExtOhMw9YJAh9rAHDhym1V2SnmRg5tm6+BpjI= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2025 14:39:44.5534 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cef7a26-cb60-4c21-13d5-08dd30bb7592 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8898 Document the sysfs interface for programming and monitoring the performance counters in various HW blocks of Mellanox BlueField-1, BlueField-2 and BlueField-3. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson --- .../ABI/testing/sysfs-platform-mellanox-pmc | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-mellanox-pmc diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc new file mode 100644 index 000000000000..9f987c6410da --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc @@ -0,0 +1,54 @@ +HID Driver Description +MLNXBFD0 mlxbf-pmc Performance counters (BlueField-1) +MLNXBFD1 mlxbf-pmc Performance counters (BlueField-2) +MLNXBFD2 mlxbf-pmc Performance counters (BlueField-3) + +What: /sys/bus/platform/devices//hwmon/hwmonX//event_list +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + List of events supported by the counters in the specific block. + It is used to extract the event number or ID associated with + each event. + +What: /sys/bus/platform/devices//hwmon/hwmonX//event +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Event monitored by corresponding counter. This is used to + program or read back the event that should be or is currently + being monitored by counter. + +What: /sys/bus/platform/devices//hwmon/hwmonX//counter +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Counter value of the event being monitored. This is used to + read the counter value of the event which was programmed using + event. This is also used to clear or reset the counter value + by writing 0 to the counter sysfs. + +What: /sys/bus/platform/devices//hwmon/hwmonX//enable +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Start or stop counters. This is used to start the counters + for monitoring the programmed events and also to stop the + counters after the desired duration. Writing value 1 will + start all the counters in the block, and writing 0 will + stop all the counters together. + +What: /sys/bus/platform/devices//hwmon/hwmonX// +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Value of register. This is used to read or reset the registers + where various performance statistics are counted for each block. + Writing 0 to the sysfs will clear the counter, writing any other + value is not allowed. + From patchwork Thu Jan 9 14:39:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shravan Kumar Ramani X-Patchwork-Id: 13932641 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2087.outbound.protection.outlook.com [40.107.244.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 007E221B199; Thu, 9 Jan 2025 14:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.87 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736433598; cv=fail; b=LbMcJ6gHTNAaef0IU8swrqXYivKRCfv05Kgi7s48R3gFHLCXY+KnvXL53ADqueLEreCdHL/rMBoKcep6ubJbXa40RgBLsBuqXxsujqXPvjW/G7fzsOVxcJRUnJ56HZPTQle9XXYG9u50jcdwAc1OUpNiGf8GQEVjXh6q6xYGqq0= ARC-Message-Signature: i=2; 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This will allow the user to repurpose and dedicate any of the counters in the block to counting cycles. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index 9d18dfca6a67..ce967030d62a 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -88,6 +88,7 @@ #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ) #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30) #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28) +#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0x4) #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc) /** @@ -114,6 +115,7 @@ struct mlxbf_pmc_attribute { * @attr_event: Attributes for "event" sysfs files * @attr_event_list: Attributes for "event_list" sysfs files * @attr_enable: Attributes for "enable" sysfs files + * @attr_count_clock: Attributes for "count_clock" sysfs files * @block_attr: All attributes needed for the block * @block_attr_grp: Attribute group for the block */ @@ -126,6 +128,7 @@ struct mlxbf_pmc_block_info { struct mlxbf_pmc_attribute *attr_event; struct mlxbf_pmc_attribute attr_event_list; struct mlxbf_pmc_attribute attr_enable; + struct mlxbf_pmc_attribute attr_count_clock; struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS]; struct attribute_group block_attr_grp; }; @@ -1763,6 +1766,49 @@ static ssize_t mlxbf_pmc_enable_store(struct device *dev, return count; } +/* Show function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_count_clock = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + + blk_num = attr_count_clock->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", reg); +} + +/* Store function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_count_clock = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + int err; + + blk_num = attr_count_clock->nr; + + err = kstrtouint(buf, 0, ®); + if (err < 0) + return err; + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + /* Populate attributes for blocks with counters to monitor performance */ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_num) { @@ -1801,6 +1847,21 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_ attr = NULL; } + if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) { + /* Program crspace counters to count clock cycles using "count_clock" sysfs */ + attr = &pmc->block[blk_num].attr_count_clock; + attr->dev_attr.attr.mode = 0644; + attr->dev_attr.show = mlxbf_pmc_count_clock_show; + attr->dev_attr.store = mlxbf_pmc_count_clock_store; + attr->nr = blk_num; + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, + "count_clock"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; + attr = NULL; + } + pmc->block[blk_num].attr_counter = devm_kcalloc( dev, pmc->block[blk_num].counters, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL); From patchwork Thu Jan 9 14:39:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shravan Kumar Ramani X-Patchwork-Id: 13932642 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2072.outbound.protection.outlook.com [40.107.243.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 027DB21B908; Thu, 9 Jan 2025 14:40:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736433602; cv=fail; b=j3aPXDUAcMb18NmMdF/DplSWC5I5UGfOXbXQk51pOZh2CMn23xdT5LwYrm2ehCYb9go68C+q1vblH8jFVVZx+fjmnvH7JIYSGEADo77Z43+MEQfZAizmL9SxUG+D6YPk9WccsYN7JdmJ/+9HlTR041pubpLO3CyNiIEqqkRZwBs= ARC-Message-Signature: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2025 14:39:57.3869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a782d13-f0d8-40d3-9c63-08dd30bb7d46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6838 The HW clock_measure counter info is passed to the driver from ACPI. Create a new sub-directory for clock_measure events and provide read access to the user. Writes are blocked since the fields are RO. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index ce967030d62a..25270a425ded 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -862,6 +862,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = { {75, "HISTOGRAM_HISTOGRAM_BIN9"}, }; +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = { + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, +}; + static struct mlxbf_pmc_context *pmc; /* UUID used to probe ATF service. */ @@ -1035,6 +1066,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size } else if (strstr(blk, "llt")) { events = mlxbf_pmc_llt_events; size = ARRAY_SIZE(mlxbf_pmc_llt_events); + } else if (strstr(blk, "clock_measure")) { + events = mlxbf_pmc_clock_events; + size = ARRAY_SIZE(mlxbf_pmc_clock_events); } else { events = NULL; size = 0; @@ -1469,14 +1503,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is_l3, u /* Method to read a register */ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) { - u32 ecc_out; + u32 reg; - if (strstr(pmc->block_name[blk_num], "ecc")) { + if ((strstr(pmc->block_name[blk_num], "ecc")) || + (strstr(pmc->block_name[blk_num], "clock_measure"))) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, - &ecc_out)) + ®)) return -EFAULT; - *result = ecc_out; + *result = reg; return 0; } @@ -1490,6 +1525,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) /* Method to write to a register */ static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { + if (strstr(pmc->block_name[blk_num], "clock_measure")) + return -EINVAL; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2025 14:39:58.2559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d1c17f9-edd1-4aac-3604-08dd30bb7dcb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6240 Document newly added "count_clock" sysfs entry for the Mellanox BlueField PMC driver. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson --- Documentation/ABI/testing/sysfs-platform-mellanox-pmc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc index 9f987c6410da..a7896ebfdae6 100644 --- a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc +++ b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc @@ -52,3 +52,14 @@ Description: Writing 0 to the sysfs will clear the counter, writing any other value is not allowed. +What: /sys/bus/platform/devices//hwmon/hwmonX//count_clock +Date: Jan 2025 +KernelVersion: 6.13 +Contact: "Shravan Kumar Ramani " +Description: + Use a counter for counting cycles. This is used to repurpose/dedicate + any of the counters in the block to counting cycles. Each counter is + represented by a bit (bit 0 for counter0, bit1 for counter1 and so on) + and setting the corresponding bit will reserve that specific counter + for counting cycles and override the event setting. +