From patchwork Fri Jan 10 12:26:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934429 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2133920D4E0; Fri, 10 Jan 2025 12:27:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512022; cv=none; b=gc+tXr1u1LF+b3Mkeblv53cfdDXND9nZWb/zw/5xYrnQRpL+EYJyHzi3cXsl5+ANlFV4sm8ZZuPjCiGoantIK4s7bwWlxkbCTaP+PlzcoxTEKpWsinoj0RAkFhRLcHs6QT1piHbB9HNTYuoWMrUFRcIx1Y/X58TBpYGnzNmYj0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512022; c=relaxed/simple; bh=5PrNSKiAb94z9S7D8ygUAtw6L2KNH3DdWyRMQ9xN3Gc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eECawyC7vZxd2ALIa1zdhVPUph1MC9DBIW0vSUKD82L/v/IZbBJ58FbUUG1odOSA85YCJH/n5qKkT91BfbVR3h5GBvptPEAotA6bKR8yG4+zfl4RjAFtFZ8jSVqeKO+9ThGkazHOAmgcr8IXSMML2vVPsfRw5JIKHnf8ITX11xg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV17z3x4Gz6GFlq; Fri, 10 Jan 2025 20:25:19 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 3DF74140A08; Fri, 10 Jan 2025 20:26:57 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:26:56 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 01/14] rasdaemon: Fix for parsing error when trace event's format file is larger than PAGE_SIZE Date: Fri, 10 Jan 2025 12:26:27 +0000 Message-ID: <20250110122641.1668-2-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose When a trace event's format file is larger than PAGE_SIZE (4096) then libtraceevent returns parsing failed when rasdaemon reads the fields. The reason found that tep_parse_event() call in the add_event_handler() internally fails in libtraceevent because of the incomplete format file data read. However libtraceevent did not return error in this stage, which is fixed in the following patch for libtraceevent. https://lore.kernel.org/all/20250109102338.6128644d@gandalf.local.home/ When rasdaemon reads a trace event format file,the maximum data size that can be read is limited to PAGE_SIZE by the seq_read() and seq_read_iter() functions in the kernel. This results in userspace receiving partial data if the format file is larger than PAGE_SIZE, requiring fix in the rasdaemon to read the complete data from the format file. Add fix for reading trace event format files larger than PAGE_SIZE in add_event_handler(). Signed-off-by: Shiju Jose Reviewed-by: Jonathan Cameron --- ras-events.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/ras-events.c b/ras-events.c index 5d8118a..6692a31 100644 --- a/ras-events.c +++ b/ras-events.c @@ -376,7 +376,7 @@ static int filter_ras_mc_event(struct ras_events *ras, char *group, char *event, static int get_pagesize(struct ras_events *ras, struct tep_handle *pevent) { - int fd, len, page_size = 4096; + int fd, len, page_size = 8192; char buf[page_size]; fd = open_trace(ras, "events/header_page", O_RDONLY); @@ -827,7 +827,8 @@ static int add_event_handler(struct ras_events *ras, struct tep_handle *pevent, unsigned int page_size, char *group, char *event, tep_event_handler_func func, char *filter_str, int id) { - int fd, size, rc; + int fd, rc; + int size = 0; char *page, fname[MAX_PATH + 1]; struct tep_event_filter *filter = NULL; @@ -857,13 +858,17 @@ static int add_event_handler(struct ras_events *ras, struct tep_handle *pevent, return rc; } - size = read(fd, page, page_size); + do { + rc = read(fd, page + size, page_size); + if (rc < 0) { + log(TERM, LOG_ERR, "Can't get arch page size\n"); + free(page); + close(fd); + return size; + } + size += rc; + } while (rc > 0); close(fd); - if (size < 0) { - log(TERM, LOG_ERR, "Can't get arch page size\n"); - free(page); - return size; - } /* Registers the special event handlers */ rc = tep_register_event_handler(pevent, -1, group, event, func, ras); From patchwork Fri Jan 10 12:26:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934428 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E97E20CCFF; Fri, 10 Jan 2025 12:26:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512022; cv=none; b=dHgch0zYSDkdn/yjw4/KRU1zwEWeyCAHHKIKH7MbqfoYm1tQzOgIJapzx2owuY3OLRM/US5bOTGrKidIrh3ku35XnEXS3S3UTsXTfBj7aDfOtB0wmueYBlD/I8eOT3fuZ0FSip3PExG26ARU3DNo6pQe47tLUkaPoO/b+MWgXjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512022; c=relaxed/simple; bh=D6bhIDt/2J7FW///EE7RuzuvXMlsMsnemwu6QDnllD0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C52M2gWAfSw3QXcEpsQ4RAMoDj5Ux7WMsPxvvBd1Vq6BbrATdq7aojfsNW42hrzsrVtlAsvYdUqhMN2/iGmNDnBEuO2tdAjn1jc5UUIcT1uLNb/3/Qluf8TlcR7koDlsl6BkXnVvSKPqCB3Db0IT/BVbXfYBMsICZmE5LBJzBtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV18S1Gr8z67mJg; Fri, 10 Jan 2025 20:25:44 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 6E75814022E; Fri, 10 Jan 2025 20:26:58 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:26:57 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 02/14] rasdaemon: cxl: Fix logging of memory event type of DRAM trace event Date: Fri, 10 Jan 2025 12:26:28 +0000 Message-ID: <20250110122641.1668-3-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record. Fix logging of memory event type field of DRAM trace event. For e.g. if value is 0x1 it will be reported as an Invalid Address (General Media Event Record - Memory Event Type) instead of Scrub Media ECC Error (DRAM Event Record - Memory Event Type) and so on. Fixes: 9a2f6186db26 ("rasdaemon: Add support for the CXL dram events") Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index 67ce32e..8733b2b 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -898,6 +898,13 @@ int ras_cxl_general_media_event_handler(struct trace_seq *s, #define CXL_DER_VALID_COLUMN BIT(6) #define CXL_DER_VALID_CORRECTION_MASK BIT(7) +static const char * const cxl_der_mem_event_type[] = { + "Media ECC Error", + "Scrub Media ECC Error", + "Invalid Address", + "Data Path Error", +}; + int ras_cxl_dram_event_handler(struct trace_seq *s, struct tep_record *record, struct tep_event *event, void *context) @@ -938,9 +945,9 @@ int ras_cxl_dram_event_handler(struct trace_seq *s, if (tep_get_field_val(s, event, "type", record, &val, 1) < 0) return -1; ev.type = val; - if (trace_seq_printf(s, "type:%s ", - get_cxl_type_str(cxl_gmer_mem_event_type, - ARRAY_SIZE(cxl_gmer_mem_event_type), + if (trace_seq_printf(s, "memory_event_type:%s ", + get_cxl_type_str(cxl_der_mem_event_type, + ARRAY_SIZE(cxl_der_mem_event_type), ev.type)) <= 0) return -1; From patchwork Fri Jan 10 12:26:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934430 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59D5620D4E1; Fri, 10 Jan 2025 12:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512023; cv=none; b=ROk+Ub13xnMozOdRXSbXvHsk18NKVddeOD6e4M4qTNhuGOenZDHLGu6dgoi533H2KUOmlV4/9g23oS/rjpnRnHDfevqyF7cHGezM4XTnHfJnjU6CjfVu6EKg9938/g02Jj13CfD20sygzbDzxQkzbnA6EUESe0zFkOINJTFBhCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512023; c=relaxed/simple; bh=EyIzN5hw5gWxxHs3Qj+6T0IsAi7m2FKPlyIvVTbPZ7I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c0Z9sQ68sZWnpqag/HS1pC30mKDpTEeIneGVlgFcONRhm5rnxPW0lUssMRSOvcSiFh4wCC+uAXeSOVITq/X2YdWr0NHc/qrmQDR+IYgp/owvQfbjg9swIgYzzaVRBhXtAY9Do0fBYYLD3zOCCrhg4jYzBkbt7+WVl1X2iyOtypg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV14V3JCpz6K5VF; Fri, 10 Jan 2025 20:22:18 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 74C1C140A86; Fri, 10 Jan 2025 20:26:59 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:26:58 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 03/14] rasdaemon: cxl: Fix mismatch in region field's name with kernel DRAM trace event Date: Fri, 10 Jan 2025 12:26:29 +0000 Message-ID: <20250110122641.1668-4-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose Fix mismatch in 'region' field's name with kernel DRAM trace event. Fixes: ea224ad58b37 ("rasdaemon: CXL: Extract, log and record region info from cxl_general_media and cxl_dram events") Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index 8733b2b..7d4fc9f 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -966,7 +966,7 @@ int ras_cxl_dram_event_handler(struct trace_seq *s, if (trace_seq_printf(s, "hpa:0x%llx ", (unsigned long long)ev.hpa) <= 0) return -1; - ev.region = tep_get_field_raw(s, event, "region", record, &len, 1); + ev.region = tep_get_field_raw(s, event, "region_name", record, &len, 1); if (!ev.region) return -1; if (trace_seq_printf(s, "region:%s ", ev.region) <= 0) From patchwork Fri Jan 10 12:26:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934431 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A71420D511; Fri, 10 Jan 2025 12:27:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512024; cv=none; b=sK4p1xzYKjd+bxA78NpE+BnY/aMbB8PU77bARG1QXrldsDYiq9IhgThVM3ymb2jZc+ruxteruRVW12MZL3ZV690mC+AK13S9Xs48MYBMAkWvIhF6ZTxpSGu5svomH9CnggFTpwXs8WKU7g0EI+tev1kNhMDP9zle9HZ8YQF8WjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512024; c=relaxed/simple; bh=6MLwmtaOqZRADd+fnlTNXh3G3u/8An6BRl/MVq0S8EA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PtaUXWrpDlGO9a8/J2A/iwF0W5uC6vTqRDz6jk9OPAo3b+j81Qlt0T34EZlAUfaOReJXwYskFguFJPLdU6JOfvwZrS4qqGG+LoAWBSKmEelH7+s3uyRgH0u3Es0Yq+weiwSZ4HmTg9i72H/8VWRgG79citJ1a5zTKktO2s+wGPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV1825NKkz6GFmH; Fri, 10 Jan 2025 20:25:22 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 9D253140A08; Fri, 10 Jan 2025 20:27:00 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:26:59 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 04/14] rasdaemon: cxl: Add automatic indexing for storing CXL fields in SQLite database Date: Fri, 10 Jan 2025 12:26:30 +0000 Message-ID: <20250110122641.1668-5-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose When the CXL specification adds new fields to the common header of CXL event records, manual updates to the indexing are required to store these CXL fields in the SQLite database. This update introduces automatic indexing to facilitate the storage of CXL fields in the SQLite database, eliminating the need for manual update to indexing. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-record.c | 145 ++++++++++++++++++++++++++++----------------------- 1 file changed, 80 insertions(+), 65 deletions(-) diff --git a/ras-record.c b/ras-record.c index b4a1abd..3d95f97 100644 --- a/ras-record.c +++ b/ras-record.c @@ -780,23 +780,25 @@ int ras_store_cxl_overflow_event(struct ras_events *ras, struct ras_cxl_overflow static int ras_store_cxl_common_hdr(sqlite3_stmt *stmt, struct ras_cxl_event_common_hdr *hdr) { - if (!stmt || !hdr) - return 0; + int idx = 1; - sqlite3_bind_text(stmt, 1, hdr->timestamp, -1, NULL); - sqlite3_bind_text(stmt, 2, hdr->memdev, -1, NULL); - sqlite3_bind_text(stmt, 3, hdr->host, -1, NULL); - sqlite3_bind_int64(stmt, 4, hdr->serial); - sqlite3_bind_text(stmt, 5, hdr->log_type, -1, NULL); - sqlite3_bind_text(stmt, 6, hdr->hdr_uuid, -1, NULL); - sqlite3_bind_int(stmt, 7, hdr->hdr_flags); - sqlite3_bind_int(stmt, 8, hdr->hdr_handle); - sqlite3_bind_int(stmt, 9, hdr->hdr_related_handle); - sqlite3_bind_text(stmt, 10, hdr->hdr_timestamp, -1, NULL); - sqlite3_bind_int(stmt, 11, hdr->hdr_length); - sqlite3_bind_int(stmt, 12, hdr->hdr_maint_op_class); + if (!stmt || !hdr) + return -1; - return 0; + sqlite3_bind_text(stmt, idx++, hdr->timestamp, -1, NULL); + sqlite3_bind_text(stmt, idx++, hdr->memdev, -1, NULL); + sqlite3_bind_text(stmt, idx++, hdr->host, -1, NULL); + sqlite3_bind_int64(stmt, idx++, hdr->serial); + sqlite3_bind_text(stmt, idx++, hdr->log_type, -1, NULL); + sqlite3_bind_text(stmt, idx++, hdr->hdr_uuid, -1, NULL); + sqlite3_bind_int(stmt, idx++, hdr->hdr_flags); + sqlite3_bind_int(stmt, idx++, hdr->hdr_handle); + sqlite3_bind_int(stmt, idx++, hdr->hdr_related_handle); + sqlite3_bind_text(stmt, idx++, hdr->hdr_timestamp, -1, NULL); + sqlite3_bind_int(stmt, idx++, hdr->hdr_length); + sqlite3_bind_int(stmt, idx++, hdr->hdr_maint_op_class); + + return idx; } /* @@ -827,15 +829,19 @@ static const struct db_table_descriptor cxl_generic_event_tab = { int ras_store_cxl_generic_event(struct ras_events *ras, struct ras_cxl_generic_event *ev) { - int rc; struct sqlite3_priv *priv = ras->db_priv; + int idx; + int rc; if (!priv || !priv->stmt_cxl_generic_event) - return 0; + return -1; log(TERM, LOG_INFO, "cxl_generic_event store: %p\n", priv->stmt_cxl_generic_event); - ras_store_cxl_common_hdr(priv->stmt_cxl_generic_event, &ev->hdr); - sqlite3_bind_blob(priv->stmt_cxl_generic_event, 13, ev->data, + idx = ras_store_cxl_common_hdr(priv->stmt_cxl_generic_event, &ev->hdr); + if (idx <= 0) + return -1; + + sqlite3_bind_blob(priv->stmt_cxl_generic_event, idx++, ev->data, CXL_EVENT_RECORD_DATA_LENGTH, NULL); rc = sqlite3_step(priv->stmt_cxl_generic_event); @@ -891,28 +897,31 @@ static const struct db_table_descriptor cxl_general_media_event_tab = { int ras_store_cxl_general_media_event(struct ras_events *ras, struct ras_cxl_general_media_event *ev) { - int rc; struct sqlite3_priv *priv = ras->db_priv; + int idx; + int rc; if (!priv || !priv->stmt_cxl_general_media_event) - return 0; + return -1; log(TERM, LOG_INFO, "cxl_general_media_event store: %p\n", priv->stmt_cxl_general_media_event); - ras_store_cxl_common_hdr(priv->stmt_cxl_general_media_event, &ev->hdr); - sqlite3_bind_int64(priv->stmt_cxl_general_media_event, 13, ev->dpa); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 14, ev->dpa_flags); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 15, ev->descriptor); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 16, ev->type); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 17, ev->transaction_type); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 18, ev->channel); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 19, ev->rank); - sqlite3_bind_int(priv->stmt_cxl_general_media_event, 20, ev->device); - sqlite3_bind_blob(priv->stmt_cxl_general_media_event, 21, ev->comp_id, + idx = ras_store_cxl_common_hdr(priv->stmt_cxl_general_media_event, &ev->hdr); + if (idx <= 0) + return -1; + sqlite3_bind_int64(priv->stmt_cxl_general_media_event, idx++, ev->dpa); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->dpa_flags); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->descriptor); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->type); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->transaction_type); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->channel); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->rank); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->device); + sqlite3_bind_blob(priv->stmt_cxl_general_media_event, idx++, ev->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE, NULL); - sqlite3_bind_int64(priv->stmt_cxl_general_media_event, 22, ev->hpa); - sqlite3_bind_text(priv->stmt_cxl_general_media_event, 23, ev->region, -1, NULL); - sqlite3_bind_text(priv->stmt_cxl_general_media_event, 24, ev->region_uuid, -1, NULL); + sqlite3_bind_int64(priv->stmt_cxl_general_media_event, idx++, ev->hpa); + sqlite3_bind_text(priv->stmt_cxl_general_media_event, idx++, ev->region, -1, NULL); + sqlite3_bind_text(priv->stmt_cxl_general_media_event, idx++, ev->region_uuid, -1, NULL); rc = sqlite3_step(priv->stmt_cxl_general_media_event); if (rc != SQLITE_OK && rc != SQLITE_DONE) @@ -970,32 +979,35 @@ static const struct db_table_descriptor cxl_dram_event_tab = { int ras_store_cxl_dram_event(struct ras_events *ras, struct ras_cxl_dram_event *ev) { - int rc; struct sqlite3_priv *priv = ras->db_priv; + int idx; + int rc; if (!priv || !priv->stmt_cxl_dram_event) - return 0; + return -1; log(TERM, LOG_INFO, "cxl_dram_event store: %p\n", priv->stmt_cxl_dram_event); - ras_store_cxl_common_hdr(priv->stmt_cxl_dram_event, &ev->hdr); - sqlite3_bind_int64(priv->stmt_cxl_dram_event, 13, ev->dpa); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 14, ev->dpa_flags); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 15, ev->descriptor); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 16, ev->type); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 17, ev->transaction_type); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 18, ev->channel); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 19, ev->rank); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 20, ev->nibble_mask); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 21, ev->bank_group); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 22, ev->bank); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 23, ev->row); - sqlite3_bind_int(priv->stmt_cxl_dram_event, 24, ev->column); - sqlite3_bind_blob(priv->stmt_cxl_dram_event, 25, ev->cor_mask, + idx = ras_store_cxl_common_hdr(priv->stmt_cxl_dram_event, &ev->hdr); + if (idx <= 0) + return -1; + sqlite3_bind_int64(priv->stmt_cxl_dram_event, idx++, ev->dpa); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->dpa_flags); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->descriptor); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->type); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->transaction_type); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->channel); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->rank); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->nibble_mask); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->bank_group); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->bank); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->row); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->column); + sqlite3_bind_blob(priv->stmt_cxl_dram_event, idx++, ev->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE, NULL); - sqlite3_bind_int64(priv->stmt_cxl_dram_event, 26, ev->hpa); - sqlite3_bind_text(priv->stmt_cxl_dram_event, 27, ev->region, -1, NULL); - sqlite3_bind_text(priv->stmt_cxl_dram_event, 28, ev->region_uuid, -1, NULL); + sqlite3_bind_int64(priv->stmt_cxl_dram_event, idx++, ev->hpa); + sqlite3_bind_text(priv->stmt_cxl_dram_event, idx++, ev->region, -1, NULL); + sqlite3_bind_text(priv->stmt_cxl_dram_event, idx++, ev->region_uuid, -1, NULL); rc = sqlite3_step(priv->stmt_cxl_dram_event); if (rc != SQLITE_OK && rc != SQLITE_DONE) @@ -1047,24 +1059,27 @@ static const struct db_table_descriptor cxl_memory_module_event_tab = { int ras_store_cxl_memory_module_event(struct ras_events *ras, struct ras_cxl_memory_module_event *ev) { - int rc; struct sqlite3_priv *priv = ras->db_priv; + int idx; + int rc; if (!priv || !priv->stmt_cxl_memory_module_event) - return 0; + return -1; log(TERM, LOG_INFO, "cxl_memory_module_event store: %p\n", priv->stmt_cxl_memory_module_event); - ras_store_cxl_common_hdr(priv->stmt_cxl_memory_module_event, &ev->hdr); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 13, ev->event_type); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 14, ev->health_status); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 15, ev->media_status); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 16, ev->life_used); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 17, ev->dirty_shutdown_cnt); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 18, ev->cor_vol_err_cnt); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 19, ev->cor_per_err_cnt); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 20, ev->device_temp); - sqlite3_bind_int(priv->stmt_cxl_memory_module_event, 21, ev->add_status); + idx = ras_store_cxl_common_hdr(priv->stmt_cxl_memory_module_event, &ev->hdr); + if (idx <= 0) + return -1; + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->event_type); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->health_status); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->media_status); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->life_used); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->dirty_shutdown_cnt); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->cor_vol_err_cnt); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->cor_per_err_cnt); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->device_temp); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->add_status); rc = sqlite3_step(priv->stmt_cxl_memory_module_event); if (rc != SQLITE_OK && rc != SQLITE_DONE) From patchwork Fri Jan 10 12:26:31 2025 Content-Type: text/plain; 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Fri, 10 Jan 2025 13:27:00 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 05/14] rasdaemon: cxl: Update common event to CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:31 +0000 Message-ID: <20250110122641.1668-6-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec 3.1 section 8.2.9.2.1 Table 8-42, Common Event Record format has updated with Maintenance Operation Subclass information. Add updates in rasdaemon CXL event handler for the above spec change and for the corresponding changes in kernel CXL common trace event implementation. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 10 +++++++++- ras-record.c | 5 +++++ ras-record.h | 1 + ras-report.c | 6 ++++-- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index 7d4fc9f..d16eaef 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -575,18 +575,20 @@ int ras_cxl_overflow_event_handler(struct trace_seq *s, /* * Common Event Record Format - * CXL 3.0 section 8.2.9.2.1; Table 8-42 + * CXL 3.1 section 8.2.9.2.1; Table 8-43 */ #define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2) #define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3) #define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4) #define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5) +#define CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID BIT(6) static const struct cxl_event_flags cxl_hdr_flags[] = { { .bit = CXL_EVENT_RECORD_FLAG_PERMANENT, .flag = "PERMANENT_CONDITION" }, { .bit = CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, .flag = "MAINTENANCE_NEEDED" }, { .bit = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, .flag = "PERFORMANCE_DEGRADED" }, { .bit = CXL_EVENT_RECORD_FLAG_HW_REPLACE, .flag = "HARDWARE_REPLACEMENT_NEEDED" }, + { .bit = CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID, .flag = "MAINT_OP_SUB_CLASS_VALID" }, }; static int handle_ras_cxl_common_hdr(struct trace_seq *s, @@ -670,6 +672,12 @@ static int handle_ras_cxl_common_hdr(struct trace_seq *s, if (trace_seq_printf(s, "hdr_maint_op_class:%u ", hdr->hdr_maint_op_class) <= 0) return -1; + if (tep_get_field_val(s, event, "hdr_maint_op_sub_class", record, &val, 1) < 0) + return -1; + hdr->hdr_maint_op_sub_class = val; + if (trace_seq_printf(s, "hdr_maint_op_sub_class:%u ", hdr->hdr_maint_op_sub_class) <= 0) + return -1; + return 0; } diff --git a/ras-record.c b/ras-record.c index 3d95f97..f680ebe 100644 --- a/ras-record.c +++ b/ras-record.c @@ -797,6 +797,7 @@ static int ras_store_cxl_common_hdr(sqlite3_stmt *stmt, struct ras_cxl_event_com sqlite3_bind_text(stmt, idx++, hdr->hdr_timestamp, -1, NULL); sqlite3_bind_int(stmt, idx++, hdr->hdr_length); sqlite3_bind_int(stmt, idx++, hdr->hdr_maint_op_class); + sqlite3_bind_int(stmt, idx++, hdr->hdr_maint_op_sub_class); return idx; } @@ -818,6 +819,7 @@ static const struct db_fields cxl_generic_event_fields[] = { { .name = "hdr_ts", .type = "TEXT" }, { .name = "hdr_length", .type = "INTEGER" }, { .name = "hdr_maint_op_class", .type = "INTEGER" }, + { .name = "hdr_maint_op_sub_class", .type = "INTEGER" }, { .name = "data", .type = "BLOB" }, }; @@ -874,6 +876,7 @@ static const struct db_fields cxl_general_media_event_fields[] = { { .name = "hdr_ts", .type = "TEXT" }, { .name = "hdr_length", .type = "INTEGER" }, { .name = "hdr_maint_op_class", .type = "INTEGER" }, + { .name = "hdr_maint_op_sub_class", .type = "INTEGER" }, { .name = "dpa", .type = "INTEGER" }, { .name = "dpa_flags", .type = "INTEGER" }, { .name = "descriptor", .type = "INTEGER" }, @@ -953,6 +956,7 @@ static const struct db_fields cxl_dram_event_fields[] = { { .name = "hdr_ts", .type = "TEXT" }, { .name = "hdr_length", .type = "INTEGER" }, { .name = "hdr_maint_op_class", .type = "INTEGER" }, + { .name = "hdr_maint_op_sub_class", .type = "INTEGER" }, { .name = "dpa", .type = "INTEGER" }, { .name = "dpa_flags", .type = "INTEGER" }, { .name = "descriptor", .type = "INTEGER" }, @@ -1039,6 +1043,7 @@ static const struct db_fields cxl_memory_module_event_fields[] = { { .name = "hdr_ts", .type = "TEXT" }, { .name = "hdr_length", .type = "INTEGER" }, { .name = "hdr_maint_op_class", .type = "INTEGER" }, + { .name = "hdr_maint_op_sub_class", .type = "INTEGER" }, { .name = "event_type", .type = "INTEGER" }, { .name = "health_status", .type = "INTEGER" }, { .name = "media_status", .type = "INTEGER" }, diff --git a/ras-record.h b/ras-record.h index cd549a1..2a0124a 100644 --- a/ras-record.h +++ b/ras-record.h @@ -179,6 +179,7 @@ struct ras_cxl_event_common_hdr { char hdr_timestamp[64]; uint8_t hdr_length; uint8_t hdr_maint_op_class; + uint8_t hdr_maint_op_sub_class; }; struct ras_cxl_generic_event { diff --git a/ras-report.c b/ras-report.c index bc77d04..7e974b9 100644 --- a/ras-report.c +++ b/ras-report.c @@ -507,7 +507,8 @@ static int set_cxl_generic_event_backtrace(char *buf, struct ras_cxl_generic_eve "hdr_related_handle=0x%x\n" "hdr_timestamp=%s\n" "hdr_length=%u\n" - "hdr_maint_op_class=%u\n", + "hdr_maint_op_class=%u\n" + "hdr_maint_op_sub_class=%u\n", ev->hdr.timestamp, ev->hdr.memdev, ev->hdr.host, @@ -519,7 +520,8 @@ static int set_cxl_generic_event_backtrace(char *buf, struct ras_cxl_generic_eve ev->hdr.hdr_related_handle, ev->hdr.hdr_timestamp, ev->hdr.hdr_length, - ev->hdr.hdr_maint_op_class); + ev->hdr.hdr_maint_op_class, + ev->hdr.hdr_maint_op_sub_class); return 0; } From patchwork Fri Jan 10 12:26:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934433 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C223C20E037; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV14Z01NJz6K939; Fri, 10 Jan 2025 20:22:22 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 0375F14022E; Fri, 10 Jan 2025 20:27:03 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:27:02 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 06/14] rasdaemon: cxl: Add Component Identifier formatting for CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:32 +0000 Message-ID: <20250110122641.1668-7-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose Add Component Identifier formatting for CXL spec rev 3.1, Section 8.2.9.2.1, Table 8-44. Add helper function to print component ID, parse and log PLDM entity ID and resource ID. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 41 +++++++++++++++++++++++++++++++++++++++++ ras-record.h | 3 +++ 2 files changed, 44 insertions(+) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index d16eaef..80afa9f 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -573,6 +573,47 @@ int ras_cxl_overflow_event_handler(struct trace_seq *s, return 0; } +/* + * Component ID Format + * CXL 3.1 section 8.2.9.2.1; Table 8-44 + */ +#define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0) +#define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1) +static const struct cxl_event_flags cxl_pldm_comp_id_flags[] = { + { .bit = CXL_PLDM_COMPONENT_ID_ENTITY_VALID, .flag = "PLDM Entity ID" }, + { .bit = CXL_PLDM_COMPONENT_ID_RES_VALID, .flag = "Resource ID" }, +}; + +static int ras_cxl_print_component_id(struct trace_seq *s, uint8_t *comp_id, + uint8_t *entity_id, uint8_t *res_id) +{ + int i; + + if (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) { + if (trace_seq_printf(s, "PLDM Entity ID:") <= 0) + return -1; + for (i = 1; i < 7; i++) { + if (trace_seq_printf(s, "%02x ", comp_id[i]) <= 0) + return -1; + } + if (entity_id) + memcpy(entity_id, &comp_id[1], CXL_PLDM_ENTITY_ID_LEN); + } + + if (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) { + if (trace_seq_printf(s, "Resource ID:") <= 0) + return -1; + for (i = 7; i < 11; i++) { + if (trace_seq_printf(s, "%02x ", comp_id[i]) <= 0) + return -1; + } + if (res_id) + memcpy(res_id, &comp_id[7], CXL_PLDM_RES_ID_LEN); + } + + return 0; +} + /* * Common Event Record Format * CXL 3.1 section 8.2.9.2.1; Table 8-43 diff --git a/ras-record.h b/ras-record.h index 2a0124a..a3a88eb 100644 --- a/ras-record.h +++ b/ras-record.h @@ -137,6 +137,9 @@ struct ras_cxl_poison_event { #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 +#define CXL_PLDM_ENTITY_ID_LEN 6 +#define CXL_PLDM_RES_ID_LEN 4 + struct ras_cxl_aer_ue_event { char timestamp[64]; const char *memdev; From patchwork Fri Jan 10 12:26:33 2025 Content-Type: text/plain; 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Fri, 10 Jan 2025 13:27:03 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 07/14] rasdaemon: cxl: Update CXL general media event to CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:33 +0000 Message-ID: <20250110122641.1668-8-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec rev 3.1 section 8.2.9.2.1.1 Table 8-45, General Media Event Record has updated with following new fields and new types for Memory Event Type and Transaction Type fields. 1. Advanced Programmable Corrected Memory Error Threshold Event Flags 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type The format of component identifier has changed (CXL spec 3.1 section 8.2.9.2.1 Table 8-44). Update the parsing, logging and recording of general media event for the above spec changes. Example rasdaemon log for CXL general media event, cxl_general_media 2024-11-19 18:35:29 +0000 memdev:mem3 host:0000:0f:00.0 \ serial:0x3 log type:Fatal hdr_uuid:fbcd0a77-c260-417f-85a9-088b1621eba6 \ hdr_handle:0x1 hdr_related_handle:0x0 hdr_timestamp:1970-01-01 00:01:50 +0000 \ hdr_length:128 hdr_maint_op_class:2 hdr_maint_op_sub_class:4 dpa:0x30d40 \ dpa_flags:descriptor:'UNCORRECTABLE EVENT' 'THRESHOLD EVENT' 'POISON LIST OVERFLOW' \ memory_event_type:TE State Violation memory_event_sub_type:Media Link Command \ Training Error transaction_type:Host Inject Poison channel:3 rank:33 device:5 \ comp_id:03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \ comp_id_pldm_valid_flags:'PLDM Entity ID' 'Resource ID' \ PLDM Entity ID:74 c5 08 9a 1a 0b Resource ID:fc d2 7e 2f \ Advanced Programmable CME threshold Event Flags:'Corrected Memory Errors in Multiple \ Media Components' 'Exceeded Programmable Threshold' Corrected Memory Error Count:0x78 Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 73 +++++++++++++++++++++++++++++++++++++++++++++-- ras-record.c | 13 +++++++++ ras-record.h | 5 ++++ ras-report.c | 10 +++++-- 4 files changed, 96 insertions(+), 5 deletions(-) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index 80afa9f..225bde6 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -772,9 +772,32 @@ static const struct cxl_event_flags cxl_dpa_flags[] = { { .bit = CXL_DPA_NOT_REPAIRABLE, .flag = "NOT_REPAIRABLE" }, }; +/* CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 */ +static const char * const cxl_mem_event_sub_type[] = { + "Not Reported", + "Internal Datapath Error", + "Media Link Command Training Error", + "Media Link Control Training Error", + "Media Link Data Training Error", + "Media Link CRC Error", +}; + +#define CXL_CME_EV_FLAG_CME_MULTIPLE_MEDIA BIT(0) +#define CXL_CME_EV_FLAG_THRESHOLD_EXCEEDED BIT(1) +static const struct cxl_event_flags cxl_cme_threshold_ev_flags[] = { + { + .bit = CXL_CME_EV_FLAG_CME_MULTIPLE_MEDIA, + .flag = "Corrected Memory Errors in Multiple Media Components" + }, + { + .bit = CXL_CME_EV_FLAG_THRESHOLD_EXCEEDED, + .flag = "Exceeded Programmable Threshold" + }, +}; + /* * General Media Event Record - GMER - * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 + * CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 */ #define CXL_GMER_EVT_DESC_UNCORRECTABLE_EVENT BIT(0) #define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1) @@ -790,11 +813,16 @@ static const struct cxl_event_flags cxl_gmer_event_desc_flags[] = { #define CXL_GMER_VALID_RANK BIT(1) #define CXL_GMER_VALID_DEVICE BIT(2) #define CXL_GMER_VALID_COMPONENT BIT(3) +#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4) static const char * const cxl_gmer_mem_event_type[] = { "ECC Error", "Invalid Address", "Data Path Error", + "TE State Violation", + "Scrub Media ECC Error", + "Advanced Programmable CME Counter Expiration", + "CKID Violation", }; static const char * const cxl_gmer_trans_type[] = { @@ -805,13 +833,15 @@ static const char * const cxl_gmer_trans_type[] = { "Host Inject Poison", "Internal Media Scrub", "Internal Media Management", + "Internal Media Error Check Scrub", + "Media Initialization", }; int ras_cxl_general_media_event_handler(struct trace_seq *s, struct tep_record *record, struct tep_event *event, void *context) { - int len, i; + int len, i, rc; unsigned long long val; struct ras_events *ras = context; struct ras_cxl_general_media_event ev; @@ -846,11 +876,20 @@ int ras_cxl_general_media_event_handler(struct trace_seq *s, if (tep_get_field_val(s, event, "type", record, &val, 1) < 0) return -1; ev.type = val; - if (trace_seq_printf(s, "type:%s ", + if (trace_seq_printf(s, "memory_event_type:%s ", get_cxl_type_str(cxl_gmer_mem_event_type, ARRAY_SIZE(cxl_gmer_mem_event_type), ev.type)) <= 0) return -1; + if (tep_get_field_val(s, event, "sub_type", record, &val, 1) < 0) + return -1; + ev.sub_type = val; + if (trace_seq_printf(s, "memory_event_sub_type:%s ", + get_cxl_type_str(cxl_mem_event_sub_type, + ARRAY_SIZE(cxl_mem_event_sub_type), + ev.sub_type)) <= 0) + return -1; + if (tep_get_field_val(s, event, "transaction_type", record, &val, 1) < 0) return -1; ev.transaction_type = val; @@ -918,8 +957,36 @@ int ras_cxl_general_media_event_handler(struct trace_seq *s, if (trace_seq_printf(s, "%02x ", ev.comp_id[i]) <= 0) break; } + + if (ev.validity_flags & CXL_GMER_VALID_COMPONENT_ID_FORMAT) { + if (trace_seq_printf(s, "comp_id_pldm_valid_flags:") <= 0) + return -1; + if (decode_cxl_event_flags(s, ev.comp_id[0], cxl_pldm_comp_id_flags, + ARRAY_SIZE(cxl_pldm_comp_id_flags)) < 0) + return -1; + + rc = ras_cxl_print_component_id(s, ev.comp_id, ev.entity_id, ev.res_id); + if (rc) + return rc; + } } + if (tep_get_field_val(s, event, "cme_threshold_ev_flags", record, &val, 1) < 0) + return -1; + ev.cme_threshold_ev_flags = val; + if (trace_seq_printf(s, "Advanced Programmable CME threshold Event Flags:") <= 0) + return -1; + if (decode_cxl_event_flags(s, ev.cme_threshold_ev_flags, + cxl_cme_threshold_ev_flags, + ARRAY_SIZE(cxl_cme_threshold_ev_flags)) < 0) + return -1; + + if (tep_get_field_val(s, event, "cme_count", record, &val, 1) < 0) + return -1; + ev.cme_count = val; + if (trace_seq_printf(s, "Corrected Memory Error Count:%u ", ev.cme_count) <= 0) + return -1; + /* Insert data into the SGBD */ #ifdef HAVE_SQLITE3 ras_store_cxl_general_media_event(ras, &ev); diff --git a/ras-record.c b/ras-record.c index f680ebe..1020c37 100644 --- a/ras-record.c +++ b/ras-record.c @@ -889,6 +889,11 @@ static const struct db_fields cxl_general_media_event_fields[] = { { .name = "hpa", .type = "INTEGER" }, { .name = "region", .type = "TEXT" }, { .name = "region_uuid", .type = "TEXT" }, + { .name = "pldm_entity_id", .type = "BLOB" }, + { .name = "pldm_resource_id", .type = "BLOB" }, + { .name = "sub_type", .type = "INTEGER" }, + { .name = "cme_threshold_ev_flags", .type = "INTEGER" }, + { .name = "cme_count", .type = "INTEGER" }, }; static const struct db_table_descriptor cxl_general_media_event_tab = { @@ -925,6 +930,14 @@ int ras_store_cxl_general_media_event(struct ras_events *ras, sqlite3_bind_int64(priv->stmt_cxl_general_media_event, idx++, ev->hpa); sqlite3_bind_text(priv->stmt_cxl_general_media_event, idx++, ev->region, -1, NULL); sqlite3_bind_text(priv->stmt_cxl_general_media_event, idx++, ev->region_uuid, -1, NULL); + sqlite3_bind_blob(priv->stmt_cxl_general_media_event, idx++, ev->entity_id, + CXL_PLDM_ENTITY_ID_LEN, NULL); + sqlite3_bind_blob(priv->stmt_cxl_general_media_event, idx++, ev->res_id, + CXL_PLDM_RES_ID_LEN, NULL); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->sub_type); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, + ev->cme_threshold_ev_flags); + sqlite3_bind_int(priv->stmt_cxl_general_media_event, idx++, ev->cme_count); rc = sqlite3_step(priv->stmt_cxl_general_media_event); if (rc != SQLITE_OK && rc != SQLITE_DONE) diff --git a/ras-record.h b/ras-record.h index a3a88eb..12e693b 100644 --- a/ras-record.h +++ b/ras-record.h @@ -196,15 +196,20 @@ struct ras_cxl_general_media_event { uint8_t dpa_flags; uint8_t descriptor; uint8_t type; + uint8_t sub_type; uint8_t transaction_type; uint8_t channel; uint8_t rank; uint32_t device; uint8_t *comp_id; + uint8_t entity_id[CXL_PLDM_ENTITY_ID_LEN]; + uint8_t res_id[CXL_PLDM_RES_ID_LEN]; uint16_t validity_flags; uint64_t hpa; const char *region; const char *region_uuid; + uint8_t cme_threshold_ev_flags; + uint32_t cme_count; }; struct ras_cxl_dram_event { diff --git a/ras-report.c b/ras-report.c index 7e974b9..ed1f4b8 100644 --- a/ras-report.c +++ b/ras-report.c @@ -555,13 +555,16 @@ static int set_cxl_general_media_event_backtrace(char *buf, struct ras_cxl_gener "dpa_flags=%u\n" "descriptor=%u\n" "type=%u\n" + "sub_type=0x%x\n" "transaction_type=%u\n" "hpa=0x%lx\n" "region=%s\n" "region_uuid=%s\n" "channel=%u\n" "rank=%u\n" - "device=0x%x\n", + "device=0x%x\n" + "cme_threshold_ev_flags=0x%x\n" + "cme_count=0x%x\n", ev->hdr.timestamp, ev->hdr.memdev, ev->hdr.host, @@ -578,13 +581,16 @@ static int set_cxl_general_media_event_backtrace(char *buf, struct ras_cxl_gener ev->dpa_flags, ev->descriptor, ev->type, + ev->sub_type, ev->transaction_type, ev->hpa, ev->region, ev->region_uuid, ev->channel, ev->rank, - ev->device); + ev->device, + ev->cme_threshold_ev_flags, + ev->cme_count); return 0; } From patchwork Fri Jan 10 12:26:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934435 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31F9120E701; Fri, 10 Jan 2025 12:27:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512030; cv=none; b=L1mvH7w0nmjKRtWQ5ONsdj9siYSGdmSKtOn4+pb47OIp7g1xD9fcg/mqlgKysGT4NytRwA1/KQiAqk4EtfoI9EdxobxYFIXCBKV1fxG2ubGz5rjqpAo4QF1Dy9QdNVgzcvZbXgLYfrgcR0jnR0wvIdnDyYsyDOPGC7kZuB3kJzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512030; 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Fri, 10 Jan 2025 20:27:05 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:27:04 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 08/14] rasdaemon: cxl: Update CXL DRAM event to CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:34 +0000 Message-ID: <20250110122641.1668-9-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated with following new fields and new types for Memory Event Type, Transaction Type and Validity Flags fields. 1. Component Identifier 2. Sub-channel 3. Advanced Programmable Corrected Memory Error Threshold Event Flags 4. Corrected Memory Error Count at Event 5. Memory Event Sub-Type Update the parsing, logging and recording of DRAM event for the above spec rev 3.1 changes. Example rasdaemon log for CXL DRAM event, cxl_dram 2024-11-19 18:39:00 +0000 memdev:mem3 host:0000:0f:00.0 serial:0x3 \ log type:Informational hdr_uuid:601dcbb3-9c06-4eab-b8af-4e9bfb5c9624 \ hdr_handle:0x1 hdr_related_handle:0x0 hdr_timestamp:1970-01-01 00:05:21 +0000 \ hdr_length:128 hdr_maint_op_class:1 hdr_maint_op_sub_class:3 dpa:0x18680 \ dpa_flags:descriptor:'UNCORRECTABLE EVENT' 'THRESHOLD EVENT' \ memory_event_type:Data Path Error memory_event_sub_type:Media Link CRC Error \ transaction_type:Internal Media Scrub channel:3 rank:17 nibble_mask:3866802 \ bank_group:7 bank:11 row:2 column:77 correction_mask:21 00 00 00 00 00 00 00 \ 2c 00 00 00 00 00 00 00 37 00 00 00 00 00 00 00 42 00 00 00 00 00 00 00 \ comp_id:01 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \ comp_id_pldm_valid_flags:'PLDM Entity ID' PLDM Entity ID:74 c5 08 9a 1a 0b \ Advanced Programmable CME threshold Event Flags:'Corrected Memory Errors in \ Multiple Media Components' 'Exceeded Programmable Threshold' CVME Count:0x94 Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 67 +++++++++++++++++++++++++++++++++++++++++++++-- ras-record.c | 18 +++++++++++++ ras-record.h | 7 +++++ ras-report.c | 12 +++++++-- 4 files changed, 100 insertions(+), 4 deletions(-) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index 225bde6..3dd795e 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -1003,7 +1003,7 @@ int ras_cxl_general_media_event_handler(struct trace_seq *s, /* * DRAM Event Record - DER * - * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 + * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46 */ #define CXL_DER_VALID_CHANNEL BIT(0) #define CXL_DER_VALID_RANK BIT(1) @@ -1013,19 +1013,25 @@ int ras_cxl_general_media_event_handler(struct trace_seq *s, #define CXL_DER_VALID_ROW BIT(5) #define CXL_DER_VALID_COLUMN BIT(6) #define CXL_DER_VALID_CORRECTION_MASK BIT(7) +#define CXL_DER_VALID_COMPONENT_ID BIT(8) +#define CXL_DER_VALID_COMPONENT_ID_FORMAT BIT(9) +#define CXL_DER_VALID_SUB_CHANNEL BIT(10) static const char * const cxl_der_mem_event_type[] = { "Media ECC Error", "Scrub Media ECC Error", "Invalid Address", "Data Path Error", + "TE State Violation", + "Advanced Programmable CME Counter Expiration", + "CKID Violation", }; int ras_cxl_dram_event_handler(struct trace_seq *s, struct tep_record *record, struct tep_event *event, void *context) { - int len, i; + int len, i, rc; unsigned long long val; struct ras_events *ras = context; struct ras_cxl_dram_event ev; @@ -1067,6 +1073,15 @@ int ras_cxl_dram_event_handler(struct trace_seq *s, ev.type)) <= 0) return -1; + if (tep_get_field_val(s, event, "sub_type", record, &val, 1) < 0) + return -1; + ev.sub_type = val; + if (trace_seq_printf(s, "memory_event_sub_type:%s ", + get_cxl_type_str(cxl_mem_event_sub_type, + ARRAY_SIZE(cxl_mem_event_sub_type), + ev.sub_type)) <= 0) + return -1; + if (tep_get_field_val(s, event, "transaction_type", record, &val, 1) < 0) return -1; ev.transaction_type = val; @@ -1108,6 +1123,14 @@ int ras_cxl_dram_event_handler(struct trace_seq *s, return -1; } + if (ev.validity_flags & CXL_DER_VALID_SUB_CHANNEL) { + if (tep_get_field_val(s, event, "sub_channel", record, &val, 1) < 0) + return -1; + ev.sub_channel = val; + if (trace_seq_printf(s, "sub_channel:%u ", ev.sub_channel) <= 0) + return -1; + } + if (ev.validity_flags & CXL_DER_VALID_RANK) { if (tep_get_field_val(s, event, "rank", record, &val, 1) < 0) return -1; @@ -1168,6 +1191,46 @@ int ras_cxl_dram_event_handler(struct trace_seq *s, } } + if (ev.validity_flags & CXL_DER_VALID_COMPONENT_ID) { + ev.comp_id = tep_get_field_raw(s, event, "comp_id", record, &len, 1); + if (!ev.comp_id) + return -1; + if (trace_seq_printf(s, "comp_id:") <= 0) + return -1; + for (i = 0; i < CXL_EVENT_GEN_MED_COMP_ID_SIZE; i++) { + if (trace_seq_printf(s, "%02x ", ev.comp_id[i]) <= 0) + break; + } + + if (ev.validity_flags & CXL_DER_VALID_COMPONENT_ID_FORMAT) { + if (trace_seq_printf(s, "comp_id_pldm_valid_flags:") <= 0) + return -1; + if (decode_cxl_event_flags(s, ev.comp_id[0], cxl_pldm_comp_id_flags, + ARRAY_SIZE(cxl_pldm_comp_id_flags)) < 0) + return -1; + + rc = ras_cxl_print_component_id(s, ev.comp_id, ev.entity_id, ev.res_id); + if (rc) + return rc; + } + } + + if (tep_get_field_val(s, event, "cme_threshold_ev_flags", record, &val, 1) < 0) + return -1; + ev.cme_threshold_ev_flags = val; + if (trace_seq_printf(s, "Advanced Programmable CME threshold Event Flags:") <= 0) + return -1; + if (decode_cxl_event_flags(s, ev.cme_threshold_ev_flags, + cxl_cme_threshold_ev_flags, + ARRAY_SIZE(cxl_cme_threshold_ev_flags)) < 0) + return -1; + + if (tep_get_field_val(s, event, "cvme_count", record, &val, 1) < 0) + return -1; + ev.cvme_count = val; + if (trace_seq_printf(s, "CVME Count:%u ", ev.cvme_count) <= 0) + return -1; + /* Insert data into the SGBD */ #ifdef HAVE_SQLITE3 ras_store_cxl_dram_event(ras, &ev); diff --git a/ras-record.c b/ras-record.c index 1020c37..9799d7e 100644 --- a/ras-record.c +++ b/ras-record.c @@ -986,6 +986,13 @@ static const struct db_fields cxl_dram_event_fields[] = { { .name = "hpa", .type = "INTEGER" }, { .name = "region", .type = "TEXT" }, { .name = "region_uuid", .type = "TEXT" }, + { .name = "comp_id", .type = "BLOB" }, + { .name = "pldm_entity_id", .type = "BLOB" }, + { .name = "pldm_resource_id", .type = "BLOB" }, + { .name = "sub_type", .type = "INTEGER" }, + { .name = "sub_channel", .type = "INTEGER" }, + { .name = "cme_threshold_ev_flags", .type = "INTEGER" }, + { .name = "cvme_count", .type = "INTEGER" }, }; static const struct db_table_descriptor cxl_dram_event_tab = { @@ -1025,6 +1032,17 @@ int ras_store_cxl_dram_event(struct ras_events *ras, struct ras_cxl_dram_event * sqlite3_bind_int64(priv->stmt_cxl_dram_event, idx++, ev->hpa); sqlite3_bind_text(priv->stmt_cxl_dram_event, idx++, ev->region, -1, NULL); sqlite3_bind_text(priv->stmt_cxl_dram_event, idx++, ev->region_uuid, -1, NULL); + sqlite3_bind_blob(priv->stmt_cxl_dram_event, idx++, ev->comp_id, + CXL_EVENT_GEN_MED_COMP_ID_SIZE, NULL); + sqlite3_bind_blob(priv->stmt_cxl_dram_event, idx++, ev->entity_id, + CXL_PLDM_ENTITY_ID_LEN, NULL); + sqlite3_bind_blob(priv->stmt_cxl_dram_event, idx++, ev->res_id, + CXL_PLDM_RES_ID_LEN, NULL); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->sub_type); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->sub_channel); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, + ev->cme_threshold_ev_flags); + sqlite3_bind_int(priv->stmt_cxl_dram_event, idx++, ev->cvme_count); rc = sqlite3_step(priv->stmt_cxl_dram_event); if (rc != SQLITE_OK && rc != SQLITE_DONE) diff --git a/ras-record.h b/ras-record.h index 12e693b..3aec063 100644 --- a/ras-record.h +++ b/ras-record.h @@ -218,8 +218,10 @@ struct ras_cxl_dram_event { uint8_t dpa_flags; uint8_t descriptor; uint8_t type; + uint8_t sub_type; uint8_t transaction_type; uint8_t channel; + uint8_t sub_channel; uint8_t rank; uint32_t nibble_mask; uint8_t bank_group; @@ -231,6 +233,11 @@ struct ras_cxl_dram_event { uint64_t hpa; const char *region; const char *region_uuid; + uint8_t *comp_id; + uint8_t entity_id[CXL_PLDM_ENTITY_ID_LEN]; + uint8_t res_id[CXL_PLDM_RES_ID_LEN]; + uint8_t cme_threshold_ev_flags; + uint32_t cvme_count; }; struct ras_cxl_memory_module_event { diff --git a/ras-report.c b/ras-report.c index ed1f4b8..8e343fc 100644 --- a/ras-report.c +++ b/ras-report.c @@ -624,17 +624,21 @@ static int set_cxl_dram_event_backtrace(char *buf, struct ras_cxl_dram_event *ev "dpa_flags=%u\n" "descriptor=%u\n" "type=%u\n" + "sub_type=0x%x\n" "transaction_type=%u\n" "hpa=0x%lx\n" "region=%s\n" "region_uuid=%s\n" "channel=%u\n" + "sub_channel=%u\n" "rank=%u\n" "nibble_mask=%u\n" "bank_group=%u\n" "bank=%u\n" "row=%u\n" - "column=%u\n", + "column=%u\n" + "cme_threshold_ev_flags=0x%x\n" + "cvme_count=0x%x\n", ev->hdr.timestamp, ev->hdr.memdev, ev->hdr.host, @@ -651,17 +655,21 @@ static int set_cxl_dram_event_backtrace(char *buf, struct ras_cxl_dram_event *ev ev->dpa_flags, ev->descriptor, ev->type, + ev->sub_type, ev->transaction_type, ev->hpa, ev->region, ev->region_uuid, ev->channel, + ev->sub_channel, ev->rank, ev->nibble_mask, ev->bank_group, ev->bank, ev->row, - ev->column); + ev->column, + ev->cme_threshold_ev_flags, + ev->cvme_count); return 0; } From patchwork Fri Jan 10 12:26:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934436 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E69120D4F6; Fri, 10 Jan 2025 12:27:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512031; cv=none; b=TeKr35Zcg6LFa/8/onhA4O9zijAKfMgDpH//WTiNLkI9IhqkoA/UiWh90zWljEyi8n/TzSPtRmdxSB5MAi01UOQvBKmWfeVpPbVH0nXjXhAO+olZQyAl1fYSaPYsUpZ3CXE5BpWstaAVdzzvxFI5cMM7L8R0kcjq/LLvtxuGDDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512031; 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Fri, 10 Jan 2025 20:27:06 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:27:05 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 09/14] rasdaemon: cxl: Update memory module event to CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:35 +0000 Message-ID: <20250110122641.1668-10-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec 3.1 section 8.2.9.2.1.3 Table 8-47, Memory Module Event Record has updated with following new fields and new info for Device Event Type and Device Health Information fields. 1. Validity Flags 2. Component Identifier 3. Device Event Sub-Type Update the parsing, logging and recording of memory module event for the above spec rev 3.1 changes. Example rasdaemon log for CXL memory module event, cxl_memory_module 2024-11-19 18:43:15 +0000 memdev:mem3 host:0000:0f:00.0 \ serial:0x3 log type:Fatal hdr_uuid:fe927475-dd59-4339-a586-79bab113b774 \ hdr_handle:0x2 hdr_related_handle:0x0 hdr_timestamp:1970-01-01 00:09:36 +0000 \ hdr_length:128 hdr_maint_op_class:0 hdr_maint_op_sub_class:1 \ event_type:Temperature Change event_sub_type:Unsupported Config Data \ health_status:'MAINTENANCE_NEEDED' 'REPLACEMENT_NEEDED' \ media_status:All Data Loss in Event of Power Loss as_life_used:Unknown \ as_dev_temp:Normal as_cor_vol_err_cnt:Normal as_cor_per_err_cnt:Normal \ life_used:8 device_temp:3 dirty_shutdown_cnt:33 cor_vol_err_cnt:25 \ cor_per_err_cnt:45 comp_id:02 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \ comp_id_pldm_valid_flags:'Resource ID' Resource ID:fc d2 7e 2f Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- ras-cxl-handler.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-- ras-record.c | 11 ++++++++++ ras-record.h | 5 +++++ ras-report.c | 2 ++ 4 files changed, 72 insertions(+), 2 deletions(-) diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c index 3dd795e..cb95fa6 100644 --- a/ras-cxl-handler.c +++ b/ras-cxl-handler.c @@ -1247,7 +1247,7 @@ int ras_cxl_dram_event_handler(struct trace_seq *s, /* * Memory Module Event Record - MMER * - * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45 + * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47 */ static const char * const cxl_dev_evt_type[] = { "Health Status Change", @@ -1256,21 +1256,33 @@ static const char * const cxl_dev_evt_type[] = { "Temperature Change", "Data Path Error", "LSA Error", + "Unrecoverable Internal Sideband Bus Error", + "Memory Media FRU Error", + "Power Management Fault", +}; + +static const char * const cxl_dev_evt_sub_type[] = { + "Not Reported", + "Invalid Config Data", + "Unsupported Config Data", + "Unsupported Memory Media FRU", }; /* * Device Health Information - DHI * - * CXL res 3.0 section 8.2.9.8.3.1; Table 8-100 + * CXL res 3.1 section 8.2.9.9.3.1; Table 8-133 */ #define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0) #define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1) #define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2) +#define CXL_DHI_HS_MEM_CAPACITY_DEGRADED BIT(3) static const struct cxl_event_flags cxl_health_status[] = { { .bit = CXL_DHI_HS_MAINTENANCE_NEEDED, .flag = "MAINTENANCE_NEEDED" }, { .bit = CXL_DHI_HS_PERFORMANCE_DEGRADED, .flag = "PERFORMANCE_DEGRADED" }, { .bit = CXL_DHI_HS_HW_REPLACEMENT_NEEDED, .flag = "REPLACEMENT_NEEDED" }, + { .bit = CXL_DHI_HS_MEM_CAPACITY_DEGRADED, .flag = "MEM_CAPACITY_DEGRADED" }, }; static const char * const cxl_media_status[] = { @@ -1302,10 +1314,14 @@ static const char * const cxl_one_bit_status[] = { #define CXL_DHI_AS_COR_VOL_ERR_CNT(as) (((as) & 0x10) >> 4) #define CXL_DHI_AS_COR_PER_ERR_CNT(as) (((as) & 0x20) >> 5) +#define CXL_MMER_VALID_COMPONENT_ID BIT(0) +#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1) + int ras_cxl_memory_module_event_handler(struct trace_seq *s, struct tep_record *record, struct tep_event *event, void *context) { + int len, i, rc; unsigned long long val; struct ras_events *ras = context; struct ras_cxl_memory_module_event ev; @@ -1323,6 +1339,15 @@ int ras_cxl_memory_module_event_handler(struct trace_seq *s, ev.event_type)) <= 0) return -1; + if (tep_get_field_val(s, event, "event_sub_type", record, &val, 1) < 0) + return -1; + ev.event_sub_type = val; + if (trace_seq_printf(s, "event_sub_type:%s ", + get_cxl_type_str(cxl_dev_evt_sub_type, + ARRAY_SIZE(cxl_dev_evt_sub_type), + ev.event_sub_type)) <= 0) + return -1; + if (tep_get_field_val(s, event, "health_status", record, &val, 1) < 0) return -1; ev.health_status = val; @@ -1395,6 +1420,33 @@ int ras_cxl_memory_module_event_handler(struct trace_seq *s, if (trace_seq_printf(s, "cor_per_err_cnt:%u ", ev.cor_per_err_cnt) <= 0) return -1; + if (tep_get_field_val(s, event, "validity_flags", record, &val, 1) < 0) + return -1; + ev.validity_flags = val; + + if (ev.validity_flags & CXL_MMER_VALID_COMPONENT_ID) { + ev.comp_id = tep_get_field_raw(s, event, "comp_id", record, &len, 1); + if (!ev.comp_id) + return -1; + if (trace_seq_printf(s, "comp_id:") <= 0) + return -1; + for (i = 0; i < CXL_EVENT_GEN_MED_COMP_ID_SIZE; i++) { + if (trace_seq_printf(s, "%02x ", ev.comp_id[i]) <= 0) + break; + } + + if (ev.validity_flags & CXL_MMER_VALID_COMPONENT_ID_FORMAT) { + if (trace_seq_printf(s, "comp_id_pldm_valid_flags:") <= 0) + return -1; + if (decode_cxl_event_flags(s, ev.comp_id[0], cxl_pldm_comp_id_flags, + ARRAY_SIZE(cxl_pldm_comp_id_flags)) < 0) + return -1; + + rc = ras_cxl_print_component_id(s, ev.comp_id, ev.entity_id, ev.res_id); + if (rc) + return rc; + } + } /* Insert data into the SGBD */ #ifdef HAVE_SQLITE3 ras_store_cxl_memory_module_event(ras, &ev); diff --git a/ras-record.c b/ras-record.c index 9799d7e..eed7aca 100644 --- a/ras-record.c +++ b/ras-record.c @@ -1084,6 +1084,10 @@ static const struct db_fields cxl_memory_module_event_fields[] = { { .name = "cor_per_err_cnt", .type = "INTEGER" }, { .name = "device_temp", .type = "INTEGER" }, { .name = "add_status", .type = "INTEGER" }, + { .name = "event_sub_type", .type = "INTEGER" }, + { .name = "comp_id", .type = "BLOB" }, + { .name = "pldm_entity_id", .type = "BLOB" }, + { .name = "pldm_resource_id", .type = "BLOB" }, }; static const struct db_table_descriptor cxl_memory_module_event_tab = { @@ -1116,6 +1120,13 @@ int ras_store_cxl_memory_module_event(struct ras_events *ras, sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->cor_per_err_cnt); sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->device_temp); sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->add_status); + sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->event_sub_type); + sqlite3_bind_blob(priv->stmt_cxl_memory_module_event, idx++, ev->comp_id, + CXL_EVENT_GEN_MED_COMP_ID_SIZE, NULL); + sqlite3_bind_blob(priv->stmt_cxl_memory_module_event, idx++, ev->entity_id, + CXL_PLDM_ENTITY_ID_LEN, NULL); + sqlite3_bind_blob(priv->stmt_cxl_memory_module_event, idx++, ev->res_id, + CXL_PLDM_RES_ID_LEN, NULL); rc = sqlite3_step(priv->stmt_cxl_memory_module_event); if (rc != SQLITE_OK && rc != SQLITE_DONE) diff --git a/ras-record.h b/ras-record.h index 3aec063..5eab62c 100644 --- a/ras-record.h +++ b/ras-record.h @@ -243,6 +243,7 @@ struct ras_cxl_dram_event { struct ras_cxl_memory_module_event { struct ras_cxl_event_common_hdr hdr; uint8_t event_type; + uint8_t event_sub_type; uint8_t health_status; uint8_t media_status; uint8_t life_used; @@ -251,6 +252,10 @@ struct ras_cxl_memory_module_event { uint32_t cor_per_err_cnt; int16_t device_temp; uint8_t add_status; + uint16_t validity_flags; + uint8_t *comp_id; + uint8_t entity_id[CXL_PLDM_ENTITY_ID_LEN]; + uint8_t res_id[CXL_PLDM_RES_ID_LEN]; }; struct ras_mc_event; diff --git a/ras-report.c b/ras-report.c index 8e343fc..4535421 100644 --- a/ras-report.c +++ b/ras-report.c @@ -700,6 +700,7 @@ static int set_cxl_memory_module_event_backtrace(char *buf, struct ras_cxl_memor "hdr_length=%u\n" "hdr_maint_op_class=%u\n" "event_type=%u\n" + "event_sub_type=0x%x\n" "health_status=%u\n" "media_status=%u\n" "life_used=%u\n" @@ -721,6 +722,7 @@ static int set_cxl_memory_module_event_backtrace(char *buf, struct ras_cxl_memor ev->hdr.hdr_length, ev->hdr.hdr_maint_op_class, ev->event_type, + ev->event_sub_type, ev->health_status, ev->media_status, ev->life_used, From patchwork Fri Jan 10 12:26:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934437 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9458020E708; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV18B0yv2z6GFm8; Fri, 10 Jan 2025 20:25:30 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id CF8F91406AC; Fri, 10 Jan 2025 20:27:07 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:27:06 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 10/14] rasdaemon: ras-mc-ctl: Fix logging of memory event type in CXL DRAM error table Date: Fri, 10 Jan 2025 12:26:36 +0000 Message-ID: <20250110122641.1668-11-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record. Fix decoding of memory event type in the CXL DRAM error table in RAS SQLite database. For e.g. if value is 0x1 it will be logged as an Invalid Address (General Media Event Record - Memory Event Type) instead of Scrub Media ECC Error (DRAM Event Record - Memory Event Type) and so on. Fixes: c38c14afc5d7 ("rasdaemon: ras-mc-ctl: Add support for CXL DRAM trace events") Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- util/ras-mc-ctl.in | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index c24941f..3f9bad0 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1339,7 +1339,7 @@ sub get_cxl_descriptor_flags_text return join (", ", @out); } -sub get_cxl_mem_event_type +sub get_cxl_gmer_mem_event_type { my @types; @@ -1354,6 +1354,22 @@ sub get_cxl_mem_event_type return $types[$_[0]]; } +sub get_cxl_der_mem_event_type +{ + my @types; + + if ($_[0] < 0 || $_[0] > 3) { + return "unknown-type"; + } + + @types = ("Media ECC Error", + "Scrub Media ECC Error", + "Invalid Address", + "Data Path Error"); + + return $types[$_[0]]; +} + sub get_cxl_transaction_type { my @types; @@ -1978,7 +1994,7 @@ sub errors $out .= sprintf "dpa=0x%llx, ", $dpa if (defined $dpa && length $dpa); $out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags); $out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor); - $out .= sprintf "memory event type: %s, ", get_cxl_mem_event_type($mem_event_type) if (defined $mem_event_type && length $mem_event_type); + $out .= sprintf "memory event type: %s, ", get_cxl_gmer_mem_event_type($mem_event_type) if (defined $mem_event_type && length $mem_event_type); $out .= sprintf "transaction_type: %s, ", get_cxl_transaction_type($transaction_type) if (defined $transaction_type && length $transaction_type); $out .= sprintf "channel=%u, ", $channel if (defined $channel && length $channel); $out .= sprintf "rank=%u, ", $rank if (defined $rank && length $rank); @@ -2024,7 +2040,7 @@ sub errors $out .= sprintf "dpa=0x%llx, ", $dpa if (defined $dpa && length $dpa); $out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags); $out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor); - $out .= sprintf "memory event type: %s, ", get_cxl_mem_event_type($type) if (defined $type && length $type); + $out .= sprintf "memory event type: %s, ", get_cxl_der_mem_event_type($type) if (defined $type && length $type); $out .= sprintf "transaction_type: %s, ", get_cxl_transaction_type($transaction_type) if (defined $transaction_type && length $transaction_type); $out .= sprintf "channel=%u, ", $channel if (defined $channel && length $channel); $out .= sprintf "rank=%u, ", $rank if (defined $rank && length $rank); From patchwork Fri Jan 10 12:26:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934438 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB76A20E71B; Fri, 10 Jan 2025 12:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV18f53rpz6L4yB; Fri, 10 Jan 2025 20:25:54 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id EC98C140A08; Fri, 10 Jan 2025 20:27:08 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:27:08 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 11/14] rasdaemon: ras-mc-ctl: Update logging of common event data to align with CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:37 +0000 Message-ID: <20250110122641.1668-12-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose The Common Event Record format in the CXL spec 3.1, section 8.2.9.2.1, Table 8-42, has been updated to include Maintenance Operation Subclass information. This update modifies ras-mc-ctl to log CXL common event data in the RAS SQLite database tables, reflecting the specification changes introduced in revision 3.1. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- util/ras-mc-ctl.in | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index 3f9bad0..58ee916 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1755,7 +1755,7 @@ sub errors my ($memdev, $host, $serial, $error_status, $first_error, $header_log); my ($log_type, $first_ts, $last_ts); my ($trace_type, $region, $region_uuid, $hpa, $dpa, $dpa_length, $source, $flags, $overflow_ts); - my ($hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $data); + my ($hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $data); my ($dpa_flags, $descriptor, $mem_event_type, $transaction_type, $channel, $rank, $device, $comp_id); my ($nibble_mask, $bank_group, $row, $column, $cor_mask); my ($event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status); @@ -1935,10 +1935,10 @@ sub errors # CXL generic errors use constant CXL_EVENT_RECORD_DATA_LENGTH => 0x50; - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, data from cxl_generic_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, data from cxl_generic_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $data)); + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $data)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -1953,6 +1953,7 @@ sub errors $out .= "hdr_timestamp=$hdr_ts, " if (defined $hdr_ts && length $hdr_ts); $out .= sprintf "hdr_length=%u, ", $hdr_length if (defined $hdr_length && length $hdr_length); $out .= sprintf "hdr_maint_op_class=%u, ", $hdr_maint_op_class if (defined $hdr_maint_op_class && length $hdr_maint_op_class); + $out .= sprintf "hdr_maint_op_sub_class=%u, ", $hdr_maint_op_sub_class if (defined $hdr_maint_op_sub_class && length $hdr_maint_op_sub_class); if (defined $data && length $data) { $out .= sprintf "data:\n"; my @bytes = unpack "C*", $data; @@ -1973,10 +1974,10 @@ sub errors # CXL general media errors use constant CXL_EVENT_GEN_MED_COMP_ID_SIZE => 0x10; - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, device, comp_id, hpa, region, region_uuid from cxl_general_media_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, device, comp_id, hpa, region, region_uuid from cxl_general_media_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $dpa, $dpa_flags, $descriptor, $mem_event_type, $transaction_type, $channel, $rank, $device, $comp_id, $hpa, $region, $region_uuid)); + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $dpa, $dpa_flags, $descriptor, $mem_event_type, $transaction_type, $channel, $rank, $device, $comp_id, $hpa, $region, $region_uuid)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -1991,6 +1992,7 @@ sub errors $out .= "hdr_timestamp=$hdr_ts, " if (defined $hdr_ts && length $hdr_ts); $out .= sprintf "hdr_length=%u, ", $hdr_length if (defined $hdr_length && length $hdr_length); $out .= sprintf "hdr_maint_op_class=%u, ", $hdr_maint_op_class if (defined $hdr_maint_op_class && length $hdr_maint_op_class); + $out .= sprintf "hdr_maint_op_sub_class=%u, ", $hdr_maint_op_sub_class if (defined $hdr_maint_op_sub_class && length $hdr_maint_op_sub_class); $out .= sprintf "dpa=0x%llx, ", $dpa if (defined $dpa && length $dpa); $out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags); $out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor); @@ -2019,10 +2021,10 @@ sub errors # CXL DRAM errors use constant CXL_EVENT_DER_CORRECTION_MASK_SIZE => 0x20; - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, nibble_mask, bank_group, bank, row, column, cor_mask, hpa, region, region_uuid from cxl_dram_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, nibble_mask, bank_group, bank, row, column, cor_mask, hpa, region, region_uuid from cxl_dram_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $dpa, $dpa_flags, $descriptor, $type, $transaction_type, $channel, $rank, $nibble_mask, $bank_group, $bank, $row, $column, $cor_mask, $hpa, $region, $region_uuid)); + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $dpa, $dpa_flags, $descriptor, $type, $transaction_type, $channel, $rank, $nibble_mask, $bank_group, $bank, $row, $column, $cor_mask, $hpa, $region, $region_uuid)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -2037,6 +2039,7 @@ sub errors $out .= "hdr_timestamp=$hdr_ts, " if (defined $hdr_ts && length $hdr_ts); $out .= sprintf "hdr_length=%u, ", $hdr_length if (defined $hdr_length && length $hdr_length); $out .= sprintf "hdr_maint_op_class=%u, ", $hdr_maint_op_class if (defined $hdr_maint_op_class && length $hdr_maint_op_class); + $out .= sprintf "hdr_maint_op_sub_class=%u, ", $hdr_maint_op_sub_class if (defined $hdr_maint_op_sub_class && length $hdr_maint_op_sub_class); $out .= sprintf "dpa=0x%llx, ", $dpa if (defined $dpa && length $dpa); $out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags); $out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor); @@ -2068,10 +2071,10 @@ sub errors } # CXL memory module errors - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, event_type, health_status, media_status, life_used, dirty_shutdown_cnt, cor_vol_err_cnt, cor_per_err_cnt, device_temp, add_status from cxl_memory_module_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, event_type, health_status, media_status, life_used, dirty_shutdown_cnt, cor_vol_err_cnt, cor_per_err_cnt, device_temp, add_status from cxl_memory_module_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status)); + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -2086,6 +2089,7 @@ sub errors $out .= "hdr_timestamp=$hdr_ts, " if (defined $hdr_ts && length $hdr_ts); $out .= sprintf "hdr_length=%u, ", $hdr_length if (defined $hdr_length && length $hdr_length); $out .= sprintf "hdr_maint_op_class=%u, ", $hdr_maint_op_class if (defined $hdr_maint_op_class && length $hdr_maint_op_class); + $out .= sprintf "hdr_maint_op_sub_class=%u, ", $hdr_maint_op_sub_class if (defined $hdr_maint_op_sub_class && length $hdr_maint_op_sub_class); $out .= sprintf "event_type: %s, ", get_cxl_dev_event_type($event_type) if (defined $event_type && length $event_type); $out .= sprintf "health_status: %s, ", get_cxl_health_status_text($health_status) if (defined $health_status && length $health_status); $out .= sprintf "media_status: %s, ", get_cxl_media_status($media_status) if (defined $media_status && length $media_status); From patchwork Fri Jan 10 12:26:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934439 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D26C820FA9A; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YV18g5wdcz6L51y; Fri, 10 Jan 2025 20:25:55 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 19F021403D2; Fri, 10 Jan 2025 20:27:10 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.126.170.14) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 10 Jan 2025 13:27:09 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 12/14] rasdaemon: ras-mc-ctl: Update logging of CXL general media event data to align with CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:38 +0000 Message-ID: <20250110122641.1668-13-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec rev 3.1 section 8.2.9.2.1.1 Table 8-45, General Media Event Record has updated with following new fields and new types for Memory Event Type and Transaction Type fields. 1. Advanced Programmable Corrected Memory Error Threshold Event Flags 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type The format of component identifier has changed (CXL spec 3.1 section 8.2.9.2.1 Table 8-44). This update modifies ras-mc-ctl to parse and log CXL general media event data stored in the RAS SQLite database table, reflecting the specification changes introduced in revision 3.1. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- util/ras-mc-ctl.in | 92 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 80 insertions(+), 12 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index 58ee916..fe21f81 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1339,21 +1339,65 @@ sub get_cxl_descriptor_flags_text return join (", ", @out); } +#CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 +#General Media Event Record - GMER sub get_cxl_gmer_mem_event_type { my @types; - if ($_[0] < 0 || $_[0] > 2) { + if ($_[0] < 0 || $_[0] > 6) { return "unknown-type"; } @types = ("ECC Error", "Invalid Address", - "Data Path Error"); + "Data Path Error", + "TE State Violation", + "Scrub Media ECC Error", + "Advanced Programmable CME Counter Expiration", + "CKID Violation"); return $types[$_[0]]; } +# CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 +sub get_cxl_mem_event_sub_type +{ + my @types; + + if ($_[0] < 0 || $_[0] > 5) { + return "unknown-type"; + } + + @types = ("Not Reported", + "Internal Datapath Error", + "Media Link Command Training Error", + "Media Link Control Training Error", + "Media Link Data Training Error", + "Media Link CRC Error"); + + return $types[$_[0]]; +} + +use constant { + CXL_EVT_FLAG_CME_MULTIPLE_MEDIA => 0x0001, + CXL_EVT_FLAG_THRESHOLD_EXCEEDED => 0x0002, +}; +sub get_cxl_cme_threshold_ev_flags_text +{ + my $flags = $_[0]; + my @out; + + if ($flags & CXL_EVT_FLAG_CME_MULTIPLE_MEDIA) { + push @out, (sprintf "\'Corrected Memory Errors in Multiple Media Components\' "); + } + if ($flags & CXL_EVT_FLAG_THRESHOLD_EXCEEDED) { + push @out, (sprintf "\'Exceeded Programmable Threshold\' "); + } + + return join (", ", @out); +} + sub get_cxl_der_mem_event_type { my @types; @@ -1370,11 +1414,12 @@ sub get_cxl_der_mem_event_type return $types[$_[0]]; } +# CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 sub get_cxl_transaction_type { my @types; - if ($_[0] < 0 || $_[0] > 6) { + if ($_[0] < 0 || $_[0] > 8) { return "unknown-type"; } @@ -1384,7 +1429,9 @@ sub get_cxl_transaction_type "Host Scan Media", "Host Inject Poison", "Internal Media Scrub", - "Internal Media Management"); + "Internal Media Management", + "Internal Media Error Check Scrub", + "Media Initialization"); return $types[$_[0]]; } @@ -1453,6 +1500,19 @@ sub get_cxl_media_status return $types[$_[0]]; } +# arg0 - name of the id +# arg1 - id +# arg2 - size(bytes) of id +# arg3 - out log buffer +sub print_cxl_dev_id +{ + $_[3] .= sprintf "%s:", $_[0]; + my @bytes = unpack "C*", $_[1]; + for (my $i = 0; $i < $_[2]; $i++) { + $_[3] .= sprintf "%02x ", $bytes[$i]; + } +} + sub summary { require DBI; @@ -1756,9 +1816,10 @@ sub errors my ($log_type, $first_ts, $last_ts); my ($trace_type, $region, $region_uuid, $hpa, $dpa, $dpa_length, $source, $flags, $overflow_ts); my ($hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $data); - my ($dpa_flags, $descriptor, $mem_event_type, $transaction_type, $channel, $rank, $device, $comp_id); + my ($dpa_flags, $descriptor, $mem_event_type, $mem_event_sub_type, $transaction_type, $channel, $rank, $device, $comp_id, $pldm_entity_id, $pldm_res_id); my ($nibble_mask, $bank_group, $row, $column, $cor_mask); my ($event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status); + my ($sub_type, $cme_threshold_ev_flags, $cme_count); my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); @@ -1974,10 +2035,12 @@ sub errors # CXL general media errors use constant CXL_EVENT_GEN_MED_COMP_ID_SIZE => 0x10; - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, device, comp_id, hpa, region, region_uuid from cxl_general_media_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, device, comp_id, hpa, region, region_uuid, pldm_entity_id, pldm_resource_id, sub_type, cme_threshold_ev_flags, cme_count from cxl_general_media_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $dpa, $dpa_flags, $descriptor, $mem_event_type, $transaction_type, $channel, $rank, $device, $comp_id, $hpa, $region, $region_uuid)); + use constant CXL_EVENT_GEN_PLDM_ENTITY_ID_SIZE => 0x6; + use constant CXL_EVENT_GEN_PLDM_RES_ID_SIZE => 0x4; + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $dpa, $dpa_flags, $descriptor, $mem_event_type, $transaction_type, $channel, $rank, $device, $comp_id, $hpa, $region, $region_uuid, $pldm_entity_id, $pldm_res_id, $sub_type, $cme_threshold_ev_flags, $cme_count)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -1997,20 +2060,25 @@ sub errors $out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags); $out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor); $out .= sprintf "memory event type: %s, ", get_cxl_gmer_mem_event_type($mem_event_type) if (defined $mem_event_type && length $mem_event_type); + $out .= sprintf "memory event sub type: %s, ", get_cxl_mem_event_sub_type($mem_event_sub_type) if (defined $mem_event_sub_type && length $mem_event_sub_type); $out .= sprintf "transaction_type: %s, ", get_cxl_transaction_type($transaction_type) if (defined $transaction_type && length $transaction_type); $out .= sprintf "channel=%u, ", $channel if (defined $channel && length $channel); $out .= sprintf "rank=%u, ", $rank if (defined $rank && length $rank); $out .= sprintf "device=0x%x, ", $device if (defined $device && length $device); if (defined $comp_id && length $comp_id) { - $out .= sprintf "component_id:"; - my @bytes = unpack "C*", $comp_id; - for (my $i = 0; $i < CXL_EVENT_GEN_MED_COMP_ID_SIZE; $i++) { - $out .= sprintf "%02x ", $bytes[$i]; - } + print_cxl_dev_id("component_id", $comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE, $out); } + if (defined $pldm_entity_id && length $pldm_entity_id) { + print_cxl_dev_id("pldm_entity_id", $pldm_entity_id, CXL_EVENT_GEN_PLDM_ENTITY_ID_SIZE, $out); + } + if (defined $pldm_res_id && length $pldm_res_id) { + print_cxl_dev_id("pldm_resource_id", $pldm_res_id, CXL_EVENT_GEN_PLDM_RES_ID_SIZE, $out); + } $out .= sprintf "hpa=0x%llx, ", $hpa if (defined $hpa && length $hpa); $out .= "region=$region, " if (defined $region && length $region); $out .= "region_uuid=$region_uuid, " if (defined $region_uuid && length $region_uuid); + $out .= sprintf "cme_threshold_ev_flags: %s, ", get_cxl_cme_threshold_ev_flags_text($cme_threshold_ev_flags) if (defined $cme_threshold_ev_flags && length $cme_threshold_ev_flags); + $out .= sprintf "cme_count=%u, ", $cme_count if (defined $cme_count && length $cme_count); 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Fri, 10 Jan 2025 13:27:10 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 13/14] rasdaemon: ras-mc-ctl: Update logging of CXL DRAM event data to align with CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:39 +0000 Message-ID: <20250110122641.1668-14-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated with following new fields and new types for Memory Event Type, Transaction Type and Validity Flags fields. 1. Component Identifier 2. Sub-channel 3. Advanced Programmable Corrected Memory Error Threshold Event Flags 4. Corrected Volatile Memory Error Count at Event 5. Memory Event Sub-Type This update modifies ras-mc-ctl to parse and log CXL DRAM event data stored in the RAS SQLite database table, reflecting the specification changes introduced in revision 3.1. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- util/ras-mc-ctl.in | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index fe21f81..86ea48e 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1402,14 +1402,17 @@ sub get_cxl_der_mem_event_type { my @types; - if ($_[0] < 0 || $_[0] > 3) { + if ($_[0] < 0 || $_[0] > 6) { return "unknown-type"; } @types = ("Media ECC Error", "Scrub Media ECC Error", "Invalid Address", - "Data Path Error"); + "Data Path Error", + "TE State Violation", + "Advanced Programmable CME Counter Expiration", + "CKID Violation"); return $types[$_[0]]; } @@ -1819,7 +1822,7 @@ sub errors my ($dpa_flags, $descriptor, $mem_event_type, $mem_event_sub_type, $transaction_type, $channel, $rank, $device, $comp_id, $pldm_entity_id, $pldm_res_id); my ($nibble_mask, $bank_group, $row, $column, $cor_mask); my ($event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status); - my ($sub_type, $cme_threshold_ev_flags, $cme_count); + my ($sub_type, $sub_channel, $cme_threshold_ev_flags, $cme_count, $cvme_count); my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); @@ -2089,10 +2092,10 @@ sub errors # CXL DRAM errors use constant CXL_EVENT_DER_CORRECTION_MASK_SIZE => 0x20; - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, nibble_mask, bank_group, bank, row, column, cor_mask, hpa, region, region_uuid from cxl_dram_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, dpa, dpa_flags, descriptor, type, transaction_type, channel, rank, nibble_mask, bank_group, bank, row, column, cor_mask, hpa, region, region_uuid, comp_id, pldm_entity_id, pldm_resource_id, sub_type, sub_channel, cme_threshold_ev_flags, cvme_count from cxl_dram_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $dpa, $dpa_flags, $descriptor, $type, $transaction_type, $channel, $rank, $nibble_mask, $bank_group, $bank, $row, $column, $cor_mask, $hpa, $region, $region_uuid)); + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $dpa, $dpa_flags, $descriptor, $type, $transaction_type, $channel, $rank, $nibble_mask, $bank_group, $bank, $row, $column, $cor_mask, $hpa, $region, $region_uuid, $comp_id, $pldm_entity_id, $pldm_res_id, $mem_event_sub_type, $sub_channel, $cme_threshold_ev_flags, $cvme_count)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -2112,8 +2115,10 @@ sub errors $out .= sprintf "dpa_flags: %s, ", get_cxl_dpa_flags_text($dpa_flags) if (defined $dpa_flags && length $dpa_flags); $out .= sprintf "descriptor_flags: %s, ", get_cxl_descriptor_flags_text($descriptor) if (defined $descriptor && length $descriptor); $out .= sprintf "memory event type: %s, ", get_cxl_der_mem_event_type($type) if (defined $type && length $type); + $out .= sprintf "memory event sub type: %s, ", get_cxl_mem_event_sub_type($mem_event_sub_type) if (defined $mem_event_sub_type && length $mem_event_sub_type); $out .= sprintf "transaction_type: %s, ", get_cxl_transaction_type($transaction_type) if (defined $transaction_type && length $transaction_type); $out .= sprintf "channel=%u, ", $channel if (defined $channel && length $channel); + $out .= sprintf "sub_channel=%u, ", $sub_channel if (defined $sub_channel && length $sub_channel); $out .= sprintf "rank=%u, ", $rank if (defined $rank && length $rank); $out .= sprintf "nibble_mask=%u, ", $nibble_mask if (defined $nibble_mask && length $nibble_mask); $out .= sprintf "bank_group=%u, ", $bank_group if (defined $bank_group && length $bank_group); @@ -2130,6 +2135,17 @@ sub errors $out .= sprintf "hpa=0x%llx, ", $hpa if (defined $hpa && length $hpa); $out .= "region=$region, " if (defined $region && length $region); $out .= "region_uuid=$region_uuid, " if (defined $region_uuid && length $region_uuid); + if (defined $comp_id && length $comp_id) { + print_cxl_dev_id("component_id", $comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE, $out); + } + if (defined $pldm_entity_id && length $pldm_entity_id) { + print_cxl_dev_id("pldm_entity_id", $pldm_entity_id, CXL_EVENT_GEN_PLDM_ENTITY_ID_SIZE, $out); + } + if (defined $pldm_res_id && length $pldm_res_id) { + print_cxl_dev_id("pldm_resource_id", $pldm_res_id, CXL_EVENT_GEN_PLDM_RES_ID_SIZE, $out); + } + $out .= sprintf "cme_threshold_ev_flags: %s, ", get_cxl_cme_threshold_ev_flags_text($cme_threshold_ev_flags) if (defined $cme_threshold_ev_flags && length $cme_threshold_ev_flags); + $out .= sprintf "cvme_count=%u, ", $cvme_count if (defined $cvme_count && length $cvme_count); $out .= "\n"; } if ($out ne "") { From patchwork Fri Jan 10 12:26:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 13934441 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1809E2101A9; Fri, 10 Jan 2025 12:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512036; cv=none; b=qNuap+3aF01KvL8xm8nyQbx8sJbBOBy0t1kUXJM9D16OElCcoyChxMyoEet7VDjlGz1/+nibUv6sseLHFJsjk62zJGDJQgWy7hmqUaEX0ZPkneb9Er7NHJWvRMuitWVEWT6X2eawDhgsdKNjdB95+lhHMdHwtU1G89gVGJ/r6J8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736512036; c=relaxed/simple; bh=4BFJHDiiUAomO+9PvQSWDRz+Hwc8QpA1zTgZtaR+4Ro=; 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Fri, 10 Jan 2025 13:27:11 +0100 From: To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 14/14] rasdaemon: ras-mc-ctl: Update logging of CXL memory module data to align with CXL spec rev 3.1 Date: Fri, 10 Jan 2025 12:26:40 +0000 Message-ID: <20250110122641.1668-15-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250110122641.1668-1-shiju.jose@huawei.com> References: <20250110122641.1668-1-shiju.jose@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml100001.china.huawei.com (7.191.160.183) To frapeml500007.china.huawei.com (7.182.85.172) From: Shiju Jose CXL spec 3.1 section 8.2.9.2.1.3 Table 8-47, Memory Module Event Record has updated with following new fields and new info for Device Event Type and Device Health Information fields. 1. Validity Flags 2. Component Identifier 3. Device Event Sub-Type This update modifies ras-mc-ctl to parse and log CXL memory module event data stored in the RAS SQLite database table, reflecting the specification changes introduced in revision 3.1. Reviewed-by: Jonathan Cameron Signed-off-by: Shiju Jose --- util/ras-mc-ctl.in | 46 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in index 86ea48e..ba48660 100755 --- a/util/ras-mc-ctl.in +++ b/util/ras-mc-ctl.in @@ -1439,11 +1439,12 @@ sub get_cxl_transaction_type return $types[$_[0]]; } +# CXL rev 3.1 section 8.2.9.2.1.3; Table 8-47 sub get_cxl_dev_event_type { my @types; - if ($_[0] < 0 || $_[0] > 5) { + if ($_[0] < 0 || $_[0] > 8) { return "unknown-type"; } @@ -1452,15 +1453,37 @@ sub get_cxl_dev_event_type "Life Used Change", "Temperature Change", "Data Path Error", - "LSA Error"); + "LSA Error", + "Unrecoverable Internal Sideband Bus Error", + "Memory Media FRU Error", + "Power Management Fault"); return $types[$_[0]]; } +sub get_cxl_dev_event_sub_type +{ + my @types; + + if ($_[0] < 0 || $_[0] > 3) { + return "unknown-type"; + } + + @types = ("Not Reported", + "Invalid Config Data", + "Unsupported Config Data", + "Unsupported Memory Media FRU"); + + return $types[$_[0]]; +} + +#CXL rev 3.1 section 8.2.9.9.3.1; Table 8-133 use constant { CXL_DHI_HS_MAINTENANCE_NEEDED => 0x0001, CXL_DHI_HS_PERFORMANCE_DEGRADED => 0x0002, CXL_DHI_HS_HW_REPLACEMENT_NEEDED => 0x0004, + CXL_DHI_HS_HW_REPLACEMENT_NEEDED => 0x0004, + CXL_DHI_HS_MEM_CAPACITY_DEGRADED => 0x0008, }; sub get_cxl_health_status_text @@ -1477,6 +1500,9 @@ sub get_cxl_health_status_text if ($flags & CXL_DHI_HS_HW_REPLACEMENT_NEEDED) { push @out, (sprintf "\'REPLACEMENT_NEEDED\' "); } + if ($flags & CXL_DHI_HS_MEM_CAPACITY_DEGRADED) { + push @out, (sprintf "\'MEM_CAPACITY_DEGRADED\' "); + } return join (", ", @out); } @@ -1821,7 +1847,7 @@ sub errors my ($hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $data); my ($dpa_flags, $descriptor, $mem_event_type, $mem_event_sub_type, $transaction_type, $channel, $rank, $device, $comp_id, $pldm_entity_id, $pldm_res_id); my ($nibble_mask, $bank_group, $row, $column, $cor_mask); - my ($event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status); + my ($event_type, $event_sub_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status); my ($sub_type, $sub_channel, $cme_threshold_ev_flags, $cme_count, $cvme_count); my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); @@ -2155,10 +2181,10 @@ sub errors } # CXL memory module errors - $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, event_type, health_status, media_status, life_used, dirty_shutdown_cnt, cor_vol_err_cnt, cor_per_err_cnt, device_temp, add_status from cxl_memory_module_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, memdev, host, serial, log_type, hdr_uuid, hdr_flags, hdr_handle, hdr_related_handle, hdr_ts, hdr_length, hdr_maint_op_class, hdr_maint_op_sub_class, event_type, health_status, media_status, life_used, dirty_shutdown_cnt, cor_vol_err_cnt, cor_per_err_cnt, device_temp, add_status, event_sub_type, comp_id, pldm_entity_id, pldm_resource_id from cxl_memory_module_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); - $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status)); + $query_handle->bind_columns(\($id, $timestamp, $memdev, $host, $serial, $log_type, $hdr_uuid, $hdr_flags, $hdr_handle, $hdr_related_handle, $hdr_ts, $hdr_length, $hdr_maint_op_class, $hdr_maint_op_sub_class, $event_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status, $event_sub_type, $comp_id, $pldm_entity_id, $pldm_res_id)); $out = ""; while($query_handle->fetch()) { $out .= "$id $timestamp error: "; @@ -2175,6 +2201,7 @@ sub errors $out .= sprintf "hdr_maint_op_class=%u, ", $hdr_maint_op_class if (defined $hdr_maint_op_class && length $hdr_maint_op_class); $out .= sprintf "hdr_maint_op_sub_class=%u, ", $hdr_maint_op_sub_class if (defined $hdr_maint_op_sub_class && length $hdr_maint_op_sub_class); $out .= sprintf "event_type: %s, ", get_cxl_dev_event_type($event_type) if (defined $event_type && length $event_type); + $out .= sprintf "event_sub_type: %s, ", get_cxl_dev_event_sub_type($event_sub_type) if (defined $event_sub_type && length $event_sub_type); $out .= sprintf "health_status: %s, ", get_cxl_health_status_text($health_status) if (defined $health_status && length $health_status); $out .= sprintf "media_status: %s, ", get_cxl_media_status($media_status) if (defined $media_status && length $media_status); $out .= sprintf "life_used=%u, ", $life_used if (defined $life_used && length $life_used); @@ -2183,6 +2210,15 @@ sub errors $out .= sprintf "cor_per_err_cnt=%u, ", $cor_per_err_cnt if (defined $cor_per_err_cnt && length $cor_per_err_cnt); $out .= sprintf "device_temp=%u, ", $device_temp if (defined $device_temp && length $device_temp); $out .= sprintf "add_status=%u ", $add_status if (defined $add_status && length $add_status); + if (defined $comp_id && length $comp_id) { + print_cxl_dev_id("component_id", $comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE, $out); + } + if (defined $pldm_entity_id && length $pldm_entity_id) { + print_cxl_dev_id("pldm_entity_id", $pldm_entity_id, CXL_EVENT_GEN_PLDM_ENTITY_ID_SIZE, $out); + } + if (defined $pldm_res_id && length $pldm_res_id) { + print_cxl_dev_id("pldm_resource_id", $pldm_res_id, CXL_EVENT_GEN_PLDM_RES_ID_SIZE, $out); + } $out .= "\n"; } if ($out ne "") {