From patchwork Sat Jan 11 16:14:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 13936083 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FE521B3926; Sat, 11 Jan 2025 16:14:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612100; cv=none; b=VMOahrnxU6bBLU3bqHOzNpR75OZvx9ZyimRFVksVI2spu0AYaiBamDjbqTU1v3J5XBxwAhTL8lzqfcHx+/K79W+4shYygI60EtSBPm/infDoJLrnNk+KK8B6acKExsOhD3DPNkqCl0aRHrEnsqPgR16Yaj/xhvtFZXgtJUxgCx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736612100; c=relaxed/simple; bh=QhIR6IVNhDKIGvS9mrCQN+vy8fYDqP+FrI/vAQE6KCM=; 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Sat, 11 Jan 2025 16:14:55 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:14:51 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , Subject: [PATCH V7 1/5] interconnect: core: Add dynamic id allocation support Date: Sat, 11 Jan 2025 16:14:25 +0000 Message-ID: <20250111161429.51-2-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BYiuIdzH9mf4e1M5lIXHM0zQSAyfFAlv X-Proofpoint-GUID: BYiuIdzH9mf4e1M5lIXHM0zQSAyfFAlv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 Current interconnect framework is based on static IDs for creating node and registering with framework. This becomes a limitation for topologies where there are multiple instances of same interconnect provider. Add icc_node_create_alloc_id() API to create icc node with dynamic id, this will help to overcome the dependency on static IDs. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/core.c | 32 +++++++++++++++++++++++++++ include/linux/interconnect-provider.h | 6 +++++ 2 files changed, 38 insertions(+) diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 9d5404a07e8a..0b7093eb51af 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -858,6 +858,38 @@ struct icc_node *icc_node_create(int id) } EXPORT_SYMBOL_GPL(icc_node_create); +/** + * icc_node_create_alloc_id() - create node and dynamically allocate id + * @start_id: min id to be allocated + * + * Return: icc_node pointer on success, or ERR_PTR() on error + */ +struct icc_node *icc_node_create_alloc_id(int start_id) +{ + struct icc_node *node; + int id; + + mutex_lock(&icc_lock); + + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return ERR_PTR(-ENOMEM); + + id = idr_alloc(&icc_idr, node, start_id, 0, GFP_KERNEL); + if (id < 0) { + WARN(1, "%s: couldn't get idr\n", __func__); + kfree(node); + node = ERR_PTR(id); + goto out; + } + node->id = id; +out: + mutex_unlock(&icc_lock); + + return node; +} +EXPORT_SYMBOL_GPL(icc_node_create_alloc_id); + /** * icc_node_destroy() - destroy a node * @id: node id diff --git a/include/linux/interconnect-provider.h b/include/linux/interconnect-provider.h index f5aef8784692..4fc7a5884374 100644 --- a/include/linux/interconnect-provider.h +++ b/include/linux/interconnect-provider.h @@ -117,6 +117,7 @@ struct icc_node { int icc_std_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); struct icc_node *icc_node_create(int id); +struct icc_node *icc_node_create_alloc_id(int start_id); void icc_node_destroy(int id); int icc_link_create(struct icc_node *node, const int dst_id); void icc_node_add(struct icc_node *node, struct icc_provider *provider); @@ -141,6 +142,11 @@ static inline struct icc_node *icc_node_create(int id) return ERR_PTR(-ENOTSUPP); } +static inline struct icc_node *icc_node_create_alloc_id(int start_id) +{ + return ERR_PTR(-EOPNOTSUPP); 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Sat, 11 Jan 2025 16:14:59 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:14:55 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , Subject: [PATCH V7 2/5] interconnect: qcom: Add multidev EPSS L3 support Date: Sat, 11 Jan 2025 16:14:26 +0000 Message-ID: <20250111161429.51-3-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AYXkRSNb30QssqBuiVC23hoKYxfdcbtC X-Proofpoint-ORIG-GUID: AYXkRSNb30QssqBuiVC23hoKYxfdcbtC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 EPSS on SA8775P has two instances which requires creation of two device nodes with different compatible and device data because of unique icc node id and name limitation in interconnect framework. Add multidevice support to osm-l3 code to get unique node id from icc framework. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 91 ++++++++++++++++++++++-------- 1 file changed, 67 insertions(+), 24 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 6a656ed44d49..8e98d1c9a840 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -11,6 +12,7 @@ #include #include #include +#include #include #include @@ -34,6 +36,9 @@ #define OSM_L3_MAX_LINKS 1 +#define OSM_L3_NODE_ID_START 10000 +#define OSM_NODE_NAME_SUFFIX_SIZE 10 + #define to_osm_l3_provider(_provider) \ container_of(_provider, struct qcom_osm_l3_icc_provider, provider) @@ -55,46 +60,40 @@ struct qcom_osm_l3_icc_provider { */ struct qcom_osm_l3_node { const char *name; - u16 links[OSM_L3_MAX_LINKS]; + const char *links[OSM_L3_MAX_LINKS]; u16 id; u16 num_links; u16 buswidth; }; struct qcom_osm_l3_desc { - const struct qcom_osm_l3_node * const *nodes; + struct qcom_osm_l3_node * const *nodes; size_t num_nodes; unsigned int lut_row_size; unsigned int reg_freq_lut; unsigned int reg_perf_state; }; -enum { - OSM_L3_MASTER_NODE = 10000, - OSM_L3_SLAVE_NODE, -}; - -#define DEFINE_QNODE(_name, _id, _buswidth, ...) \ - static const struct qcom_osm_l3_node _name = { \ +#define DEFINE_QNODE(_name, _buswidth, ...) \ + static struct qcom_osm_l3_node _name = { \ .name = #_name, \ - .id = _id, \ .buswidth = _buswidth, \ .num_links = COUNT_ARGS(__VA_ARGS__), \ - .links = { __VA_ARGS__ }, \ + __VA_OPT__(.links = { #__VA_ARGS__ }) \ } -DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16); +DEFINE_QNODE(osm_l3_master, 16, osm_l3_slave); +DEFINE_QNODE(osm_l3_slave, 16); -static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { +static struct qcom_osm_l3_node * const osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &osm_l3_master, [SLAVE_OSM_L3] = &osm_l3_slave, }; -DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32); +DEFINE_QNODE(epss_l3_master, 32, epss_l3_slave); +DEFINE_QNODE(epss_l3_slave, 32); -static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { +static struct qcom_osm_l3_node * const epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &epss_l3_master, [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; @@ -123,6 +122,19 @@ static const struct qcom_osm_l3_desc epss_l3_l3_vote = { .reg_perf_state = EPSS_REG_L3_VOTE, }; +static u16 get_node_id_by_name(const char *node_name, + const struct qcom_osm_l3_desc *desc) +{ + struct qcom_osm_l3_node *const *nodes = desc->nodes; + int i; + + for (i = 0; i < desc->num_nodes; i++) { + if (!strcmp(nodes[i]->name, node_name)) + return nodes[i]->id; + } + return 0; +} + static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -164,10 +176,11 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) const struct qcom_osm_l3_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - const struct qcom_osm_l3_node * const *qnodes; + struct qcom_osm_l3_node * const *qnodes; struct icc_node *node; size_t num_nodes; struct clk *clk; + u64 addr; int ret; clk = clk_get(&pdev->dev, "xo"); @@ -188,6 +201,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) if (!qp) return -ENOMEM; + ret = of_property_read_reg(pdev->dev.of_node, 0, &addr, NULL); + if (ret) + return ret; + qp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(qp->base)) return PTR_ERR(qp->base); @@ -242,26 +259,51 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) icc_provider_init(provider); + /* create icc nodes */ for (i = 0; i < num_nodes; i++) { - size_t j; + char *node_name; + size_t len; - node = icc_node_create(qnodes[i]->id); + node = icc_node_create_alloc_id(OSM_L3_NODE_ID_START); if (IS_ERR(node)) { ret = PTR_ERR(node); goto err; } + qnodes[i]->id = node->id; + + /* len = strlen(node->name) + @ + 8 (base-address) + NULL */ + len = strlen(qnodes[i]->name) + OSM_NODE_NAME_SUFFIX_SIZE; + node_name = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!node_name) { + ret = -ENOMEM; + goto err; + } + + snprintf(node_name, len, "%s@%08llx", qnodes[i]->name, addr); + node->name = node_name; - node->name = qnodes[i]->name; /* Cast away const and add it back in qcom_osm_l3_set() */ node->data = (void *)qnodes[i]; icc_node_add(node, provider); - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - data->nodes[i] = node; } + /* create links in topolgy */ + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = data->nodes[i]; + for (j = 0; j < qnodes[i]->num_links; j++) { + u16 link_node_id = get_node_id_by_name(qnodes[i]->links[j], desc); + + if (link_node_id) + icc_link_create(node, link_node_id); + else + goto err; + } + } + ret = icc_provider_register(provider); if (ret) goto err; @@ -284,6 +326,7 @@ static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, + { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match); From patchwork Sat Jan 11 16:14:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 13936085 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 919561B2184; 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Signed-off-by: Raviteja Laggyshetty --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 21dae0b92819..94f7f283787a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm6375-cpucp-l3 - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 + - qcom,sa8775p-epss-l3 - const: qcom,epss-l3 reg: From patchwork Sat Jan 11 16:14:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 13936086 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F16991B4F0A; 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Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 368bcf7c9802..c6a889d4ddaf 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; 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Sat, 11 Jan 2025 16:15:12 GMT Received: from 4206f847eb12.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 11 Jan 2025 08:15:08 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Odelu Kukatla , "Mike Tipton" , Vivek Aknurwar CC: Sibi Sankar , , , , , Shivnandan Kumar Subject: [PATCH V7 5/5] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Date: Sat, 11 Jan 2025 16:14:29 +0000 Message-ID: <20250111161429.51-6-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250111161429.51-1-quic_rlaggysh@quicinc.com> References: <20250111161429.51-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gNG2wkyMQFomrz_UZBN_3YaO8rWBwYzK X-Proofpoint-ORIG-GUID: gNG2wkyMQFomrz_UZBN_3YaO8rWBwYzK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501110138 From: Jagadeesh Kona Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. If a single OPP table is used for both CPU domains, then _allocate_opp_table() won't be invoked for CPU4 but instead CPU4 will be added as device under the CPU0 OPP table. Due to this, dev_pm_opp_of_find_icc_paths() won't be invoked for CPU4 device and hence CPU4 won't be able to independently scale it's interconnects. Both CPU0 and CPU4 devices will scale the same ICC path which can lead to one device overwriting the BW vote placed by other device. Hence CPU0 and CPU4 require separate OPP tables to allow independent scaling of DDR and L3 frequencies for each CPU domain, with the final DDR and L3 frequencies being an aggregate of both. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Signed-off-by: Jagadeesh Kona Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 210 ++++++++++++++++++++++++++ 1 file changed, 210 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index c6a889d4ddaf..7c52bca958fe 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -49,6 +49,11 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -71,6 +76,11 @@ cpu1: cpu@100 { next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -88,6 +98,11 @@ cpu2: cpu@200 { next-level-cache = <&l2_2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -105,6 +120,11 @@ cpu3: cpu@300 { next-level-cache = <&l2_3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -122,6 +142,11 @@ cpu4: cpu@10000 { next-level-cache = <&l2_4>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -145,6 +170,11 @@ cpu5: cpu@10100 { next-level-cache = <&l2_5>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -162,6 +192,11 @@ cpu6: cpu@10200 { next-level-cache = <&l2_6>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -179,6 +214,11 @@ cpu7: cpu@10300 { next-level-cache = <&l2_7>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible = "cache"; cache-level = <2>; @@ -268,6 +308,176 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 { }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_1267mhz: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1363mhz: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1459mhz: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1536mhz: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1632mhz: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1785mhz: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1939mhz: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2188mhz: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2265mhz: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2361mhz: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu0_opp_2457mhz: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu0_opp_2553mhz: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <12787200 54681600>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp_1267mhz: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1363mhz: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1459mhz: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1536mhz: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1632mhz: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1785mhz: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1939mhz: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2188mhz: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2265mhz: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2361mhz: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu4_opp_2457mhz: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu4_opp_2553mhz: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <12787200 54681600>; + }; + }; + dummy-sink { compatible = "arm,coresight-dummy-sink";