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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:20 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 01/13] hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriate Date: Sat, 11 Jan 2025 19:36:59 +0100 Message-ID: <20250111183711.2338-2-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and "DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. QEMU currently misses to set the DMA bit which causes the driver to loop forever. Fix that by setting the DMA bit if enabled when doing DMA block transfers. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow --- hw/sd/sdhci.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 299cd4bc1b..a958c11497 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -665,12 +665,13 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) } } + if (s->norintstsen & SDHC_NISEN_DMA) { + s->norintsts |= SDHC_NIS_DMA; + } + if (s->blkcnt == 0) { sdhci_end_transfer(s); } else { - if (s->norintstsen & SDHC_NISEN_DMA) { - s->norintsts |= SDHC_NIS_DMA; - } sdhci_update_irq(s); } } @@ -691,6 +692,10 @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s) } s->blkcnt--; + if (s->norintstsen & SDHC_NISEN_DMA) { + s->norintsts |= SDHC_NIS_DMA; + } + sdhci_end_transfer(s); } From patchwork Sat Jan 11 18:37:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13936116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BD89E7719E for ; Sat, 11 Jan 2025 18:38:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWgMS-00071b-Lx; Sat, 11 Jan 2025 13:37:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWgMQ-00070R-T4; Sat, 11 Jan 2025 13:37:26 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWgMP-0003u5-Fn; Sat, 11 Jan 2025 13:37:26 -0500 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-5d3d479b1e6so4130882a12.2; Sat, 11 Jan 2025 10:37:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1736620642; x=1737225442; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jKrZnbsTuw0Y/FLcZknSpoAChzMgNZQkW7pMKPGttDo=; b=TQx3MvZaL+ntt0w+f2aXwBycSKZshhAnCmrqvlhFfEvZHYlZ22xDwgZFxlt9e0pqv9 1wQoLpBSpU1HWHDGmnYl8/Cop7bKhxkNbig5WwfhCn3Kg4oTrACF7V0MDcKnnkeucJwT kUhKZdxHizQTT7Pn6E/AZHaLoK5bew/UsZb3/0BRDCWKXshsLoPqy70bym5cfkWN21xi DXw4wjJLM1pSXfz8VX9r9yXxmwQ8px1FV+iafweZmJt5KxjQDTCHBdhHkKsZSZekMjoU urI7nwYRg1sK82YK2yPlpDu8vq2pWg98a+Ry5BUHeCcJ0Cbq6v5W3bYbiDrRrVPPIJ4t 1cvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736620642; x=1737225442; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jKrZnbsTuw0Y/FLcZknSpoAChzMgNZQkW7pMKPGttDo=; b=CNWvGXn/hY+ELKZRkruMvFcKE4edDemxiAYeAVflUkTMy/csVSa11zOl/R737VvX1U QY7TI+Ik5BOlLbd2L3CBQoM6wVklpfkjpkQGhdbF9vbXcDFUMbwIcWERERJ9Fj/WcMIZ vu97qwRj1xupwTNJ/GQ/yw00vNApCHnojucdF5wMDq7+cClBlUILVpu0WbAVQJDZ3nTl ARXEnM7vkAtOV56nQt+onb8wQ2nXmdCeKY7AWWY+iRpQnFwx9teufR1B2muup6BzCqsJ LA3+O3aoIrGLfK6fQ4HP6KsN6NfkkAEEcyP5HCHgKLqUSIF116ACQinKTplLBmUB6R2o mU5Q== X-Forwarded-Encrypted: i=1; AJvYcCU5mTn/By8YRUMJRqjVjP1SenaPib0V0a0BRtKAZB4am9oRSMk9NH1/WPsufscfUuYnMAo2gnpKaQ==@nongnu.org, AJvYcCXnKRmcIj8oD4j8HI6PQuviOmvlVR09ybIGcA4IR51jbzVMZ8fNJPDyyt6RKJnM5ahLJyrO3rSJEaYWrQ==@nongnu.org X-Gm-Message-State: AOJu0Yzbl5HyAhSVXE6CfMZxYiStQ86Zpvvj7JOvZta+TcmmwnqW0ZKq EgCRVtd46sqgd7z8Y6n6iV2R+vpEJWu9pRvtNZhEg0MrJtkX7G+cejaP3w== X-Gm-Gg: ASbGnctFZ/aqm1pmtMtxL6/3ojFdDcaIQPRcSh+c/+wi4d0o1Sf9g8unirAsPn+PtLL ZuYVm1fW7xffXjRmj5wD2gTSLx7ng0yPUTmY621c1+9+mLNq7meZTz3Sq9dRQPb3kS2wecZbGOX UFgW6QQWEwd2qJWh//Z+I/KW4v/N1pA6ItH0p0ERZ98a63W8ic9ZuGC0vS+VbaxELb+J7RadKiM ah3ASKgZ9GtcwgSZ8tIHNBl2NNhbmYilN1QCh5Mj64/4AHLBrmqtEpcWcV9s7uXK3uyedV3/G3q 0erwztBNaRUDGLnEwsNHcQPcEW1tuF1R5VVv53/TOIA= X-Google-Smtp-Source: AGHT+IHtWrLyQ+lfnYOjHykEJCbpjYc80pqn0wfgoTDYl8TgoY+HZR5gIDBKFNUCKc/mFmDZjaUwCQ== X-Received: by 2002:a05:6402:5194:b0:5d0:fb56:3f with SMTP id 4fb4d7f45d1cf-5d972e0e341mr34989711a12.12.1736620642049; Sat, 11 Jan 2025 10:37:22 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-101-099.78.54.pool.telefonica.de. [78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:21 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 02/13] hw/char/imx_serial: Fix reset value of UFCR register Date: Sat, 11 Jan 2025 19:37:00 +0100 Message-ID: <20250111183711.2338-3-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The value of the UCFR register is respected when echoing characters to the terminal, but its reset value is reserved. Fix the reset value to the one documented in the datasheet. While at it move the related attribute out of the section of unimplemented registers since its value is actually respected. Signed-off-by: Bernhard Beschow --- include/hw/char/imx_serial.h | 2 +- hw/char/imx_serial.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index 65f0e97c76..90ba3ff18c 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -109,13 +109,13 @@ struct IMXSerialState { uint32_t ucr1; uint32_t ucr2; uint32_t uts1; + uint32_t ufcr; /* * The registers below are implemented just so that the * guest OS sees what it has written */ uint32_t onems; - uint32_t ufcr; uint32_t ubmr; uint32_t ubrc; uint32_t ucr3; diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 12705a1337..f805da23ff 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -159,6 +159,7 @@ static void imx_serial_reset(IMXSerialState *s) s->ucr3 = 0x700; s->ubmr = 0; s->ubrc = 4; + s->ufcr = BIT(11) | BIT(0); fifo32_reset(&s->rx_fifo); timer_del(&s->ageing_timer); From patchwork Sat Jan 11 18:37:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13936114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 717E8E7719A for ; Sat, 11 Jan 2025 18:38:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWgMU-000733-AX; Sat, 11 Jan 2025 13:37:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWgMS-000713-7n; Sat, 11 Jan 2025 13:37:28 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWgMQ-0003uH-R1; Sat, 11 Jan 2025 13:37:27 -0500 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-aa6a92f863cso592340566b.1; Sat, 11 Jan 2025 10:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1736620644; x=1737225444; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0PqxDnBjevTT4lcWrIDnfXMGDt0Ne6U2zvgq/38zAcs=; b=bct1y9rZGKD2nbX2nL8QvscPDpf+dL9dVsV6OcRMSBz1mO0/qIeheyvd6Q8NoUPrli 9nIo6I8yBX93JryBByTD+v0uUbUNtudwigx+b2vyzsqQC/lKSrJRg/ux7FgOwITiakTh xpzMyCzrzwWXmhWVj2WbC5COBg17WMFOtI1suzVdugpTKNwVrWUgH69Y0sQWyAzhw/dr 8e016uioHKP4vtVTLH0spHNLJbipzttgM6H51OEFCAXuQyToqp7tfRCHxshvh694IWVd /ygmVRWvMAB5SfYKpK4rNaAyKIlNQ+fjUFiaWb3KE52gKU/POmQ+FBeMqCDwyte87Il/ KKvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736620644; x=1737225444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0PqxDnBjevTT4lcWrIDnfXMGDt0Ne6U2zvgq/38zAcs=; b=mEHWPZZgvQb2H/SZjXN9+9rlY7pxsd2GFZg8rz+qq7Gd7xoTtueR0kIanu2cTSwIVE epcA1qrUa6vZpAOCRCF0SxoqUFGhXrXA67Wj7WsTAFMs3yxZMorBZIYwJfuqp/eap5Nu bZBFcrdORiUTpxBnPK07v6FoKzNqAVFj4GsXiTbB+ZCW2tqJ0UM4KlBmHA/Uz1cNbiAB 3A4UEJNIN90EUu3U5NNT85cmHoPqEMbWpWxMtSNZn2uQsObTXRSQUuOUsb7QgNbOigVK IUfJPOkR/RpIL5Hw6noTRZvm8jRhV8ooS3tjeulKNr/Xp50GWb9x/Wf5tk1+l6f5Z9pw DjGg== X-Forwarded-Encrypted: i=1; AJvYcCX8scoBbj8F+lwXctejTUlbLdQW/dTog+k89MBMsO2t7rjvoPMQeQIw7fbT3lflriVqbtUjua7wpg==@nongnu.org, AJvYcCXAJGCisDJL99uqyO1FFprdhLEnk6pzapiSNYJJxCr4XfWyfraUqT1mzhysehEsywC/4JxJazPgw9uupw==@nongnu.org X-Gm-Message-State: AOJu0YzHMaaVncs6uqEAx8TI9Bl/WK43XnhjhdbcB9An+9BdQFdbcxTb E9Ah3asdVMFsltqUWDh0wMaORlyg1PfO0SSI9uPGgEol2BquBHFBX4UzyA== X-Gm-Gg: ASbGncvj+GC35E2MU3yM2IuUY2u5y/08g7GGCxWOuW1I0i7814y7AGC5b8ao75Z9ARx PONGxM3EqcbOAmslH0KhwkTMnnCOu88XR+mnP6jWzlW51gUc6vvzbe+Mq4UXZXaSmAiZiRl0K0B MfdcyEovZCU+qGb+AVwT4wqWBxBdhr+k8tTxRaRijSTPcj0sgyE1ACLWxqpKryjbFoQjDcuo8/Y dBGZRe8lnMJeNJPdvH2oqFRv50kFIsRGeQcTwXpxEu8858K/zOaJZqThBj32N9g1eCwfXD/yBKz MghtSd7dgDJBtVVfaipMtjxTQGaEz2exsd8dpAEIpaI= X-Google-Smtp-Source: AGHT+IGu+ZJNKOi4dbgTGRgsIs4Ojn44voEJH4WzHk62IEeSXhlJzu0ebrp/NS+05OVlSHx4Jt4H9A== X-Received: by 2002:a17:907:1c21:b0:aab:d8df:9bbb with SMTP id a640c23a62f3a-ab2abc925cbmr1429988466b.41.1736620643942; Sat, 11 Jan 2025 10:37:23 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-101-099.78.54.pool.telefonica.de. [78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:22 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 03/13] hw/char/imx_serial: Update all state before restarting ageing timer Date: Sat, 11 Jan 2025 19:37:01 +0100 Message-ID: <20250111183711.2338-4-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fixes characters to be "echoed" after each keystroke rather than after every other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY only after every other keystroke. Signed-off-by: Bernhard Beschow --- hw/char/imx_serial.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index f805da23ff..be06f39a4d 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -381,14 +381,14 @@ static void imx_put_data(void *opaque, uint32_t value) if (fifo32_num_used(&s->rx_fifo) >= rxtl) { s->usr1 |= USR1_RRDY; } - - imx_serial_rx_fifo_ageing_timer_restart(s); - s->usr2 |= USR2_RDR; s->uts1 &= ~UTS1_RXEMPTY; if (value & URXD_BRK) { s->usr2 |= USR2_BRCD; } + + imx_serial_rx_fifo_ageing_timer_restart(s); + imx_update(s); } From patchwork Sat Jan 11 18:37:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13936126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 084EBE7719A for ; Sat, 11 Jan 2025 18:40:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWgMV-00073N-6d; Sat, 11 Jan 2025 13:37:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWgMT-00072h-QT; Sat, 11 Jan 2025 13:37:29 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWgMR-0003ua-PE; Sat, 11 Jan 2025 13:37:29 -0500 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-aaf0f1adef8so634680766b.3; Sat, 11 Jan 2025 10:37:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1736620645; x=1737225445; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lLQk74MqOI0tELXFza1L8vMcugJxwMU6tidXaRRoSsk=; b=I2tRI93eaamDQ66hta4vLk/WyDgD59CqB57yiZ9BfYdRKI27RIeloqR2e78We+z5ai IUnjhniXsxlrSf+EzgdjYXIqLK69ZX25kQSxP0KZb9ntgFFQgZ4d8IVXQaLD/cz/eSpc VGax6EbBEvkgiCgJqYw+Ot5OsjInYIhgjZxrNfiKs3nU9/6dm96o5LqRHpCCrM9Ue8O7 qDtF7v7SCJ7Nrib7SHnHk7XcuByw3IGhI71jOW+PI7Ug8pzv9pcbCDa0n77cqxKTve1V CbJKgSJ7F/hw22DMsVuaESle2FaX7BKP0K7mueW9R159gnV28rQnWHAdIq9oF9GAiRQZ TAKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736620645; x=1737225445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lLQk74MqOI0tELXFza1L8vMcugJxwMU6tidXaRRoSsk=; b=xFtssOPTH1ExlDxB85dP8rqvFjilV0S0GscL1lzIeGKqUJjedZ3bWErN2PWN8Y94aS zKVI7LFNq8gN7Wq+f/C+1eMFJ0eBv1P8b+DYAZrqBsjyz77lpxdYmoPZUWdCB+yQ7TuB jJnWdAL0ZKXzkXsIcTZmPlmh5jI8+jPhCM6HCP46R1wfNmvnW5Yf2fadlqSn04ZNLOrZ EjmkCKzKdAPPlPMNbHNekFi4vdoNqdOGpxbvKl78UAiPC/GNbGSvGaHjP4kxVE6elm/C OLuIVsQeqFlHUK3lUgi8dn0crLnBUJS43UXZQvctfgvtxccGGzs8izescRV+TUM8uhQU p8AA== X-Forwarded-Encrypted: i=1; AJvYcCUBqTjruUDb8Ohs4nBVThEECf/hY8vOJChQb6JzXYK0hYsd23ImiE75gLM6yyJzMxgWvyHzqIREGhIeCg==@nongnu.org, AJvYcCVwoenwyPg5Xmdz4685j92teMjqMCMLudmRmUHt1M6/RkDR8bAUj8hpiCEhhKXQrjhWcDQrXVN48g==@nongnu.org X-Gm-Message-State: AOJu0YzgQCaz3aDTPDROFgXsBqNepDEN97ReJ60iaPe5Qjv99wkA8ukb W+dkL2ViRVlG+4//zMHAhER/+Whk8n026ZAmZ3I67p53ZkydExEmlqA+2A== X-Gm-Gg: ASbGncu2AxfdwD2Y4GoezuklQn+kqXzUReEGJ4LwHSJYwLBw12mvq7dvrxYVKreQ5fx eeQTGkvAFDFmPVHMm8egBOUEfhIzMx1t5Uakuuxr14bi9fkfuI7yf4LQQUmfvow8F0ztgfaATib l4+14YPmRW3s60U7zud2UHBOWJwaj7UDAabrBZIeN/R/i+DgSQflAqsIH4Ji3vcc11jCkc/g1ss KEo5//goBc8mWttVfGEjRcD4shr1Ylyiwhwkjsnd1eR2PORohXuGuCRfHDzVilCubcXeJ6ubMgt vqgkauB3Vr0RSX/ntlFOjxCa7kCzy8AjgPOSlyXKp7A= X-Google-Smtp-Source: AGHT+IFLHGj1mGSs40UUqiB20iy6Bxbzql+PqU0cGT/QSq/7Xil6RSXUNvi6ydoB1Vdj6ZBcJPBhRw== X-Received: by 2002:a17:907:94d3:b0:aa6:93c4:c68f with SMTP id a640c23a62f3a-ab2ab703fe3mr1299916366b.21.1736620645138; Sat, 11 Jan 2025 10:37:25 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-101-099.78.54.pool.telefonica.de. [78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:24 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 04/13] hw/pci-host/designware: Expose MSI IRQ Date: Sat, 11 Jan 2025 19:37:02 +0100 Message-ID: <20250111183711.2338-5-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share the MSI IRQ with the INTx lines, so expose it as a dedicated pin. Signed-off-by: Bernhard Beschow --- include/hw/arm/fsl-imx6.h | 4 +++- include/hw/arm/fsl-imx7.h | 4 +++- include/hw/pci-host/designware.h | 1 + hw/arm/fsl-imx6.c | 13 ++++++++++++- hw/arm/fsl-imx7.c | 13 ++++++++++++- hw/pci-host/designware.c | 7 +++---- hw/arm/Kconfig | 2 ++ 7 files changed, 36 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 61c593ffd2..9da32fc189 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -33,6 +33,7 @@ #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "hw/pci-host/designware.h" +#include "hw/or-irq.h" #include "exec/memory.h" #include "cpu.h" #include "qom/object.h" @@ -73,6 +74,7 @@ struct FslIMX6State { ChipideaState usb[FSL_IMX6_NUM_USBS]; IMXFECState eth; DesignwarePCIEHost pcie; + OrIRQState pcie4_msi_irq; MemoryRegion rom; MemoryRegion caam; MemoryRegion ocram; @@ -457,7 +459,7 @@ struct FslIMX6State { #define FSL_IMX6_PCIE1_IRQ 120 #define FSL_IMX6_PCIE2_IRQ 121 #define FSL_IMX6_PCIE3_IRQ 122 -#define FSL_IMX6_PCIE4_IRQ 123 +#define FSL_IMX6_PCIE4_MSI_IRQ 123 #define FSL_IMX6_DCIC1_IRQ 124 #define FSL_IMX6_DCIC2_IRQ 125 #define FSL_IMX6_MLB150_HIGH_IRQ 126 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 411fa1c2e3..aa7818c499 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -36,6 +36,7 @@ #include "hw/net/imx_fec.h" #include "hw/pci-host/designware.h" #include "hw/usb/chipidea.h" +#include "hw/or-irq.h" #include "cpu.h" #include "qom/object.h" #include "qemu/units.h" @@ -85,6 +86,7 @@ struct FslIMX7State { IMX7GPRState gpr; ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; + OrIRQState pcie4_msi_irq; MemoryRegion rom; MemoryRegion caam; MemoryRegion ocram; @@ -428,7 +430,7 @@ enum FslIMX7IRQs { FSL_IMX7_PCI_INTA_IRQ = 125, FSL_IMX7_PCI_INTB_IRQ = 124, FSL_IMX7_PCI_INTC_IRQ = 123, - FSL_IMX7_PCI_INTD_IRQ = 122, + FSL_IMX7_PCI_INTD_MSI_IRQ = 122, FSL_IMX7_UART7_IRQ = 126, diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index c484e377a8..bf8b278978 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -86,6 +86,7 @@ struct DesignwarePCIEHost { MemoryRegion io; qemu_irq irqs[4]; + qemu_irq msi; } pci; MemoryRegion mmio; diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index ac8c66e242..88b9ccff49 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -106,6 +106,8 @@ static void fsl_imx6_init(Object *obj) object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); + object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq, + TYPE_OR_IRQ); } static void fsl_imx6_realize(DeviceState *dev, Error **errp) @@ -435,14 +437,23 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR); + object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2, + &error_abort); + qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort); + + irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ); + qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); + irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ); + irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); + irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); /* * PCIe PHY diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 05e3389fbe..004bf49937 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -150,6 +150,8 @@ static void fsl_imx7_init(Object *obj) * PCIE */ object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); + object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq, + TYPE_OR_IRQ); /* * USBs @@ -597,14 +599,23 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); + object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2, + &error_abort); + qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort); + + irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ); + qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); + irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); + irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); + irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); /* * USBs diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index c3fc37b904..3e8c36e6a7 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -55,8 +55,6 @@ #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C -#define DESIGNWARE_PCIE_IRQ_MSI 3 - static DesignwarePCIEHost * designware_pcie_root_to_host(DesignwarePCIERoot *root) { @@ -90,7 +88,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { - qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); + qemu_set_irq(host->pci.msi, 1); } } @@ -335,7 +333,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, case DESIGNWARE_PCIE_MSI_INTR0_STATUS: root->msi.intr[0].status ^= val; if (!root->msi.intr[0].status) { - qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0); + qemu_set_irq(host->pci.msi, 0); } break; @@ -680,6 +678,7 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { sysbus_init_irq(sbd, &s->pci.irqs[i]); } + sysbus_init_irq(sbd, &s->pci.msi); memory_region_init_io(&s->mmio, OBJECT(s), diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e779b5af95..256013ca80 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -516,6 +516,7 @@ config FSL_IMX6 select PL310 # cache controller select PCI_EXPRESS_DESIGNWARE select SDHCI + select OR_IRQ config ASPEED_SOC bool @@ -573,6 +574,7 @@ config FSL_IMX7 select WDT_IMX2 select PCI_EXPRESS_DESIGNWARE select SDHCI + select OR_IRQ select UNIMP config ARM_SMMUV3 From patchwork Sat Jan 11 18:37:03 2025 Content-Type: text/plain; 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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:25 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 05/13] hw/gpio/imx_gpio: Don't clear input GPIO values upon reset Date: Sat, 11 Jan 2025 19:37:03 +0100 Message-ID: <20250111183711.2338-6-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Input GPIO values such as a present SD card may get notified before the GPIO controller itself gets reset. Claring the input values thus loses data. Assuming that input GPIO events are only fired when the state changes, the input values shouldn't be reset. Signed-off-by: Bernhard Beschow --- hw/gpio/imx_gpio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c index 898f80f8c8..67c47a7280 100644 --- a/hw/gpio/imx_gpio.c +++ b/hw/gpio/imx_gpio.c @@ -302,7 +302,6 @@ static void imx_gpio_reset(DeviceState *dev) s->dr = 0; s->gdir = 0; - s->psr = 0; s->icr = 0; s->imr = 0; s->isr = 0; From patchwork Sat Jan 11 18:37:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13936117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AED56E7719A for ; Sat, 11 Jan 2025 18:38:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWgMY-00077d-T6; Sat, 11 Jan 2025 13:37:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWgMV-00073c-Ns; Sat, 11 Jan 2025 13:37:31 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWgMU-0003vD-5e; Sat, 11 Jan 2025 13:37:31 -0500 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-aaeecbb7309so568967166b.0; Sat, 11 Jan 2025 10:37:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1736620648; x=1737225448; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vwaUYglCz5HiwshtDxMwHXFy/Vt9VTZk7BnhuaVWzvw=; b=SuPuejRkb7fDDFdM/moA3irk6BRSLKbjABuONAm/wiAIPh0n5x5a1kSJVVFCHYtGKi ML2hk8CT2UCPEj8p6RuTxP/h29ut4u27DF1iBCUuDBlhtD4aHtvNI26Yn4iQlAhyTQuO TiYWkPzeE7gqbLpOg6D93MAc4UArH2g/uAXgM90lH7lG2hRIqgxToJjZfgH5YbFPgPUO VeyOJxyAPNUrJM8AcQiABQ4O438Mz4TTbpqc208KebXsFxYieiKaGOKPZt/1NFWvXAmC t/3ZOi/UIXi/Zz0ClhNuEuLdphdNYTyFWUNfJlVwfuCXUnZme7Yxq7VA10FiXZq0XYeD 2WsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736620648; x=1737225448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vwaUYglCz5HiwshtDxMwHXFy/Vt9VTZk7BnhuaVWzvw=; b=MW3UCqPgmkl2ial6U/M4Yx13FgBNzNgLs6+iX8ZmQuJNN3WU8mM3oywNq+/Wkygb8M jUqGygX35nTVMo9Vc2FlNToeZZS+LMAxZWYG+eZyHrAhmsCrGSWHMYTmIi1esjPGZoQV 0z9A8MzmN4h6vSXgsdZ5U/zrL2oyq8xvth+TOtZsZZ8t2r3dxLEggYMph/MxP7XsrLJq lL6kMdQL40pl0RqTVMBg29VCmR5NNKHjMpFDw+VcFI9hAJLHsZScDDQoijZ34XXZ0Ph5 BXvD9ZNdX/TpSmQ54dpzsXi3m+l+K1iDNuXd1MWFPjbQtGYzh+lB3tKazReoIdk7xkbI z/gA== X-Forwarded-Encrypted: i=1; AJvYcCVhSR9zuRDxZigCsKH8rim1UrvKXJTmc3xOy52JgZA6C6IXHEBvK4ruI5uKtsuzARN0hKtc80fS2w==@nongnu.org, AJvYcCXvUFjSPNQBxHoKJi76LZEowhFjCEsBN/80QuA894e+jLoOIw/z1XeA3KCvrhczrF+giZCSD4CtDArvqw==@nongnu.org X-Gm-Message-State: AOJu0YwTjqc164HoWh0eTHrZJ4q5e0FE48ouo+PH7FmaBKxdvUB7yYr2 eM9ODGXi754tEdsxLKzbqOpgRBPHF5kTstDXWq9JNea/x3h7Ht27YIFb/Q== X-Gm-Gg: ASbGncvrlGvbB+kHO9za4b3PFmpaQ6k2l6yMIzFpxdozA8i+k/iQHZJZ0UYA9g79LWs YwvREkHTkbs6jI7P2qlHsXs0irmS6fFEeN1fu8toOYrj5tOEUVM0j3qF6lEx90RBBifn0a6F8tT 9bJeakdmihRkxNDYks5s3siNkISxdOvfzLhJI2yxEJ8iZplHADl+H4UyXfKZr1yJQaSTeRWhVS2 JuSCrcYUk196hNnO/CVO/3SWyyA+DsaaJxQ4VsBwlEIqr1R15pk8G9VlrT9KxnV9WPaHl/hYdqd 7WTi9yAnGCzgg2RFRDOms9MsooToKY7ggnzBIEdeluE= X-Google-Smtp-Source: AGHT+IGg6A43GqG+fKlJLbkXIsfEFKKzZHDVcgaPh9VZcMTtDZyP5x9WlL/UlqvbyGnHh219Vq4D3w== X-Received: by 2002:a17:907:6090:b0:aa6:7354:e926 with SMTP id a640c23a62f3a-ab2ab748ed0mr1428185366b.36.1736620647533; Sat, 11 Jan 2025 10:37:27 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-101-099.78.54.pool.telefonica.de. [78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:27 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 06/13] hw/sd/sd: Remove legacy sd_set_cb() in favor of GPIOs Date: Sat, 11 Jan 2025 19:37:04 +0100 Message-ID: <20250111183711.2338-7-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Commit ce5dd27534b0 "hw/sd: Remove omap2_mmc device" removed the last user of sd_set_cb(). Rework this functionality into GPIOs. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow --- include/hw/sd/sdcard_legacy.h | 1 - hw/sd/sd.c | 31 ++++++++++++++----------------- 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/include/hw/sd/sdcard_legacy.h b/include/hw/sd/sdcard_legacy.h index 0dc3889555..a121232560 100644 --- a/include/hw/sd/sdcard_legacy.h +++ b/include/hw/sd/sdcard_legacy.h @@ -36,7 +36,6 @@ SDState *sd_init(BlockBackend *blk, bool is_spi); int sd_do_command(SDState *card, SDRequest *request, uint8_t *response); void sd_write_byte(SDState *card, uint8_t value); uint8_t sd_read_byte(SDState *card); -void sd_set_cb(SDState *card, qemu_irq readonly, qemu_irq insert); /* sd_enable should not be used -- it is only used on the nseries boards, * where it is part of a broken implementation of the MMC card slot switch diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 0330d432fd..aa8d86e1af 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -820,6 +820,16 @@ static inline uint64_t sd_addr_to_wpnum(uint64_t addr) return addr >> (HWBLOCK_SHIFT + SECTOR_SHIFT + WPGROUP_SHIFT); } +static bool sd_get_inserted(SDState *sd) +{ + return sd->blk && blk_is_inserted(sd->blk); +} + +static bool sd_get_readonly(SDState *sd) +{ + return sd->wp_switch; +} + static void sd_reset(DeviceState *dev) { SDState *sd = SDMMC_COMMON(dev); @@ -865,16 +875,9 @@ static void sd_reset(DeviceState *dev) sd->dat_lines = 0xf; sd->cmd_line = true; sd->multi_blk_cnt = 0; -} -static bool sd_get_inserted(SDState *sd) -{ - return sd->blk && blk_is_inserted(sd->blk); -} - -static bool sd_get_readonly(SDState *sd) -{ - return sd->wp_switch; + qemu_set_irq(sd->readonly_cb, sd_get_readonly(sd)); + qemu_set_irq(sd->inserted_cb, sd_get_inserted(sd)); } static void sd_cardchange(void *opaque, bool load, Error **errp) @@ -1034,14 +1037,6 @@ SDState *sd_init(BlockBackend *blk, bool is_spi) return sd; } -void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert) -{ - sd->readonly_cb = readonly; - sd->inserted_cb = insert; - qemu_set_irq(readonly, sd->blk ? !blk_is_writable(sd->blk) : 0); - qemu_set_irq(insert, sd->blk ? blk_is_inserted(sd->blk) : 0); -} - static void sd_blk_read(SDState *sd, uint64_t addr, uint32_t len) { trace_sdcard_read_block(addr, len); @@ -2727,6 +2722,8 @@ static void sd_instance_init(Object *obj) sd->last_cmd_name = "UNSET"; sd->enable = true; sd->ocr_power_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sd_ocr_powerup, sd); + qdev_init_gpio_out_named(DEVICE(sd), &sd->inserted_cb, "cd", 1); + qdev_init_gpio_out_named(DEVICE(sd), &sd->readonly_cb, "wp", 1); } static void sd_instance_finalize(Object *obj) From patchwork Sat Jan 11 18:37:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13936128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FF76E7719A for ; Sat, 11 Jan 2025 18:41:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWgMZ-00078C-JG; Sat, 11 Jan 2025 13:37:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWgMX-000767-NU; Sat, 11 Jan 2025 13:37:33 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWgMW-0003vh-5f; Sat, 11 Jan 2025 13:37:33 -0500 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-aab925654d9so589712966b.2; Sat, 11 Jan 2025 10:37:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1736620649; x=1737225449; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kOFttKKVOfYxpHBSao0DEUzlTB31JRtFpeweJdc48Qg=; b=ZDspemxrqVuq73Gsf8+TrZvMtJc3t788nkMnsYCmUqHPIklsGBytJlm7XkHD26jz7v LZpe1QaLe10gCABKPlk26PnoEcWUEM5L8t3TsBZiKzxW3xTfNDOdLB4FYEvgPgnDMLpJ T4Djr2qe3lmzV8o6YeuJcvALgIneY7QV5/L9ghPyA2oUqDuKz2ipwmpohc3p8yHRrOPl MnjK2OlYAf3Vovw90wjAz/Yjx55L/kMbTG9c8CJgM176GFbI6fYPcyrRRVR1dnS3Z9tG XX0eoZ7t9nfIap50lnwbw+v1VR5kzLGNGNNlF6X/quZRH2gPcO6HFGtrNoFeXFoWcVYg 5xDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736620649; x=1737225449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kOFttKKVOfYxpHBSao0DEUzlTB31JRtFpeweJdc48Qg=; b=pYDquuSAg8hxkIMHXQ21zNGiOjDxN86QHfSGggSPhAUtBRzeRmOnBZWEOxfxq6iomW 8dAonnZa5hSaVRWFBajsgl17kQ+PwSycRqUOn+iinNhesZiXWWuOqnTMKl8YLpDBzTIe rl20RBWRxPCSPs2VnhUk/jdMRbRSI1/4IBeI/+H+uBo9yZtlYPRhk2NpsgK4cGfgpodq JsrKAYbAsxfPbeEtzNZeGhY2a+cGboq4E5UXd23IwOQ7n4zBH7hQfLQqtS43dj/Sk4NQ pZoehT+E9wREt4oeljc8JlMT+nl+TPREcuoFLFFurBMOSfmSNQR8qEAPQbBVs6soQ6BW ml7g== X-Forwarded-Encrypted: i=1; AJvYcCUSMjDtgV1jLM85pQDFFmQIJ+zEmPPNkVW18Q8yb0OJWIx/zRwtsSGtFfgnuYN2JzQ4SZ3xRPMzvl8moQ==@nongnu.org, AJvYcCXVRcJduQCJuhsHpRm5z1pPbjqxSMdboGkQ6AGUme8AT8y+KL0oYrc+wDlHLo9Q7dn6D4jgIEPeXQ==@nongnu.org X-Gm-Message-State: AOJu0YyVlJYOAsutezAQYxcRVQMkCP2oAAErcrhuxM2j5vy7FEiaRRnc 9Wz7ScjMZiJq86zFCJ1BCYaMqy9NXkOO4hlf1nqTQhn3L2rULz/lAj19pQ== X-Gm-Gg: ASbGncvfIJc84NKfKgeHOhBlSU19/JJG3B7uGvqFFPDrSs1VXWD/bpv5cM5Et3XMuV1 uCCJ9wApe6pfz9Gt20fD7rU5vu+uz3YlOibGIBI6zgWAvRe7JYq4xvr3t33q+Dk+VJje1g5eE4z 31nXpHKPTQjzQ4INLW/Z65VOgDImQEP+ctLWL1iU4nSJ78VJuffOAPmMuon6tAiVo2feM95SN2R +DLnsYoHTamKbwMhm0eIvsq26iN/xTjlCWKSnogUOjCJcKmuF1KWRP4GWvmz00aHDbhr5DeNlDG PK8IopOHrogm9b96dgGqK2/UpNsLSsk7UgqVE9n0fMo= X-Google-Smtp-Source: AGHT+IHBgmP5SDjLl2s4DtxI4ejxoEB3BFMJxpqCO0UsVaiSJdnWKsIc4QHgB2wcopuTorYp1i1H9A== X-Received: by 2002:a17:907:3ea3:b0:aae:8491:bab5 with SMTP id a640c23a62f3a-ab2ab73b234mr1340477766b.26.1736620648696; Sat, 11 Jan 2025 10:37:28 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-101-099.78.54.pool.telefonica.de. [78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:28 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 07/13] hw/sd/sd: Allow for inverting polarities of presence and write-protect GPIOs Date: Sat, 11 Jan 2025 19:37:05 +0100 Message-ID: <20250111183711.2338-8-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Bernhard Beschow --- hw/sd/sd.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index aa8d86e1af..a50e5c20c8 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -181,6 +181,8 @@ struct SDState { qemu_irq inserted_cb; QEMUTimer *ocr_power_timer; bool enable; + bool readonly_active_low; + bool inserted_active_low; uint8_t dat_lines; bool cmd_line; }; @@ -876,8 +878,8 @@ static void sd_reset(DeviceState *dev) sd->cmd_line = true; sd->multi_blk_cnt = 0; - qemu_set_irq(sd->readonly_cb, sd_get_readonly(sd)); - qemu_set_irq(sd->inserted_cb, sd_get_inserted(sd)); + qemu_set_irq(sd->readonly_cb, sd_get_readonly(sd) ^ sd->readonly_active_low); + qemu_set_irq(sd->inserted_cb, sd_get_inserted(sd) ^ sd->inserted_active_low); } static void sd_cardchange(void *opaque, bool load, Error **errp) @@ -896,9 +898,9 @@ static void sd_cardchange(void *opaque, bool load, Error **errp) } if (sd->me_no_qdev_me_kill_mammoth_with_rocks) { - qemu_set_irq(sd->inserted_cb, inserted); + qemu_set_irq(sd->inserted_cb, inserted ^ sd->inserted_active_low); if (inserted) { - qemu_set_irq(sd->readonly_cb, readonly); + qemu_set_irq(sd->readonly_cb, readonly ^ sd->readonly_active_low); } } else { sdbus = SD_BUS(qdev_get_parent_bus(dev)); @@ -2797,6 +2799,8 @@ static void emmc_realize(DeviceState *dev, Error **errp) static const Property sdmmc_common_properties[] = { DEFINE_PROP_DRIVE("drive", SDState, blk), + DEFINE_PROP_BOOL("cd-active-low", SDState, inserted_active_low, false), + DEFINE_PROP_BOOL("wp-active-low", SDState, readonly_active_low, false), }; static const Property sd_properties[] = { From patchwork Sat Jan 11 18:37:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13936122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7692BE7719A for ; Sat, 11 Jan 2025 18:39:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWgMc-0007E6-3p; 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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:29 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 08/13] hw/char/imx_serial: Turn some DPRINTF() statements into trace events Date: Sat, 11 Jan 2025 19:37:06 +0100 Message-ID: <20250111183711.2338-9-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow --- hw/char/imx_serial.c | 58 +++++++++++++++++++++++++++++--------------- hw/char/trace-events | 5 ++++ 2 files changed, 44 insertions(+), 19 deletions(-) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index be06f39a4d..38b4865157 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qemu/fifo32.h" +#include "trace.h" #ifndef DEBUG_IMX_UART #define DEBUG_IMX_UART 0 @@ -185,10 +186,10 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, unsigned size) { IMXSerialState *s = (IMXSerialState *)opaque; + Chardev *chr = qemu_chr_fe_get_driver(&s->chr); uint32_t c, rx_used; uint8_t rxtl = s->ufcr & TL_MASK; - - DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); + uint64_t value; switch (offset >> 2) { case 0x0: /* URXD */ @@ -209,49 +210,67 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, imx_serial_rx_fifo_ageing_timer_restart(s); qemu_chr_fe_accept_input(&s->chr); } - return c; + value = c; + break; case 0x20: /* UCR1 */ - return s->ucr1; + value = s->ucr1; + break; case 0x21: /* UCR2 */ - return s->ucr2; + value = s->ucr2; + break; case 0x25: /* USR1 */ - return s->usr1; + value = s->usr1; + break; case 0x26: /* USR2 */ - return s->usr2; + value = s->usr2; + break; case 0x2A: /* BRM Modulator */ - return s->ubmr; + value = s->ubmr; + break; case 0x2B: /* Baud Rate Count */ - return s->ubrc; + value = s->ubrc; + break; case 0x2d: /* Test register */ - return s->uts1; + value = s->uts1; + break; case 0x24: /* UFCR */ - return s->ufcr; + value = s->ufcr; + break; case 0x2c: - return s->onems; + value = s->onems; + break; case 0x22: /* UCR3 */ - return s->ucr3; + value = s->ucr3; + break; case 0x23: /* UCR4 */ - return s->ucr4; + value = s->ucr4; + break; case 0x29: /* BRM Incremental */ - return 0x0; /* TODO */ + value = 0x0; /* TODO */ + break; default: qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); - return 0; + value = 0; + break; } + + trace_imx_serial_read(chr ? chr->label : "NODEV", offset, value); + + return value; } static void imx_serial_write(void *opaque, hwaddr offset, @@ -261,8 +280,7 @@ static void imx_serial_write(void *opaque, hwaddr offset, Chardev *chr = qemu_chr_fe_get_driver(&s->chr); unsigned char ch; - DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n", - offset, (unsigned int)value, chr ? chr->label : "NODEV"); + trace_imx_serial_write(chr ? chr->label : "NODEV", offset, value); switch (offset >> 2) { case 0x10: /* UTXD */ @@ -374,9 +392,11 @@ static int imx_can_receive(void *opaque) static void imx_put_data(void *opaque, uint32_t value) { IMXSerialState *s = (IMXSerialState *)opaque; + Chardev *chr = qemu_chr_fe_get_driver(&s->chr); uint8_t rxtl = s->ufcr & TL_MASK; - DPRINTF("received char\n"); + trace_imx_serial_put_data(chr ? chr->label : "NODEV", value); + imx_serial_rx_fifo_push(s, value); if (fifo32_num_used(&s->rx_fifo) >= rxtl) { s->usr1 |= USR1_RRDY; diff --git a/hw/char/trace-events b/hw/char/trace-events index 59e1f734a7..92e002da7a 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -52,6 +52,11 @@ escc_sunkbd_event_out(int ch) "Translated keycode 0x%2.2x" escc_kbd_command(int val) "Command %d" escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%01x" +# imx_serial.c +imx_serial_read(const char *chrname, uint64_t addr, uint64_t value) "%s:[0x%03" PRIu64 "] -> 0x%08" PRIx64 +imx_serial_write(const char *chrname, uint64_t addr, uint64_t value) "%s:[0x%03" PRIu64 "] <- 0x%08" PRIx64 +imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32 + # pl011.c pl011_irq_state(int level) "irq state %d" pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" From patchwork Sat Jan 11 18:37:07 2025 Content-Type: text/plain; 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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:32 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 10/13] tests/qtest/libqos: Reuse TYPE_IMX_I2C define Date: Sat, 11 Jan 2025 19:37:08 +0100 Message-ID: <20250111183711.2338-11-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas Signed-off-by: Bernhard Beschow --- tests/qtest/libqos/arm-imx25-pdk-machine.c | 5 +++-- tests/qtest/libqos/i2c-imx.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/tests/qtest/libqos/arm-imx25-pdk-machine.c b/tests/qtest/libqos/arm-imx25-pdk-machine.c index 8fe128fae8..2d8b754343 100644 --- a/tests/qtest/libqos/arm-imx25-pdk-machine.c +++ b/tests/qtest/libqos/arm-imx25-pdk-machine.c @@ -23,6 +23,7 @@ #include "libqos-malloc.h" #include "qgraph.h" #include "i2c.h" +#include "hw/i2c/imx_i2c.h" #define ARM_PAGE_SIZE 4096 #define IMX25_PDK_RAM_START 0x80000000 @@ -50,7 +51,7 @@ static void *imx25_pdk_get_driver(void *object, const char *interface) static QOSGraphObject *imx25_pdk_get_device(void *obj, const char *device) { QIMX25PDKMachine *machine = obj; - if (!g_strcmp0(device, "imx.i2c")) { + if (!g_strcmp0(device, TYPE_IMX_I2C)) { return &machine->i2c_1.obj; } @@ -86,7 +87,7 @@ static void imx25_pdk_register_nodes(void) .extra_device_opts = "bus=i2c-bus.0" }; qos_node_create_machine("arm/imx25-pdk", qos_create_machine_arm_imx25_pdk); - qos_node_contains("arm/imx25-pdk", "imx.i2c", &edge, NULL); + qos_node_contains("arm/imx25-pdk", TYPE_IMX_I2C, &edge, NULL); } libqos_init(imx25_pdk_register_nodes); diff --git a/tests/qtest/libqos/i2c-imx.c b/tests/qtest/libqos/i2c-imx.c index 710cb926d6..6d868e4cc4 100644 --- a/tests/qtest/libqos/i2c-imx.c +++ b/tests/qtest/libqos/i2c-imx.c @@ -209,8 +209,8 @@ void imx_i2c_init(IMXI2C *s, QTestState *qts, uint64_t addr) static void imx_i2c_register_nodes(void) { - qos_node_create_driver("imx.i2c", NULL); - qos_node_produces("imx.i2c", "i2c-bus"); + qos_node_create_driver(TYPE_IMX_I2C, NULL); + qos_node_produces(TYPE_IMX_I2C, "i2c-bus"); } libqos_init(imx_i2c_register_nodes); From patchwork Sat Jan 11 18:37:09 2025 Content-Type: text/plain; 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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:33 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 11/13] hw/i2c/imx_i2c: Convert DPRINTF() to trace events Date: Sat, 11 Jan 2025 19:37:09 +0100 Message-ID: <20250111183711.2338-12-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Also print the QOM canonical path when tracing which allows for distinguishing the many instances a typical i.MX SoC has. Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow Acked-by: Corey Minyard --- hw/i2c/imx_i2c.c | 21 +++++---------------- hw/i2c/trace-events | 5 +++++ 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c index c565fd5b8a..d62213b9e0 100644 --- a/hw/i2c/imx_i2c.c +++ b/hw/i2c/imx_i2c.c @@ -25,18 +25,7 @@ #include "hw/i2c/i2c.h" #include "qemu/log.h" #include "qemu/module.h" - -#ifndef DEBUG_IMX_I2C -#define DEBUG_IMX_I2C 0 -#endif - -#define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX_I2C) { \ - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \ - __func__, ##args); \ - } \ - } while (0) +#include "trace.h" static const char *imx_i2c_get_regname(unsigned offset) { @@ -152,8 +141,8 @@ static uint64_t imx_i2c_read(void *opaque, hwaddr offset, break; } - DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n", - imx_i2c_get_regname(offset), offset, value); + trace_imx_i2c_read(DEVICE(s)->canonical_path, imx_i2c_get_regname(offset), + offset, value); return (uint64_t)value; } @@ -163,8 +152,8 @@ static void imx_i2c_write(void *opaque, hwaddr offset, { IMXI2CState *s = IMX_I2C(opaque); - DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n", - imx_i2c_get_regname(offset), offset, (int)value); + trace_imx_i2c_read(DEVICE(s)->canonical_path, imx_i2c_get_regname(offset), + offset, value); value &= 0xff; diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index f708a7ace1..1ad0e95c0e 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -56,3 +56,8 @@ npcm7xx_smbus_recv_fifo(const char *id, uint8_t received, uint8_t expected) "%s pca954x_write_bytes(uint8_t value) "PCA954X write data: 0x%02x" pca954x_read_data(uint8_t value) "PCA954X read data: 0x%02x" + +# imx_i2c.c + +imx_i2c_read(const char *id, const char *reg, uint64_t ofs, uint64_t value) "%s:[%s (0x%" PRIx64 ")] -> 0x%02" PRIx64 +imx_i2c_write(const char *id, const char *reg, uint64_t ofs, uint64_t value) "%s:[%s (0x%" PRIx64 ")] <- 0x%02" PRIx64 From patchwork Sat Jan 11 18:37:10 2025 Content-Type: text/plain; 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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:34 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 12/13] hw/misc/imx6_src: Convert DPRINTF() to trace events Date: Sat, 11 Jan 2025 19:37:10 +0100 Message-ID: <20250111183711.2338-13-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow --- hw/misc/imx6_src.c | 23 +++++------------------ hw/misc/trace-events | 6 ++++++ 2 files changed, 11 insertions(+), 18 deletions(-) diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index dc6a2b92ba..06cc46292e 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -17,18 +17,7 @@ #include "qemu/module.h" #include "target/arm/arm-powerctl.h" #include "hw/core/cpu.h" - -#ifndef DEBUG_IMX6_SRC -#define DEBUG_IMX6_SRC 0 -#endif - -#define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX6_SRC) { \ - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX6_SRC, \ - __func__, ##args); \ - } \ - } while (0) +#include "trace.h" static const char *imx6_src_reg_name(uint32_t reg) { @@ -87,7 +76,7 @@ static void imx6_src_reset(DeviceState *dev) { IMX6SRCState *s = IMX6_SRC(dev); - DPRINTF("\n"); + trace_imx6_src_reset(); memset(s->regs, 0, sizeof(s->regs)); @@ -111,7 +100,7 @@ static uint64_t imx6_src_read(void *opaque, hwaddr offset, unsigned size) } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx6_src_reg_name(index), value); + trace_imx6_src_read(imx6_src_reg_name(index), value); return value; } @@ -134,8 +123,7 @@ static void imx6_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) assert(bql_locked()); s->regs[SRC_SCR] = deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0); - DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", - imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]); + trace_imx6_clear_reset_bit(imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]); g_free(ri); } @@ -173,8 +161,7 @@ static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value, return; } - DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx6_src_reg_name(index), - (uint32_t)current_value); + trace_imx6_src_write(imx6_src_reg_name(index), value); change_mask = s->regs[index] ^ (uint32_t)current_value; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 0f5d2b5666..cf1abe6928 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -253,6 +253,12 @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 +# imx6_src.c +imx6_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 +imx6_src_write(const char *reg_name, uint64_t value) "reg[%s] <= 0x%" PRIx64 +imx6_clear_reset_bit(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 +imx6_src_reset(void) "" + # imx7_src.c imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 From patchwork Sat Jan 11 18:37:11 2025 Content-Type: text/plain; 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[78.54.101.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95af187sm299026666b.142.2025.01.11.10.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 10:37:36 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Fabiano Rosas , Paolo Bonzini , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, =?utf-8?q?M?= =?utf-8?q?arc-Andr=C3=A9_Lureau?= , Jean-Christophe Dubois , Laurent Vivier , Bin Meng , qemu-block@nongnu.org, Bernhard Beschow Subject: [PATCH v2 13/13] hw/gpio/imx_gpio: Turn DPRINTF() into trace events Date: Sat, 11 Jan 2025 19:37:11 +0100 Message-ID: <20250111183711.2338-14-shentey@gmail.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250111183711.2338-1-shentey@gmail.com> References: <20250111183711.2338-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While at it add a trace event for input GPIO events. Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Bernhard Beschow --- hw/gpio/imx_gpio.c | 18 +++++++----------- hw/gpio/trace-events | 5 +++++ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c index 67c47a7280..25546221e0 100644 --- a/hw/gpio/imx_gpio.c +++ b/hw/gpio/imx_gpio.c @@ -24,6 +24,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "trace.h" #ifndef DEBUG_IMX_GPIO #define DEBUG_IMX_GPIO 0 @@ -34,14 +35,6 @@ typedef enum IMXGPIOLevel { IMX_GPIO_LEVEL_HIGH = 1, } IMXGPIOLevel; -#define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX_GPIO) { \ - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \ - __func__, ##args); \ - } \ - } while (0) - static const char *imx_gpio_reg_name(uint32_t reg) { switch (reg) { @@ -111,6 +104,8 @@ static void imx_gpio_set(void *opaque, int line, int level) IMXGPIOState *s = IMX_GPIO(opaque); IMXGPIOLevel imx_level = level ? IMX_GPIO_LEVEL_HIGH : IMX_GPIO_LEVEL_LOW; + trace_imx_gpio_set(DEVICE(s)->canonical_path, line, imx_level); + imx_gpio_set_int_line(s, line, imx_level); /* this is an input signal, so set PSR */ @@ -200,7 +195,8 @@ static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size) break; } - DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value); + trace_imx_gpio_read(DEVICE(s)->canonical_path, imx_gpio_reg_name(offset), + reg_value); return reg_value; } @@ -210,8 +206,8 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value, { IMXGPIOState *s = IMX_GPIO(opaque); - DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset), - (uint32_t)value); + trace_imx_gpio_write(DEVICE(s)->canonical_path, imx_gpio_reg_name(offset), + value); switch (offset) { case DR_ADDR: diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index b91cc7e9a4..cea896b28f 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -1,5 +1,10 @@ # See docs/devel/tracing.rst for syntax documentation. +# imx_gpio.c +imx_gpio_read(const char *id, const char *reg, uint32_t value) "%s:[%s] -> 0x%" PRIx32 +imx_gpio_write(const char *id, const char *reg, uint32_t value) "%s:[%s] <- 0x%" PRIx32 +imx_gpio_set(const char *id, int line, int level) "%s:[%d] <- %d" + # npcm7xx_gpio.c npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64