From patchwork Sun Jan 12 15:53:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5648E7719C for ; Sun, 12 Jan 2025 15:55:59 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id EC7B46B009F; Sun, 12 Jan 2025 10:55:43 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id E25B76B009C; Sun, 12 Jan 2025 10:55:43 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8F0346B00A1; Sun, 12 Jan 2025 10:55:43 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 4B9916B009C for ; Sun, 12 Jan 2025 10:55:43 -0500 (EST) Received: from smtpin23.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay05.hostedemail.com (Postfix) with ESMTP id 0F10140834 for ; Sun, 12 Jan 2025 15:55:43 +0000 (UTC) X-FDA: 82999250166.23.8E6BFE6 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf06.hostedemail.com (Postfix) with ESMTP id 7F57B180006 for ; Sun, 12 Jan 2025 15:55:41 +0000 (UTC) Authentication-Results: imf06.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf06.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1736697341; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dpGlWYXD8ytxJCUwIO6zQgRV3qwvcKaHGc7OrRtIz9E=; b=3OvQwpK04FD7KLcEDq4VhBMgysMm6WP8bqTZTBoOtaWDREmWIf1A+ZRL+ppbciENJthLt9 Gs+GswbIVaVY4aga6hYzhq0d0saDyr5hfMi3kT81ePuQlErk9u3YjpddZAQaSJgByZeFTz omjiS5KemTxauPICNODRGlCmTUi0Qn0= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1736697341; a=rsa-sha256; cv=none; b=mL3zMS4Q/liYQj7O+lu49PLGBWEps+OMSrW+0UjO6iNxlStyzqkhb3u6jpyohd7uoAi25w +Xi/EtAz6JWGE5KpOhq0QB/6MuWwXpfpEytf9C9gYXw/aBeeoO1O3IUpbDZV6ezPga+UX+ 12gJyQBDgMIerzo1b8dzNmJzI3GX508= ARC-Authentication-Results: i=1; imf06.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf06.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-2bLe; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Date: Sun, 12 Jan 2025 10:53:45 -0500 Message-ID: <20250112155453.1104139-2-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Stat-Signature: 6qq44x1kk76gd5phnx7tx4csbot6ok88 X-Rspamd-Queue-Id: 7F57B180006 X-Rspam-User: X-Rspamd-Server: rspam01 X-HE-Tag: 1736697341-41070 X-HE-Meta: U2FsdGVkX198NsjsJVlhcyA5sbECKkg5sVmTmjK/KA4aCywGJzIwRM6muah2hoeQtiO6BaAgsshTd08VAGl+8l530CKtQ60OSRRiFjB0oK8NeI3hMlBzhz4YAMVDmWFLVBrKLUT2AV43DdJQpRVWoktSYb0h0aI4BKtpI21cLPMrY5LGXhszhp0jeKnAabi+KYFibZBzNslxvOSLek0DlHJXlUVRjY7ArzbpQHbCWq9RYGvAcEDP6LwVC1U3rQvg8gY23riXKD+HbnHKC4uBriFJl41TkCz6K2Bqw9bBL49ih9n9nW12aLR7irPbfaRPDa99G8mfPoYIx/Aeo8uXWkNRH+jm1V+w0CO9Um8jnVjFP6SynHPdiJidG8vB9KJ3ybwqWzilIUPT+Q0ibgHyYQJlXDlc4m8bGpTE1jBqhykHX1nXhicZC93lJ91w2H3yEYxbxKVhSJKGhpxQsr7zWtcu7zoWSUNiEneuztDt8DjGMKAKSuQpQVOSB6lyau+WRAA2V+Ma3spwbkj8I1VOCDlmmvoG+jgRT6Sg/ygHl+AwknpCDUxJhGY1N9w5KgauhbeSRkFdIJd5ghrG5yvGPyJ0Fbk2mG7tOW7af6qi3JqT2LG3wY3CRsYfu8JeF8gNM/adEaq5mLLUrtuRXDSkV0+bFjiT9Ja7X18I11PXuG0lBTAc+Rx7qBNTjDpiOb7k0PiyVYA/EWcYKYmfgaLnz6YWH7OQQ+S3VwwM0v/lGdZ5h3PY7Jdgt5bPGoqtaDYIcySO9UgZ+rzDga4Q114U/v2Ri9AcctAS3az2lamUgKv5PwY6DwO/+XULqN8tSa02z9QA+PDfE1e2hwKJwcBt5TILhXWvvmutxjFQ4SCLatKBDdtDvxv/xXFSU3M4xWG6ujbLRPcUSNtswILq0Y5zIWKmHZnak0V8geugfGneYPL2fusTA0yHWPspAa43WUxaCyo0YPxD47/03n9fkxO 6klUfUoy xWG9cH7HQZpft3zbsG2jXDTL1ZRPiIhBx6lTPp2YMBCgSqwpiUN8HY66W1CNhoDwl61t38o4+Cnk9bUMu5CCaj1F8VNfiU6seGLoeR2QkSfU820OfY7hJa5ndpTXD/vrcsaM4CeFQUhVepn3MxRbW8GMaIFCj+JUt818vLioLbekmVe2diOpS70VajBw0dQhL1ACsDLWnTEMCqqz+SXHHC0yD1pJF7hOGbaYjSRT/so9pSC5fccnczYpjrckc5yYaci4RUKgLmDLM4NFym2Ir/GHCVtF9kZlHZti5uMYRyUPLh3sxKO7abB+YjB0hLn77G3uwjKA+KGMOS3weUzIW8Ee9EMV79HVkcuU4ia/a0kKDYnsUKRbNmUBQLsfLNMpUjKY7nH5JSP4IRwPTMOP6vDkwq9gYrPSaWIktDA/5K0c1BgnegwyLHOISncvQsQXsSFPRiwyAIqPsq18Qp0rtHUEFF2pV48J+serdgRJtph067T//nTaGdEkL/Q== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Currently x86 uses CONFIG_MMU_GATHER_TABLE_FREE when using paravirt, and not when running on bare metal. There is no real good reason to do things differently for each setup. Make them all the same. Currently get_user_pages_fast synchronizes against page table freeing in two different ways: - on bare metal, by blocking IRQs, which block TLB flush IPIs - on paravirt, with MMU_GATHER_RCU_TABLE_FREE This is done because some paravirt TLB flush implementations handle the TLB flush in the hypervisor, and will do the flush even when the target CPU has interrupts disabled. After this change, the synchronization between get_user_pages_fast and page table freeing is always handled with MMU_GATHER_RCU_TABLE_FREE, which allows bare metal to also do TLB flushes while interrupts are disabled. That makes it safe to use INVLPGB on AMD CPUs. Signed-off-by: Rik van Riel Suggested-by: Peter Zijlstra --- arch/x86/Kconfig | 2 +- arch/x86/kernel/paravirt.c | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d7bd0ae48c4..e8743f8c9fd0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -274,7 +274,7 @@ config X86 select HAVE_PCI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP - select MMU_GATHER_RCU_TABLE_FREE if PARAVIRT + select MMU_GATHER_RCU_TABLE_FREE select MMU_GATHER_MERGE_VMAS select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index fec381533555..2b78a6b466ed 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -59,11 +59,6 @@ void __init native_pv_lock_init(void) static_branch_enable(&virt_spin_lock_key); } -static void native_tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - tlb_remove_page(tlb, table); -} - struct static_key paravirt_steal_enabled; struct static_key paravirt_steal_rq_enabled; @@ -191,7 +186,7 @@ struct paravirt_patch_template pv_ops = { .mmu.flush_tlb_kernel = native_flush_tlb_global, .mmu.flush_tlb_one_user = native_flush_tlb_one_user, .mmu.flush_tlb_multi = native_flush_tlb_multi, - .mmu.tlb_remove_table = native_tlb_remove_table, + .mmu.tlb_remove_table = tlb_remove_table, .mmu.exit_mmap = paravirt_nop, .mmu.notify_page_enc_status_changed = paravirt_nop, From patchwork Sun Jan 12 15:53:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 464BBE7719E for ; Sun, 12 Jan 2025 15:55:44 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 987EB6B0099; Sun, 12 Jan 2025 10:55:42 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 7B73B6B0092; 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Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Date: Sun, 12 Jan 2025 10:53:46 -0500 Message-ID: <20250112155453.1104139-3-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 047DE160016 X-Stat-Signature: 1xmsc4nzp8ue1x7mmyz36zuz1rw9x4aa X-HE-Tag: 1736697339-836737 X-HE-Meta: U2FsdGVkX19QXgek92a2T21h7InM27kJACoIOwwn0yXYIcxuvVRD7/YhzvZSGunvxiOCmRlRknBETLkqS18WgREFdwAs49mKsF3uxnB89nS/7n9BHZhuZFBccmjBvgHwPBaShiVJjPqorJ6szvKlvTTwaP8jozBNN+cNFoHOVum6zj61vUNnIufTgKjmMyZTVH860Mx0zuXV0EExulkl/+M8dAjWfKV5ZxzPbFtjUQSYmPKVnobT2LgLuyzonpkO6acJ3FuH31sDYV+V76qcmKGQcIsLZq4WH2UN5jyjpWZxZcJ0vLPpLjozfxq6EC81mBIxsD5E65JbHpuv01jR1VIgU3/T6ZD0GjhpPNf7ZHoAePUNYFSx2Is98HskVX+FNEcx3NhKbZsrWbW12XreharR6pXarHIattoS0ISPt5BNMqL0I4lL5LvaxiPU8yDsaJPct+O2hFtCLzF1D9NNi/wzMYBXlQvA26debp1GSvGL1jpxEwJULgJe70UH3jUMIYYxxoNms0g7gmfGim7K1k4r4jtzvcLkLJJWFNOG9re8twuHV6aCEecSwHeDhemKLPAzEVnqSIcOlkZg+66BLnuhIsUx05Rg9jk4wEW9Ej6D53sdFPkycbnM/83I34xBJ3RDqgv9n+Nyg5jbDgA7OQScfcC8TEdhDmBgAeCsQR0niOVC5KABt+ORRFD/g8iCf3MozymWxbMHeMidbnXLFj/KEjSUMVSHYbhfqXpc4hiioJO1l2/ttgJjNd3xVJa3sqx2Hf/+F4s2SoIkSSHzlDYvIYj8D945oBKMiPgLeOA2RfhHVhzw5SgeFrQkXwcNfIedODUqqUzJ2rhZ9UFuCkqOmbfzxdydSS3WgTcWq22Le3ihLsiUUTzjdw64NEq16haUUWOskWUXMYT9xT9XgJZ1U9CkP3s8hvDaKx1lahYQhP+Z6VPRuhwoDBao7a/MurLt8POIDEkbDDXWPBA QvaLvCiw SfUtJnBiF6N6HziioBMczXgsoX4ENI/ugeE6CL7KNGykfl1oOyyX/Sc2Rc7edz1f+t3r/O/wEUt4H1gKqQBWKzAU6hNCQYpBf7pT+REu1zdUh2nSWRMaqSXl8kNJZ++NWmcxdk9n4tjF6YBxgPMAIDD9aXog4Rj1UwlvOy3izi+Wg7LGg593aSqTN8r2xbEne3Xm50TNf+4h0zpGNzZhpuErpgj4McvnSa9T1iWIad6ZJg5KVXHWZM2qa7npg1SrIQgd84beDVoO12wyBjHpbdPOMICHXTcwp2+rt8BYfJ5h/tgQqnUGfxsFyZ6rToft5dI+WnjynGCcOJ9Zl1kGITzASfz9WzMgOVyQhG087AJcoDz0TasquX8F+Lit9Ng95OpXUV+qW4WNFUhRdg9Dwc/utrEPieCn45t9jXJ1LdX3HsMwtpKkdIntEijf715/3kZThUb9cFRJbWVI= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Every pv_ops.mmu.tlb_remove_table call ends up calling tlb_remove_table. Get rid of the indirection by simply calling tlb_remove_table directly, and not going through the paravirt function pointers. Signed-off-by: Rik van Riel Suggested-by: Qi Zheng --- arch/x86/hyperv/mmu.c | 1 - arch/x86/include/asm/paravirt.h | 5 ----- arch/x86/include/asm/paravirt_types.h | 2 -- arch/x86/kernel/kvm.c | 1 - arch/x86/kernel/paravirt.c | 1 - arch/x86/mm/pgtable.c | 16 ++++------------ arch/x86/xen/mmu_pv.c | 1 - 7 files changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/x86/hyperv/mmu.c b/arch/x86/hyperv/mmu.c index 1cc113200ff5..cbe6c71e17c1 100644 --- a/arch/x86/hyperv/mmu.c +++ b/arch/x86/hyperv/mmu.c @@ -240,5 +240,4 @@ void hyperv_setup_mmu_ops(void) pr_info("Using hypercall for remote TLB flush\n"); pv_ops.mmu.flush_tlb_multi = hyperv_flush_tlb_multi; - pv_ops.mmu.tlb_remove_table = tlb_remove_table; } diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index d4eb9e1d61b8..794ba3647c6c 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -91,11 +91,6 @@ static inline void __flush_tlb_multi(const struct cpumask *cpumask, PVOP_VCALL2(mmu.flush_tlb_multi, cpumask, info); } -static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - PVOP_VCALL2(mmu.tlb_remove_table, tlb, table); -} - static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) { PVOP_VCALL1(mmu.exit_mmap, mm); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 8d4fbe1be489..13405959e4db 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -136,8 +136,6 @@ struct pv_mmu_ops { void (*flush_tlb_multi)(const struct cpumask *cpus, const struct flush_tlb_info *info); - void (*tlb_remove_table)(struct mmu_gather *tlb, void *table); - /* Hook for intercepting the destruction of an mm_struct. */ void (*exit_mmap)(struct mm_struct *mm); void (*notify_page_enc_status_changed)(unsigned long pfn, int npages, bool enc); diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 7a422a6c5983..3be9b3342c67 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -838,7 +838,6 @@ static void __init kvm_guest_init(void) #ifdef CONFIG_SMP if (pv_tlb_flush_supported()) { pv_ops.mmu.flush_tlb_multi = kvm_flush_tlb_multi; - pv_ops.mmu.tlb_remove_table = tlb_remove_table; pr_info("KVM setup pv remote TLB flush\n"); } diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 2b78a6b466ed..c019771e0123 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -186,7 +186,6 @@ struct paravirt_patch_template pv_ops = { .mmu.flush_tlb_kernel = native_flush_tlb_global, .mmu.flush_tlb_one_user = native_flush_tlb_one_user, .mmu.flush_tlb_multi = native_flush_tlb_multi, - .mmu.tlb_remove_table = tlb_remove_table, .mmu.exit_mmap = paravirt_nop, .mmu.notify_page_enc_status_changed = paravirt_nop, diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 5745a354a241..3dc4af1f7868 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -18,14 +18,6 @@ EXPORT_SYMBOL(physical_mask); #define PGTABLE_HIGHMEM 0 #endif -#ifndef CONFIG_PARAVIRT -static inline -void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - tlb_remove_page(tlb, table); -} -#endif - gfp_t __userpte_alloc_gfp = GFP_PGTABLE_USER | PGTABLE_HIGHMEM; pgtable_t pte_alloc_one(struct mm_struct *mm) @@ -54,7 +46,7 @@ void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) { pagetable_pte_dtor(page_ptdesc(pte)); paravirt_release_pte(page_to_pfn(pte)); - paravirt_tlb_remove_table(tlb, pte); + tlb_remove_table(tlb, pte); } #if CONFIG_PGTABLE_LEVELS > 2 @@ -70,7 +62,7 @@ void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) tlb->need_flush_all = 1; #endif pagetable_pmd_dtor(ptdesc); - paravirt_tlb_remove_table(tlb, ptdesc_page(ptdesc)); + tlb_remove_table(tlb, ptdesc_page(ptdesc)); } #if CONFIG_PGTABLE_LEVELS > 3 @@ -80,14 +72,14 @@ void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) pagetable_pud_dtor(ptdesc); paravirt_release_pud(__pa(pud) >> PAGE_SHIFT); - paravirt_tlb_remove_table(tlb, virt_to_page(pud)); + tlb_remove_table(tlb, virt_to_page(pud)); } #if CONFIG_PGTABLE_LEVELS > 4 void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d) { paravirt_release_p4d(__pa(p4d) >> PAGE_SHIFT); - paravirt_tlb_remove_table(tlb, virt_to_page(p4d)); + tlb_remove_table(tlb, virt_to_page(p4d)); } #endif /* CONFIG_PGTABLE_LEVELS > 4 */ #endif /* CONFIG_PGTABLE_LEVELS > 3 */ diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index 55a4996d0c04..041e17282af0 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -2137,7 +2137,6 @@ static const typeof(pv_ops) xen_mmu_ops __initconst = { .flush_tlb_kernel = xen_flush_tlb, .flush_tlb_one_user = xen_flush_tlb_one_user, .flush_tlb_multi = xen_flush_tlb_multi, - .tlb_remove_table = tlb_remove_table, .pgd_alloc = xen_pgd_alloc, .pgd_free = xen_pgd_free, From patchwork Sun Jan 12 15:53:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 373E4E77188 for ; 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Signed-off-by: Rik van Riel Suggested-by: Dave Hansen --- arch/x86/mm/tlb.c | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 6cf881a942bb..2b339f55f839 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1009,6 +1009,15 @@ static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm, info->initiating_cpu = smp_processor_id(); info->trim_cpumask = 0; + /* + * If the number of flushes is so large that a full flush + * would be faster, do a full flush. + */ + if ((end - start) >> stride_shift > tlb_single_page_flush_ceiling) { + info->start = 0; + info->end = TLB_FLUSH_ALL; + } + return info; } @@ -1026,17 +1035,8 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, bool freed_tables) { struct flush_tlb_info *info; + int cpu = get_cpu(); u64 new_tlb_gen; - int cpu; - - cpu = get_cpu(); - - /* Should we flush just the requested range? */ - if ((end == TLB_FLUSH_ALL) || - ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) { - start = 0; - end = TLB_FLUSH_ALL; - } /* This is also a barrier that synchronizes with switch_mm(). */ new_tlb_gen = inc_mm_tlb_gen(mm); @@ -1089,22 +1089,18 @@ static void do_kernel_range_flush(void *info) void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - /* Balance as user space task's flush, a bit conservative */ - if (end == TLB_FLUSH_ALL || - (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) { - on_each_cpu(do_flush_tlb_all, NULL, 1); - } else { - struct flush_tlb_info *info; + struct flush_tlb_info *info; + guard(preempt)(); - preempt_disable(); - info = get_flush_tlb_info(NULL, start, end, 0, false, - TLB_GENERATION_INVALID); + info = get_flush_tlb_info(NULL, start, end, PAGE_SHIFT, false, + TLB_GENERATION_INVALID); + if (end == TLB_FLUSH_ALL) + on_each_cpu(do_flush_tlb_all, NULL, 1); + else on_each_cpu(do_kernel_range_flush, info, 1); - put_flush_tlb_info(); - preempt_enable(); - } + put_flush_tlb_info(); } /* @@ -1276,7 +1272,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) int cpu = get_cpu(); - info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, + info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, PAGE_SHIFT, false, TLB_GENERATION_INVALID); /* * flush_tlb_multi() is not optimized for the common case in which only From patchwork Sun Jan 12 15:53:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3769E77188 for ; Sun, 12 Jan 2025 15:55:55 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 960FF6B0098; Sun, 12 Jan 2025 10:55:43 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 371CC6B009F; Sun, 12 Jan 2025 10:55:43 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id F2A7A6B009A; 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imf05.hostedemail.com; dkim=none; spf=pass (imf05.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1736697341; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sOiwDzUcJmcySWabyvYzZaW6UaPMP6se+kpAPen0v7I=; b=36EqEk00eht8XieXl1/1FmPTzzP6BXaMmWVVXGeVuPjfkdCeIXyA/kqzud5N5m87x/Kh8q x8NwLkzMNcF+8fjOOJb4LjX9+J4cOxkhODPoU1PoTenvzVxOPWm0e3i+nc0PNKT1eGx8iI ohw8TvYuCkkAmpibc9ZfVK18REtN9To= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-2ujL; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 04/12] x86/mm: get INVLPGB count max from CPUID Date: Sun, 12 Jan 2025 10:53:48 -0500 Message-ID: <20250112155453.1104139-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 03C5D100009 X-Stat-Signature: i67p785cfotognu43yp9zt5jjkxrchhu X-Rspam-User: X-Rspamd-Server: rspam09 X-HE-Tag: 1736697340-822753 X-HE-Meta: U2FsdGVkX19CFeuApN4j8UTk3ZnXw+oBc4S9ld55crYDA6hGCcr94PME8LjSMcOQkpILyF50W4ZANN8f4gljNFGBFZE+1qLAUTO6uHY0vnMSAKdHTxfM+4+ssNG4emZbzGghLczsWMYC5bDQMvr+5MLJpIQDtnRdlYmCGC30Pu+88LGp9j3DRR0+RV5GnTM1RvVrWFtUJMMaRHrGmCg+o81CXvTuKH82e5W6h1QrE+Q6+NRQwfRkqqHcgMGSTbJA1//s+hXDUxavBBVwRoMEJNsbp457jEzzaSxIvB+ZJOuGjJsIzK8egHkCNfzrd76KIjz7N2XauS4UdHyekwza413II+In8pqInCLWixc2BrcSmtl+F61Of9N7qjXyrISUkw2lhfFJzV3egb34j8bofNfX1ExHYu2MUfvWzmrHlEYLV7uSl4Sy1hCaFVMu8NirZlo3qhFwMouOM7oWAArsoGyxMQ8CpZm/BCyxfq8UV2aDcwFSbT7NUhVzOFOrhyx+FniutPSpyUaXomxbo2UjFzjCyMg67YMPOFdxVvwvOGoGAQ8FSO0M6bn7cgWEy2Z+dklPM0x4+DixJ4mDxMDJILGo4HPgSVPQy7EQjPbCzOM20m6T4PEUbNl02ksLoz0BJIfNQSUiprAY9DdJEBKTlrb49oJJKTjl9H/uJIT8PhdyKkVSYThwa6qvnNMIRv0AWAlXqa553dvpAy5N7GIExNbdL0xBQuCfthCAYtCIIB5xqOmC3ZwkUMU4W9eHZtaN2pv0Bzh1oYJJD6nkcognXPIgeYWctRVbb02+ywcV77YTkiX+jhkN8YLfgSkxFdUls3zX5BHXKbUga+hnscQPHJ5w2D7Xdr9IQj6rLGSZwqQ1TeXj+3/xXtNv6Sv4MxUgONlNfy2brtXzg7dulqkzJzOc6mwDAeQNNdLq2pAr2a1DeryQn6jJWfCulBeokl46VcF3RwXVjpXXnDXgbyJ AmPLZCPb fq2G/IPvr+/nP5T2pSZdlj9o/p60ApX4OOlEoOwDQ1UOtYDd6SWvXqYXFrac9URFWB9ywt81ra/fRFS2rbr6lUESigrdHMqxErSoyDMwfGJs8tLv1BQfRLMSJZre8UCWg/TU1XP9ECNj3jsT9mcBiIRmDo7yxyI02Bz2xmOCZ/68Jr2Nzd8z8AiJF2xBASkLYQyREA5gKQsCyv19/HZgVeF6QBuKq682xfiSzkDT0WvvBdbKTG6j8a0bQLRJb+yodmhB8xJno0YqYLYyKVNMCrcUGSfXhY+EAh30NiXur+0sa9vuglg/By/olHLXK6US18xuAXT97GhVMaZw3aXOeMSnpQfU7wwVVjRfllxmzBNvLcyJme0v7/3hqzDyhe6BXTozXAubFb/Fu7EY= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..bacdc502903f 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = { From patchwork Sun Jan 12 15:53:49 2025 Content-Type: text/plain; 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d=hostedemail.com; s=arc-20220608; t=1736697342; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KTwHDX9ZwNE0qLpg8jL7jj/Bv2rokHfmlVRjvUotn08=; b=5RM4CyRHg1hhCpXQDrhl3q6vluBJ4d86RhBMDLLS3ndh/ZVqv0aE25wG83/b4O08cubwae b71GM4+M2smwuy7IMzRYp9wm1K2Cnhc8NdfJK+MO5MArrzpxfdEd7pWt3mG2ISs1UdeNl+ ikHNI7gLRNbEceOkX1Op/BMuw7s5Wc8= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-30FD; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 05/12] x86/mm: add INVLPGB support code Date: Sun, 12 Jan 2025 10:53:49 -0500 Message-ID: <20250112155453.1104139-6-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 0845340003 X-Stat-Signature: pj5ggsu13gm1pge9w1buohtatuq9dw1n X-HE-Tag: 1736697341-255506 X-HE-Meta: U2FsdGVkX1/NetAFGoU7dTpN2UvxkISfd2Z4ZduOqbutCaCfiSRWWnfdvt+hAglX37sRK0qvih7A0NHgHdvUvhmZ6thtvYkasjFHaiEX3kZa6NgMMdBjA/jyZtQ1m0nGGr1Fk5fAFpwGriTna+Rrvu4OT6KfONkHjPzV7r4/kUhtGG2pPvICw4ZHFLxys+Ej7ZD1lssMLWWbxA4CtsYyijPNomJ8zsk60sMX+bQ0KEDlQK7GmVb4uTUEfY5zqRWdc6kBOMPqiXNmJe1XvI5znVgfpEpUKEVzex+NBNthPaTDql8I4Lk2stMNyMvJsRblsNy8VdZx/xyzFZQ0ueIc29P9t92ISmo6rTSPMWKKr6hDzift7ABw+R7YbfgbueCqpu3dIWgMSZKonoptTc55F/XJuSjFubMZd+gSKDbp9LSU0bxN+3rOD0m+vAc5ZC+yUuHDyC4/djKvLRFCPqsWlpDyUJ3jt3RYCkUqy24iJ7VKyU09ryM59hiD5eU04O2JXc6FxUpza/Ov3PpeycxRbShUliklUhnp/bbcxZ0WtdrN+A+IyBCKkOVzyLczt5+IglnCk9POZSMZaMymJo87n8tXZeErPsbOTIwbgdCQJbnWLisC1Eqr7K6/CbpMTJF6yhs45L7/AOR3fKjO97O9R4AghP5CIYsQ3mnMSbAnG8eptJPNsXvUUuQ1S3jGG2ct9yZHmE/rVuiPGPzxnTotb6qvPxbm7ei8Qp91rG7RAJVJRxVEmxC22QvwU5EjDYgTdfxxlio4P8iHKhrXVrbp21a9CSDKaDF4IAg18l6BkSo2d/ia8ec6PBNlDvoIxpupAM30eu5hJ/492VzVBTwJqhreWYMUNcLNgT6uBh0LHiVzYBongFpj/+t12D+Fs4WWumUBL4kBU5zY3WaLvV0P8TmEtYUKK7xbT6qCs+hf7w6vtDyejF/+/VKKq70y2C9L1K6C8eojhn/WxtXwYMt Neno3x0/ YYvxC/B6jv31LNygHIP4IUcZJuUhpi4Zp5xdcMLHd/vcrUkjPPtcMv2ja2kU4jOvodmip1sKo8IvnfzqTppMu0okWJBd2xxue5yDn4t9y8kUT2Vv8v7HLw4yt3+0tGFmRUyFjwa1m9d1Xrp3XAUcJP/siklMCpv43RT1GoK5ARVQfv/2kqm2aADj1F64feFXNWJ8tSNA8sYfjka0MiINATWdJrxcmDTYeZTMDsoU3bPZkna6TeQUaZQojdtsq12tsa2AfeUL2X1iGTJR04oCwdmnMkXoeSDJIO4flneuYQdwHchFBGQ3BJKtNUgt+8oPzzvlqCn+MJZiwwCHkwB+HQBL++HL8dvEszOy/K0MNXBl4qQINUcrYfqIxjLYgUPpDPLGVxQJmn+6CzFg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 95 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 96 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..d62e3733a1ab --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, unsigned long addr, + int extra_count, bool pmd_stride, unsigned long flags) +{ + u32 edx = (pcid << 16) | asid; + u32 ecx = (pmd_stride << 31); + u64 rax = addr | flags; + + /* Protect against negative numbers. */ + extra_count = max(extra_count, 0); + ecx |= extra_count; + + asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + asm volatile("tlbsync"); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); + tlbsync(); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + int nr, bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); + tlbsync(); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr_nosync(unsigned long addr, int nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); + tlbsync(); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 8fe3b2dda507..dba5caa4a9f4 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include From patchwork Sun Jan 12 15:53:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA570E7719E for ; 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Remove the need to send IPIs for kernel TLB flushes. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 2b339f55f839..45c7b84f6f80 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1077,6 +1077,30 @@ void flush_tlb_all(void) on_each_cpu(do_flush_tlb_all, NULL, 1); } +static bool broadcast_kernel_range_flush(struct flush_tlb_info *info) +{ + unsigned long addr; + unsigned long nr; + + if (!IS_ENABLED(CONFIG_X86_BROADCAST_TLB_FLUSH)) + return false; + + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return false; + + if (info->end == TLB_FLUSH_ALL) { + invlpgb_flush_all(); + return true; + } + + for (addr = info->start; addr < info->end; addr += nr << PAGE_SHIFT) { + nr = min((info->end - addr) >> PAGE_SHIFT, invlpgb_count_max); + invlpgb_flush_addr_nosync(addr, nr); + } + tlbsync(); + return true; +} + static void do_kernel_range_flush(void *info) { struct flush_tlb_info *f = info; @@ -1095,7 +1119,9 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) info = get_flush_tlb_info(NULL, start, end, PAGE_SHIFT, false, TLB_GENERATION_INVALID); - if (end == TLB_FLUSH_ALL) + if (broadcast_kernel_range_flush(info)) + ; /* Fall through. */ + else if (end == TLB_FLUSH_ALL) on_each_cpu(do_flush_tlb_all, NULL, 1); else on_each_cpu(do_kernel_range_flush, info, 1); From patchwork Sun Jan 12 15:53:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BD8BE7719E for ; Sun, 12 Jan 2025 15:55:58 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id BD3F76B009D; Sun, 12 Jan 2025 10:55:43 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id B11FA6B009C; Sun, 12 Jan 2025 10:55:43 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 42E5D6B009D; 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bh=BHBAIJk3kp5/hgDdQnghZ6LaG1R2na2fX2tkn+6lmL4=; b=PGFSIVDbiM2uHiCWtnIbLiQYXaSaxLwnvvW6WEv80JhtbUG0YC3iJsKh4WIufbXmp+jxmE wfhnmoG+B6kJFXc5Xc/rBZC2e4biSqVsZRnN6Hac3f/Bh91IYrctqwuWmSzzgEpIf7GYkf jwzLHYJO1pkmr/BgOE5ur78RcGY/vpY= ARC-Authentication-Results: i=1; imf20.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf20.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1736697341; a=rsa-sha256; cv=none; b=D86BQeEvER7g28wwqpYheitoIUprosx3f4Lk8+v2HnpQkZb44b40CAcR/lWRzmzoGD3zqR SUDmIkpqikbRiJC5ggmk5jhNP2A6ZeWIi/DS+k7ZkSWVM/ZN7Hp2/UK3j7f3eQMwuuC2kb AlSurd4js1N1tGBQWvas+kq+noNhBX8= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-3An5; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 07/12] x86/tlb: use INVLPGB in flush_tlb_all Date: Sun, 12 Jan 2025 10:53:51 -0500 Message-ID: <20250112155453.1104139-8-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 3846E1C000D X-Stat-Signature: s419hunatq61kdhboqt4ktcd47zncpuk X-Rspam-User: X-Rspamd-Server: rspam11 X-HE-Tag: 1736697341-677786 X-HE-Meta: U2FsdGVkX19rx9Q8EMZoOG63M2qBx01EwAuE19PHMVtQbtlNzwtOsgjRj+yJqq6mdnjPtOqYWzic+GK3XtDmw46P3qRRuL027cKWua5EaZQi2MOYbMrJ4V+b1pkEkC9W/ph6i91QUuB/3ZrCL/PBo8jCVtF8OR2m7KHGrEgFF1QYb0Nz4Kyhw4szfmi950IHUXmusZkkGva7PYgpDqjoHA4hE1e274H6H9f2VoPiUEbMKOXyy23EXWr0r+CDZ/JiqP+dc/bX2TVDrSiHg6PZ574JxVY5y+a1Un8zXGZ6liUwT/y+A7io6cAJGPy/+++UAMsrfG0ZMba4u/vy/fEeEDNKLij30NXd6tvyxWPmytZL7xkAmdOuFbFgvgSbXuukz4txXQ84yt+YXlmld4vL0TSW7mhKgTozJ75PNdhCaZ5uP1rqIvzHbsIofmMNo53/DchZamKx+ac2feOjsYMNldsp/RUTeUjPvhbQUNpKheDoM1/47IILh2Nj7bIR3X9cn0OK0WIbkE0gXBw1/dp81b0DeOTc0Q39dp8C5TbHJyZSmnTk9AwOURg4f3AM+96ikCT0yjOEvQ8qjqZn5H0fcq0faRORt39+P4LyHD77tyOJs6yZBSTaRWFWj4HxW2Zd11OX/ebOxEFNiYNIFD8IR41WRoTJvq5ibKRoUcUIOkct8ejEDjsqKHwyjoIhfZvoqYnOR6HgGYe3L4kHpGBZkF0QzGrOi9MKiwjHjjuwU/4iq+RTrsyRe7C9wlJsrJvJ5ln1x96bM14PH13D4OeU4gr8NUTLYZ4y4YKQBCmYP7RplcD+AKdUxXai8uDcTHjgaWtFE0xvNvlWx5sal5IZV+iJuzSFm6cala3XZdafwpnpxo4zEezAJWstDfnUhlHkmBdsRXugWfEDb32IzR8a5R5ErQVr3+mVPIzPcFr2aV4Y9Ynu89k1g3F4TfdTmk34Re0+SFMw4ArypODu/DO RWJItmVs BAgbIpw948TDZQOBoLrIk88tPM46EJAeq8cPjbMMrc7MegcSZwhhmF8ciA31Y56Fj4G2juDitWiDTwYMP+X2Df8ze9oE63Dqhn/2Jh5veqpewSkEVOn8sVGQ+9xtdPlV5A/VsFh5Gwb87XZKV4tk8RF7FQ/1JUgcK0qt8nrFwnghSSdaA9Z7E8jwR/C61VNs5R/FIg6InMv7S0S3Wm+Cw2p1UER+NPaMSacDOqTevln7t5Z0QXAY+It/r8iQz3aXYAqw6Zqa6TIBCe5R65vPlQ6q1T8ZThWFTJ4kyAqX9YuylB8ElkRbEbJTkHhjnRAAjimwDlOiGQ31DsdmzosthIw9UrdOOFbQuebexSLrKnXVLan48ZbahPx2DmaD3RMQ2amgFTv6MHyyYF+nH9e54ByZkOt1LIBYtRJUSwHO+Tt0+fRSIhOD69USRig== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The flush_tlb_all() function is not used a whole lot, but we might as well use broadcast TLB flushing there, too. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 45c7b84f6f80..56634c735351 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1065,6 +1065,18 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, } +static bool broadcast_flush_tlb_all(void) { + if (!IS_ENABLED(CONFIG_X86_BROADCAST_TLB_FLUSH)) + return false; + + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return false; + + guard(preempt)(); + invlpgb_flush_all(); + return true; +} + static void do_flush_tlb_all(void *info) { count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); @@ -1073,6 +1085,8 @@ static void do_flush_tlb_all(void *info) void flush_tlb_all(void) { + if (broadcast_flush_tlb_all()) + return; count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); on_each_cpu(do_flush_tlb_all, NULL, 1); } From patchwork Sun Jan 12 15:53:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E59FE7719C for ; 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d=hostedemail.com; t=1736697340; a=rsa-sha256; cv=none; b=WGJdM5nM5TjvFVBowMN0TX35IdhTQOsXajfp6Ax/wnoXrdO4hUv/b0jcLnfxsXJA5hiNHe 2Jss14OpiaBgCRghagyTe17nTn2tIgRXEu/bJPnKwtiRAM5zVieflwXsbVauZHLx46P5Hj qemUCaKeVppD2QZ/4/+SPaboLacgMxE= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-3G11; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Date: Sun, 12 Jan 2025 10:53:52 -0500 Message-ID: <20250112155453.1104139-9-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam05 X-Stat-Signature: oqfaxr4gz984urutoixrnj6qjc11tguw X-Rspamd-Queue-Id: 39BF4C0008 X-Rspam-User: X-HE-Tag: 1736697339-365709 X-HE-Meta: U2FsdGVkX19nUBOO6MoZ8c01DMhVmH4OV0exf6yqFdHRuV9C6ymabawutKwhQOxhQCI3anHj9TZA/ZnA0amPGo6I0WBK8erEo+bye4NxEwABYDDpda1T/veDo0ZY4pRP4M0ENH1sT+oER7N6D+qm7KYuYAjYGmKdmTNDP9EV/tuUvbonoRRBvNMm/MuVaNZNmr/rKyNnziKQiUnsfp5C6davWQ2m4ltMF+B4krYBLpPPTbFSYoJRCC3anAb/qJPP0tzkIJbDPRrcEgFgIfzxiVcSoWSfpAyaLpVcTIvEWIpdZfshmupDityB5pJeB5bFSGES+3Na7xIHCFLpURLxfQhfZRrPSIP1auOs3KMJj8gvGpzrL1oGu4EF0N26CLmYmG5POScjMRmtNbhte/MkIyTdPbcFDEAjFOJbWazr+eRPSVTT4/hgdeyNSpPGyNVK/yvebgomiaAAnYTkDe1SIMsgzJkXbQTIUepuuuDpsdKjrGiudHCTHasRr+mUitMDwNX8XRqd2AbtpCXB2PyyhMWD0IC2eLmWru/pMgsvhFVmmQCAjot8GeBBa89Co2u4acJ3sNJK4gL76hQCPNy+zn5O9g02asU3nAZftVfWx+O5yaRgjnIBsY31MTAawzA9LnqSW84rIHIzRg7Z8gEmcMY6J/QKMzSO3/dnuWqCOi4LDNbHBJf0wX3HN3oO8/i6j/xT+oCAXQ3p7WiRxA/W0qZeS9q9b1eLJHoBZZwKnp/FcnBwtskhTLZ9bp/XDC30tzEqTvoCrot/pTjAkcDjQyLkFTOFPEPbC2OpZ/8nQUE300KPdximNv8NYyhnNbtBAI0sukwTsuGgt8NtfMK7uK0Kx+HVUpDAAhzDsNtR6c5fFTDKmp1NSquVAq7TPPtmZKbMBTqcfeD4qXy98mQhIbCXbCWhYDL77rc2qWC4gWI8RxFppcZIebPtzQ69G0Jyx7uawNvhX4ZRUMdlcpZ ynDTVXJ5 1WbU1ssGd//z9ml8JWQ1WzdHq4NHyzR3zj0WPnW1vQRU4vRQEwbA0dJLbc+/VBk1xw8rGdvU/mBhz08xe8xBkXZpRjfvcRkcMdo3SY2KjYzrcmcqegUQaPrJcfz4WDinieNoPsW/9X6EgSm0F2ZoNdk01CdYMxMViRz9Wav190v5/h1eDkVG7f/lss6b8sgOV20/7OB9vxCS8Rspi6yxEDsd+5sRUhGdosuTqhYIReMQFaeb5WwZyXZ1Q8ETCuA1+9hFyJBnT+A9JPIfxZbDDtBQ8FMliygHUlsJmO9s+3EDDM9Vupb0CtcO1StRMEfYfnZ8m+KSwZJVmXcNB4PXX1BFwAwj7EED3IQm8CyPod10dF1Lbe/fmhgor1YZych3juUvKZZ6Z/pPrjEemaLLK0oMBsVmhcsuCzoj33DcX4n6VyME= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: In the page reclaim code, we only track the CPU(s) where the TLB needs to be flushed, rather than all the individual mappings that may be getting invalidated. Use broadcast TLB flushing when that is available. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 56634c735351..b47d6c3fe0af 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1319,7 +1319,9 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + invlpgb_flush_all_nonglobals(); + } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); From patchwork Sun Jan 12 15:53:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67C81E7719C for ; Sun, 12 Jan 2025 15:55:53 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 747546B008C; Sun, 12 Jan 2025 10:55:43 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 147896B0098; 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Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Date: Sun, 12 Jan 2025 10:53:53 -0500 Message-ID: <20250112155453.1104139-10-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: A38391C000C X-Stat-Signature: 6cx5xo3h4jqb853sc4cx8qmuyeexefeb X-Rspam-User: X-Rspamd-Server: rspam09 X-HE-Tag: 1736697340-489808 X-HE-Meta: U2FsdGVkX1/7+17/wNaHf9pifDFOo2I4rBil3tIJN4k7/zXI7RqD8HottDK0QsFZoMFSU+Memh35c/QVStbrxK7T6/V/sFygf692s58MleD5xdcjAfPHv5zs/ph2pN5qDvw8wVc/D9qn7AxlcnqrYfEmIC6JS3uKcAjmZIScj38GqSa8zackaWsqaQuLUfJhSX3bbRaVaDIXu+FX8ig7tuV2BD2H8QJMiMbwHjagbizT4ykYC+87NLpYpNYfkzyWxaqeHW/9I2iQxnyGUoPfpeC0djpd/9NiAYCKkcE7TF0W1uoGj1SslwsMSL/Yav0HbcESRymkOo1v5oDz/z8qWeUe6OIl96+zaIM12A+HWx0KwFu0uRBplIdPMbTcDZXtlWnR2nsXGujMor5EZ+2ouIjp5bAa3u0VpObO/2j9VIAjlc0pNKMDUI03/N5+aR/XjCoXBdKz0Iik5bezClAYxFUtYuG7fvH21Yb6VZcJhEIwH5ULV0UiyE0C7AoVQZFYljv7SF7FfzTVivI/R22nR2BWUomXsk//bt+y/M4NalTi18FH99KSeoD3WBVvPG3MhA76ncUNUhSiIWpbAMrle7d9Qmb9DjwsnB0um+Te/K3TlbK5LptGZsvoyJN/fjAWhK9EuuSpadwtpXMtxW/bcjDbtUdWJAXlYtjNpEtVyoq9V9RHtckTu52bfJpTf7NfpTD+i1kDmnb0aDtaWSDGbgdhCyTgLLDUkUZn2RNmnoKfZENsWNhwMBdUTmoE2i3ppd0Te6MVCJdp15RXqYvb0GEYuxNJX4urS+iUErPWdtMt6Hz35hMwlqkzU7hNqQXRs5jclNxnltpcBEwMhHIpZS549QbreiG6MErfcU0u3jJnQx2q+4TFFDvsL3i6J2T/jjW2M8avRf4c6XvY5ANWxShGOPflFQhgauQBuLYX8c2K4r3k50vaqZq5eb7nO2lyW57nOdx1H64wSQ66Z3K 98N2s+L3 pP/u/wVJjOAopzAOlKx78Y/UA2+LMTnsVRXdz8rf9cL4n6b0qH+SbSlPCh8M1wRbwya7EPxg9EeaaqQo/FGpeAt5UDvPGMtPUiIKvY7jal/JXWBw9qBTKs0LVV08DshOXsN2gKqV+qQyC4pOW/2OrTqWpuqzlEQhCH5/CvJeaEZxJ+wrR+XD3BmiT8x3WZ41Oxxt/kSrvhQXqTmMMdbd/Ty9YjOzSDFw97bZ/7brOZARxvNqm0GT/sIOkSqRxqVxFetIDoSrc8MKrZnNdukWQYLru01ZhkE7SxTvp3AMHls5gXWtCO7AhEvJckMSsMtPBguVzzY5SOBWaV6PYoq7IwCpABKMdnUoTR942z9tsB/Yf40l/bF3Ib7HmC4HyLgO7QCBV X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Use broadcast TLB invalidation, using the INVPLGB instruction, on AMD EPYC 3 and newer CPUs. In order to not exhaust PCID space, and keep TLB flushes local for single threaded processes, we only hand out broadcast ASIDs to processes active on 3 or more CPUs, and gradually increase the threshold as broadcast ASID space is depleted. Signed-off-by: Rik van Riel --- arch/x86/include/asm/mmu.h | 6 + arch/x86/include/asm/mmu_context.h | 14 ++ arch/x86/include/asm/tlbflush.h | 64 +++++ arch/x86/mm/tlb.c | 363 ++++++++++++++++++++++++++++- 4 files changed, 435 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 3b496cdcb74b..d71cd599fec4 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -69,6 +69,12 @@ typedef struct { u16 pkey_allocation_map; s16 execute_only_pkey; #endif + +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + u16 global_asid; + bool asid_transition; +#endif + } mm_context_t; #define INIT_MM_CONTEXT(mm) \ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index 795fdd53bd0a..d670699d32c2 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -139,6 +139,8 @@ static inline void mm_reset_untag_mask(struct mm_struct *mm) #define enter_lazy_tlb enter_lazy_tlb extern void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk); +extern void destroy_context_free_global_asid(struct mm_struct *mm); + /* * Init a new mm. Used on mm copies, like at fork() * and on mm's that are brand-new, like at execve(). @@ -161,6 +163,14 @@ static inline int init_new_context(struct task_struct *tsk, mm->context.execute_only_pkey = -1; } #endif + +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + mm->context.global_asid = 0; + mm->context.asid_transition = false; + } +#endif + mm_reset_untag_mask(mm); init_new_context_ldt(mm); return 0; @@ -170,6 +180,10 @@ static inline int init_new_context(struct task_struct *tsk, static inline void destroy_context(struct mm_struct *mm) { destroy_context_ldt(mm); +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) + destroy_context_free_global_asid(mm); +#endif } extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index dba5caa4a9f4..cd244cdd49dd 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -239,6 +239,70 @@ void flush_tlb_one_kernel(unsigned long addr); void flush_tlb_multi(const struct cpumask *cpumask, const struct flush_tlb_info *info); +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +static inline bool is_dyn_asid(u16 asid) +{ + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return true; + + return asid < TLB_NR_DYN_ASIDS; +} + +static inline bool is_global_asid(u16 asid) +{ + return !is_dyn_asid(asid); +} + +static inline bool in_asid_transition(const struct flush_tlb_info *info) +{ + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return false; + + return info->mm && info->mm->context.asid_transition; +} + +static inline u16 mm_global_asid(struct mm_struct *mm) +{ + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return 0; + + return mm->context.global_asid; +} +#else +static inline bool is_dyn_asid(u16 asid) +{ + return true; +} + +static inline bool is_global_asid(u16 asid) +{ + return false; +} + +static inline bool in_asid_transition(const struct flush_tlb_info *info) +{ + return false; +} + +static inline u16 mm_global_asid(struct mm_struct *mm) +{ + return 0; +} + +static inline bool needs_global_asid_reload(struct mm_struct *next, u16 prev_asid) +{ + return false; +} + +static inline void broadcast_tlb_flush(struct flush_tlb_info *info) +{ +} + +static inline void consider_global_asid(struct mm_struct *mm) +{ +} +#endif + #ifdef CONFIG_PARAVIRT #include #endif diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index b47d6c3fe0af..80375ef186d5 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -74,13 +74,15 @@ * use different names for each of them: * * ASID - [0, TLB_NR_DYN_ASIDS-1] - * the canonical identifier for an mm + * the canonical identifier for an mm, dynamically allocated on each CPU + * [TLB_NR_DYN_ASIDS, MAX_ASID_AVAILABLE-1] + * the canonical, global identifier for an mm, identical across all CPUs * - * kPCID - [1, TLB_NR_DYN_ASIDS] + * kPCID - [1, MAX_ASID_AVAILABLE] * the value we write into the PCID part of CR3; corresponds to the * ASID+1, because PCID 0 is special. * - * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS] + * uPCID - [2048 + 1, 2048 + MAX_ASID_AVAILABLE] * for KPTI each mm has two address spaces and thus needs two * PCID values, but we can still do with a single ASID denomination * for each mm. Corresponds to kPCID + 2048. @@ -225,6 +227,19 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, return; } + /* + * TLB consistency for global ASIDs is maintained with broadcast TLB + * flushing. The TLB is never outdated, and does not need flushing. + */ + if (IS_ENABLED(CONFIG_X86_BROADCAST_TLB_FLUSH) && static_cpu_has(X86_FEATURE_INVLPGB)) { + u16 global_asid = mm_global_asid(next); + if (global_asid) { + *new_asid = global_asid; + *need_flush = false; + return; + } + } + if (this_cpu_read(cpu_tlbstate.invalidate_other)) clear_asid_other(); @@ -251,6 +266,292 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, *need_flush = true; } +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +/* + * Logic for broadcast TLB invalidation. + */ +static DEFINE_RAW_SPINLOCK(global_asid_lock); +static u16 last_global_asid = MAX_ASID_AVAILABLE; +static DECLARE_BITMAP(global_asid_used, MAX_ASID_AVAILABLE) = { 0 }; +static DECLARE_BITMAP(global_asid_freed, MAX_ASID_AVAILABLE) = { 0 }; +static int global_asid_available = MAX_ASID_AVAILABLE - TLB_NR_DYN_ASIDS - 1; + +static void reset_global_asid_space(void) +{ + lockdep_assert_held(&global_asid_lock); + + /* + * A global TLB flush guarantees that any stale entries from + * previously freed global ASIDs get flushed from the TLB + * everywhere, making these global ASIDs safe to reuse. + */ + invlpgb_flush_all_nonglobals(); + + /* + * Clear all the previously freed global ASIDs from the + * broadcast_asid_used bitmap, now that the global TLB flush + * has made them actually available for re-use. + */ + bitmap_andnot(global_asid_used, global_asid_used, + global_asid_freed, MAX_ASID_AVAILABLE); + bitmap_clear(global_asid_freed, 0, MAX_ASID_AVAILABLE); + + /* + * ASIDs 0-TLB_NR_DYN_ASIDS are used for CPU-local ASID + * assignments, for tasks doing IPI based TLB shootdowns. + * Restart the search from the start of the global ASID space. + */ + last_global_asid = TLB_NR_DYN_ASIDS; +} + +static u16 get_global_asid(void) +{ + lockdep_assert_held(&global_asid_lock); + + do { + u16 start = last_global_asid; + u16 asid = find_next_zero_bit(global_asid_used, MAX_ASID_AVAILABLE, start); + + if (asid >= MAX_ASID_AVAILABLE) { + reset_global_asid_space(); + continue; + } + + /* Claim this global ASID. */ + __set_bit(asid, global_asid_used); + last_global_asid = asid; + return asid; + } while (1); +} + +/* + * Returns true if the mm is transitioning from a CPU-local ASID to a global + * (INVLPGB) ASID, or the other way around. + */ +static bool needs_global_asid_reload(struct mm_struct *next, u16 prev_asid) +{ + u16 global_asid = mm_global_asid(next); + + if (global_asid && prev_asid != global_asid) + return true; + + if (!global_asid && is_global_asid(prev_asid)) + return true; + + return false; +} + +void destroy_context_free_global_asid(struct mm_struct *mm) +{ + if (!mm->context.global_asid) + return; + + guard(raw_spinlock_irqsave)(&global_asid_lock); + + /* The global ASID can be re-used only after flush at wrap-around. */ + __set_bit(mm->context.global_asid, global_asid_freed); + + mm->context.global_asid = 0; + global_asid_available++; +} + +/* + * Check whether a process is currently active on more than "threshold" CPUs. + * This is a cheap estimation on whether or not it may make sense to assign + * a global ASID to this process, and use broadcast TLB invalidation. + */ +static bool mm_active_cpus_exceeds(struct mm_struct *mm, int threshold) +{ + int count = 0; + int cpu; + + /* This quick check should eliminate most single threaded programs. */ + if (cpumask_weight(mm_cpumask(mm)) <= threshold) + return false; + + /* Slower check to make sure. */ + for_each_cpu(cpu, mm_cpumask(mm)) { + /* Skip the CPUs that aren't really running this process. */ + if (per_cpu(cpu_tlbstate.loaded_mm, cpu) != mm) + continue; + + if (per_cpu(cpu_tlbstate_shared.is_lazy, cpu)) + continue; + + if (++count > threshold) + return true; + } + return false; +} + +/* + * Assign a global ASID to the current process, protecting against + * races between multiple threads in the process. + */ +static void use_global_asid(struct mm_struct *mm) +{ + guard(raw_spinlock_irqsave)(&global_asid_lock); + + /* This process is already using broadcast TLB invalidation. */ + if (mm->context.global_asid) + return; + + /* The last global ASID was consumed while waiting for the lock. */ + if (!global_asid_available) + return; + + /* + * The transition from IPI TLB flushing, with a dynamic ASID, + * and broadcast TLB flushing, using a global ASID, uses memory + * ordering for synchronization. + * + * While the process has threads still using a dynamic ASID, + * TLB invalidation IPIs continue to get sent. + * + * This code sets asid_transition first, before assigning the + * global ASID. + * + * The TLB flush code will only verify the ASID transition + * after it has seen the new global ASID for the process. + */ + WRITE_ONCE(mm->context.asid_transition, true); + WRITE_ONCE(mm->context.global_asid, get_global_asid()); + + global_asid_available--; +} + +/* + * Figure out whether to assign a global ASID to a process. + * We vary the threshold by how empty or full global ASID space is. + * 1/4 full: >= 4 active threads + * 1/2 full: >= 8 active threads + * 3/4 full: >= 16 active threads + * 7/8 full: >= 32 active threads + * etc + * + * This way we should never exhaust the global ASID space, even on very + * large systems, and the processes with the largest number of active + * threads should be able to use broadcast TLB invalidation. + */ +#define HALFFULL_THRESHOLD 8 +static bool meets_global_asid_threshold(struct mm_struct *mm) +{ + int avail = global_asid_available; + int threshold = HALFFULL_THRESHOLD; + + if (!avail) + return false; + + if (avail > MAX_ASID_AVAILABLE * 3 / 4) { + threshold = HALFFULL_THRESHOLD / 4; + } else if (avail > MAX_ASID_AVAILABLE / 2) { + threshold = HALFFULL_THRESHOLD / 2; + } else if (avail < MAX_ASID_AVAILABLE / 3) { + do { + avail *= 2; + threshold *= 2; + } while ((avail + threshold) < MAX_ASID_AVAILABLE / 2); + } + + return mm_active_cpus_exceeds(mm, threshold); +} + +static void consider_global_asid(struct mm_struct *mm) +{ + if (!static_cpu_has(X86_FEATURE_INVLPGB)) + return; + + /* Check every once in a while. */ + if ((current->pid & 0x1f) != (jiffies & 0x1f)) + return; + + if (meets_global_asid_threshold(mm)) + use_global_asid(mm); +} + +static void finish_asid_transition(struct flush_tlb_info *info) +{ + struct mm_struct *mm = info->mm; + int bc_asid = mm_global_asid(mm); + int cpu; + + if (!READ_ONCE(mm->context.asid_transition)) + return; + + for_each_cpu(cpu, mm_cpumask(mm)) { + /* + * The remote CPU is context switching. Wait for that to + * finish, to catch the unlikely case of it switching to + * the target mm with an out of date ASID. + */ + while (READ_ONCE(per_cpu(cpu_tlbstate.loaded_mm, cpu)) == LOADED_MM_SWITCHING) + cpu_relax(); + + if (READ_ONCE(per_cpu(cpu_tlbstate.loaded_mm, cpu)) != mm) + continue; + + /* + * If at least one CPU is not using the global ASID yet, + * send a TLB flush IPI. The IPI should cause stragglers + * to transition soon. + * + * This can race with the CPU switching to another task; + * that results in a (harmless) extra IPI. + */ + if (READ_ONCE(per_cpu(cpu_tlbstate.loaded_mm_asid, cpu)) != bc_asid) { + flush_tlb_multi(mm_cpumask(info->mm), info); + return; + } + } + + /* All the CPUs running this process are using the global ASID. */ + WRITE_ONCE(mm->context.asid_transition, false); +} + +static void broadcast_tlb_flush(struct flush_tlb_info *info) +{ + bool pmd = info->stride_shift == PMD_SHIFT; + unsigned long maxnr = invlpgb_count_max; + unsigned long asid = info->mm->context.global_asid; + unsigned long addr = info->start; + unsigned long nr; + + /* Flushing multiple pages at once is not supported with 1GB pages. */ + if (info->stride_shift > PMD_SHIFT) + maxnr = 1; + + /* + * TLB flushes with INVLPGB are kicked off asynchronously. + * The inc_mm_tlb_gen() guarantees page table updates are done + * before these TLB flushes happen. + */ + if (info->end == TLB_FLUSH_ALL) { + invlpgb_flush_single_pcid_nosync(kern_pcid(asid)); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_single_pcid_nosync(user_pcid(asid)); + } else do { + /* + * Calculate how many pages can be flushed at once; if the + * remainder of the range is less than one page, flush one. + */ + nr = min(maxnr, (info->end - addr) >> info->stride_shift); + nr = max(nr, 1); + + invlpgb_flush_user_nr_nosync(kern_pcid(asid), addr, nr, pmd); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), addr, nr, pmd); + addr += nr << info->stride_shift; + } while (addr < info->end); + + finish_asid_transition(info); + + /* Wait for the INVLPGBs kicked off above to finish. */ + tlbsync(); +} +#endif /* CONFIG_X86_BROADCAST_TLB_FLUSH */ + /* * Given an ASID, flush the corresponding user ASID. We can delay this * until the next time we switch to it. @@ -556,8 +857,9 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ if (prev == next) { /* Not actually switching mm's */ - VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != - next->context.ctx_id); + VM_WARN_ON(is_dyn_asid(prev_asid) && + this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != + next->context.ctx_id); /* * If this races with another thread that enables lam, 'new_lam' @@ -573,6 +875,23 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); + /* + * Check if the current mm is transitioning to a new ASID. + */ + if (needs_global_asid_reload(next, prev_asid)) { + next_tlb_gen = atomic64_read(&next->context.tlb_gen); + + choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); + goto reload_tlb; + } + + /* + * Broadcast TLB invalidation keeps this PCID up to date + * all the time. + */ + if (is_global_asid(prev_asid)) + return; + /* * If the CPU is not in lazy TLB mode, we are just switching * from one thread in a process to another thread in the same @@ -606,6 +925,13 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ cond_mitigation(tsk); + /* + * Let nmi_uaccess_okay() and finish_asid_transition() + * know that we're changing CR3. + */ + this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); + barrier(); + /* * Leave this CPU in prev's mm_cpumask. Atomic writes to * mm_cpumask can be expensive under contention. The CPU @@ -620,14 +946,12 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, next_tlb_gen = atomic64_read(&next->context.tlb_gen); choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); - - /* Let nmi_uaccess_okay() know that we're changing CR3. */ - this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); - barrier(); } +reload_tlb: new_lam = mm_lam_cr3_mask(next); if (need_flush) { + VM_BUG_ON(is_global_asid(new_asid)); this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); load_new_mm_cr3(next->pgd, new_asid, new_lam, true); @@ -746,7 +1070,7 @@ static void flush_tlb_func(void *info) const struct flush_tlb_info *f = info; struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); - u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + u64 local_tlb_gen; bool local = smp_processor_id() == f->initiating_cpu; unsigned long nr_invalidate = 0; u64 mm_tlb_gen; @@ -769,6 +1093,16 @@ static void flush_tlb_func(void *info) if (unlikely(loaded_mm == &init_mm)) return; + /* Reload the ASID if transitioning into or out of a global ASID */ + if (needs_global_asid_reload(loaded_mm, loaded_mm_asid)) { + switch_mm_irqs_off(NULL, loaded_mm, NULL); + loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); + } + + /* Broadcast ASIDs are always kept up to date with INVLPGB. */ + if (is_global_asid(loaded_mm_asid)) + return; + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) != loaded_mm->context.ctx_id); @@ -786,6 +1120,8 @@ static void flush_tlb_func(void *info) return; } + local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID && f->new_tlb_gen <= local_tlb_gen)) { /* @@ -953,7 +1289,7 @@ STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask, * up on the new contents of what used to be page tables, while * doing a speculative memory access. */ - if (info->freed_tables) + if (info->freed_tables || in_asid_transition(info)) on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true); else on_each_cpu_cond_mask(should_flush_tlb, flush_tlb_func, @@ -1049,9 +1385,12 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { + if (mm_global_asid(mm)) { + broadcast_tlb_flush(info); + } else if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { info->trim_cpumask = should_trim_cpumask(mm); flush_tlb_multi(mm_cpumask(mm), info); + consider_global_asid(mm); } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) { lockdep_assert_irqs_enabled(); local_irq_disable(); From patchwork Sun Jan 12 15:53:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06B6CE77188 for ; Sun, 12 Jan 2025 15:55:48 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 1BC386B0092; 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dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-3ULi; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Date: Sun, 12 Jan 2025 10:53:54 -0500 Message-ID: <20250112155453.1104139-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 66B7140016 X-Stat-Signature: wg98pu34173yi4446ojrzkty9r1iz8y7 X-Rspam-User: X-HE-Tag: 1736697340-203948 X-HE-Meta: U2FsdGVkX1+3cfHkXVT5POqwJNjapY82bv3nSRgDmPgDR6uccNlAAImXV/UY3EFLIThegZok19MEhEqoHao4SfCJV3+KnN6lQViMDsPc4MsRoNCJkiEc/N162mQbSuhe2M5C7kCk3dSTLz1ytO+DJAa+yWWnvAdZH09LOEV1cVoQa3WtU2ar9zBWUsX1+kBgS8xbiHV4kLFkcpK57meF4QmRdu2fAInkvTmH+XeneAU6lBASstT+daODwz3c/JS3tNaAS/tZVXp92SgL8NdegpxTnUbhgxCmXXYlS+HlDrriLt19WVIMkLWvYxvhXqcSw+Z2k2F6alwqiXPr640heprKbM5/TFinsMKoagSZflsguykE2Btn7bCM0yTTYJTO7Xt2Asy3OV79DklcF9PSPC7Koxd8oIAeW4uZQ9fRhVfnOLVVEEw4HMAhSbusqa+aj8OJVk6420h84+HUG6/03mKmI/GnawigpT8xxs8fkuzxJnfv3lQ+zVk+VuGw6dljoKokDIYEuxMJ5J53N38zuN5c1odSF3YEAi7RBdd6iKXVbGcDFOeZYLp1M332Okddt99h/Z17ZvB6mL9Hq13SBRKzc2Ih73UgQo/Z0Hlx1okyWkWyOEaHaJrPVfcl54+XkYrPwc1XEn2Rq1aIFy5VBZKNoyeqS8SdXRAW1zNbRX8FQaKQz44i5Et4UcZp1NHY5yyqzZXYrvW0pvK69He3C2fs4IQfU9YKxkZd9cqrD9UeUEgiJktOTrbVPvzcpgN651a6KVEuWZsvN3uRkAxouoOrSofTBhvTHlURo3wsxju03SFJQyVFZfHboZiJWSJ4iO6fJJrAnr5vMV42KDOPuami3/vlPuoa9b4HjjOsd+VgVAujDqZLJm1RyY7NkPk35xdObqOUnccpqdr3zQSlU3qORhE0B6h3CmplXm1nGwKwv6Fzk0CPUfrx5YcVIg5ZwR7EP+Dzp6T3huknl7s rkizTj0m 58SymvhJoHxvw0Pnz15WUnJyeMuO3O6jBuklGXGYwrbExwott2+1FKBGFWIa5rvvGxvMO3vPN6irSkNR0HyZfZBZ2bth69Fs/epTSJbjjgk3WyGIETcnZA5PHIFh+/HJ4lP5SOmb4SqcjIduidr0pZavpkgXI+pcvt3hiU0l7GTFC62q1JEpNXZ0KKsuX5LJUfu1kgIm+rzD+NHrSJGtFoFV84v64CVqAEJs0z7jIsDgxtr/Ifsnc7TT2dPJZM1VBW507omvpPCTMPavxccde3fqr5ZuRBffIp8SLE75KqE42gpizRvtFxOiBVlF/2zLjiNbOe+HAt+B5y/b+rsRXFnwsPP9ufjT+j4nkZV+AZ17KRaj5z6dvw97g0zKXndUIkJcoqpdSeG+WJjPDXxG1tUntywyrLhxxDp7OsUz0L53r+HY= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbbatch.h | 1 + arch/x86/include/asm/tlbflush.h | 12 +++------- arch/x86/mm/tlb.c | 41 ++++++++++++++++++++++++++++++--- 3 files changed, 42 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/tlbbatch.h b/arch/x86/include/asm/tlbbatch.h index 1ad56eb3e8a8..f9a17edf63ad 100644 --- a/arch/x86/include/asm/tlbbatch.h +++ b/arch/x86/include/asm/tlbbatch.h @@ -10,6 +10,7 @@ struct arch_tlbflush_unmap_batch { * the PFNs being flushed.. */ struct cpumask cpumask; + bool used_invlpgb; }; #endif /* _ARCH_X86_TLBBATCH_H */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index cd244cdd49dd..fa4fcafa8b87 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -350,21 +350,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 80375ef186d5..532911fbb12a 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1658,9 +1658,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1669,12 +1667,49 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB) && batch->used_invlpgb) { + tlbsync(); + migrate_enable(); + batch->used_invlpgb = false; + } + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm_global_asid(mm)) { + u16 asid = mm_global_asid(mm); + /* + * Queue up an asynchronous invalidation. The corresponding + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done + * on the same CPU. + */ + if (!batch->used_invlpgb) { + batch->used_invlpgb = true; + migrate_disable(); + } + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + } else { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or From patchwork Sun Jan 12 15:53:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43922E77188 for ; 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imf15.hostedemail.com; dkim=none; spf=pass (imf15.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-3Zr1; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 11/12] x86/mm: enable AMD translation cache extensions Date: Sun, 12 Jan 2025 10:53:55 -0500 Message-ID: <20250112155453.1104139-12-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 8C4DBA000C X-Stat-Signature: 4x69sj989rx4ku6d3amkjjntf49uqewq X-Rspam-User: X-HE-Tag: 1736697940-290629 X-HE-Meta: U2FsdGVkX187vFX/0dYOmI3LQHM6+zPbCIo+Ym8TUEHgcQwvbsCc3W+1g7d7ExoCKV9dCz/p2NaqyZNVCWjZTjEOeqU6ZVbJKFFfckZrtlPnxTFYiRPKJ/AscEtEg8dZLRgTP07hQM1x/Yl6fLbrqb6ilyv0SPDA1R0v1kkDFdU2dsJu3qTEHDiNBcTwYU3y+P3B2Vhp2Txar4eSqWSbGA1GfoNLOqpiovGZe0CR8dYPCf+MSxgySsUkSlJG6ph3pn/ZlOOFvy63mBfgAO2RuZAA6MrmpCBJTmte0EIMVBDEEBCXki9BTJhxUHjZh8a7bPHI8i6aP/jTFtO9kJyLzo+R2oLCGWZ+8/dMOOOEWvHhdS4/OpQZKafg7fwsuuPIZRJPgVySJDaCp9TqoVI39xCa6JP4SX+lP+sjXm77spJ6WeRY0XObdg5KSdK97hg6Swt/s9nJ10qD0fG/7RVJ/aU0tgq2l3mfqsiRE6NwjS65nTs20vUFjUb9mswXsAePKKACnPoidPNSFU2Lr3NmJXct1/Cacyj7ldJrlxfBs/dBUwyyuPJxnrFPwQWNEI+d6lnaP7NM5SWbGRwuF2f2CkDWTwkNtPWZML42KnUfPAY36jKaVj+3vfJJXVF7IWMiX1guvnsh9xx8zkWXH+mXK+U+mrtTQZzfScThINM6ghLrLb6BzeKapYrBYYUgko7db7vKykNqF30ZZHlKR0fNGDzxg2nXOZg6iYHkNfBYyGgI9ItLMvypRKe/JCwJuyd9VmSlRs8uevxtn7mP7zaAezOBmVW7SXv7hVzB/d1h1bmhW1zkWwkeQdKMDaEcqIo7Bn1+ycdsQ7cS7puqJ+2EQv8CYZVsbqpZFrxHM65Qw2mib846/UI24sMFy/33m8rwM1sWZFNVJeoqS/htKm8bj3pNzzhsIlEN6GKyciYkNpT9x00HXPDAY+H/eerlBZRp1Lugpsime/m9Z4asGPj U6zwmboW iO/T5tDXdWUekYHw7GKGqjTPTMX9eZaXxLsaDyQkHU6qVmiOmHCgJBKcvF4+0Lff8Q6+vNBnOHJJ1q1jcu0WgeeiXT5NM9rBjx9U30Z7ObGfk9gwLEP+aI57DTWdz+dTufBKB8AzK1+R8kia7TctHQN4SoGWYrHo8TXM5b1HBCSwlQa3Nr42SetW/DhCMtx5Ztp7rqE+3YdfAMwt8t9gtWWoPOOc2YcCXy2wq2fMmp2wASwpfqk/yFGklTnINTE52PI8D5L+heedO+djBgLolXaiHCJmPwNAcxu91lJ1O5GgyH359uEF+r8HeDt6YWu/VSZ3Y+UhSEcS3waFTkJ7lG4bcsh/dChE9tMsDCKuk7Rw52jgAXJ3GfY1G938borunV9kF X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidation. This can help reduce the TLB miss rate, by keeping more intermediate mappings in the cache. From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. Signed-off-by: Rik van Riel --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 3 +++ tools/arch/x86/include/asm/msr-index.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..dc1c1057f26e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bcf73775b4f8..b7e84d43a22d 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1071,6 +1071,9 @@ static void init_amd(struct cpuinfo_x86 *c) /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); + + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) + msr_set_bit(MSR_EFER, _EFER_TCE); } #ifdef CONFIG_X86_32 diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..dc1c1057f26e 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* From patchwork Sun Jan 12 15:53:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13936443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE66DE7719E for ; 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imf23.hostedemail.com; dkim=none; spf=pass (imf23.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tX0Ii-0000000010W-3fnO; Sun, 12 Jan 2025 10:54:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, Rik van Riel Subject: [PATCH v4 12/12] x86/mm: only invalidate final translations with INVLPGB Date: Sun, 12 Jan 2025 10:53:56 -0500 Message-ID: <20250112155453.1104139-13-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112155453.1104139-1-riel@surriel.com> References: <20250112155453.1104139-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 8C7D1140002 X-Stat-Signature: upwc5y4tywef5nxuwz9udipd5fa35tx8 X-Rspam-User: X-HE-Tag: 1736697340-107169 X-HE-Meta: U2FsdGVkX1+zCnBTIqdGiQtZTGspuh7+6VZSXKH4W4L6GEq6fqtoFixRaGlbJQmCH+VpRa5DnNGm0KTK489Ap0wE0KEvJANbMGbq0O1UH2k+ZqSDZGKoP0FBfIyQ6luqU+fjl8H1GdZc79Hl0KS/KkXF+yr4h/jWmJr1fUek7S9dGopcCrBY3llFRCosmUPRhAzaj6iJXUyCsYSclF88PpdNNs+O/KuTBPkaJ2OLA08nmZZTYHjc3HJngg6Den4wFgyu/gQypzA903XTWXo9EQGFnDst3yMmT1tnYZY7MDWYPVfNfKALiPvG66/1wpvXyK6vzEWCMjrSYXW4eM0pikmbCqCHbKonH+SGnEjhWO0R6pV4uaaX/wkzCLl/vf0grlb/8l3UZEgBXAt82viVDldKNKaGE5YrluGtmsKd6JLA753n0l4sOB8CcPVMqDtz5S1cGdHjgra553vmPfBZKRN97swnLoowPE9mbCfVf8MuHUF0k5jnvV9UMFKF413f18RKVtfA8BTc+tNY8mcjpsv4ykimIAa7WL4mJKiddDeQPTVocRwpKcWGkzww7RBtoQKF8a0QbeP9wnbJKCFuHgVTNCWZVZ19gXuwYRF2EMInVl3qlFzI/wuT59N6EcX9XWXfZxn8oNI/Mw244GhSdmvdXb27fTT2vThSEwwwTHCaS3uG1z7DMQpsS0lKHJi7+5P/N3gm3pOqhRJeQl+B+wH9qQKnUfpHWiaY+BpW7lrkEl6Gy02MwEyqyOC+z5beHssblxEFoICLo17g1qTHs3fPUzs+sk6E9JsHHb6FIXloabPipcUtfmtYP+TWd8LA6LWM4Bxw74atx8ZlkIywgCvmXuB+ciKJKcsLusY8h94B8JSt+tNOw+0D7vZH/k/11pHsSZS8mn1yVtzLx9O7G8TiIqOKnFRgC30/UhQRQeZzsSQ49hSDjbvMuOaE6QE0Lfvl5nJZdkUvYBvjLZR ULWg8eYt kGs955zJkaVrmWQ317qMTz4VTtvAKxgZutTPERmYyR9Lc3WTYMt8MwVnaXlXrKe8VAuqJVO8zgB/Sse5315AcFT4B5OR9NvjjwARa6Gue/kwCIGK4FmtxdH0uX91FrlzDXyWqEGbCtvwqQNM7BCftsQMFe5nLgAgT9BhmXBPpPlXrCF1WAYrIFN0psapJ6LdCl56OFtPZKWhwLqfSQihUDE1g21K75H571wv/i+vCIuqyE0UkyyvH+IagDo8iJYZF63suK6Lc+3IxabPjecxu7M8bulqZO2ePgKkxhQaEBGPNe9KcWuWXjIRDnHmwRONV8loawVL7H8rmOtIcFMDXOgY0dH261QkMRCRu2RzodfTpVKCqFEelN76Cb3zyxeDkT1GqA6Trz0HvNjw= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Use the INVLPGB_FINAL_ONLY flag when invalidating mappings with INVPLGB. This way only leaf mappings get removed from the TLB, leaving intermediate translations cached. On the (rare) occasions where we free page tables we do a full flush, ensuring intermediate translations get flushed from the TLB. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 10 ++++++++-- arch/x86/mm/tlb.c | 8 ++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h index d62e3733a1ab..4fa48d063b76 100644 --- a/arch/x86/include/asm/invlpgb.h +++ b/arch/x86/include/asm/invlpgb.h @@ -61,9 +61,15 @@ static inline void invlpgb_flush_user(unsigned long pcid, static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, unsigned long addr, - int nr, bool pmd_stride) + int nr, bool pmd_stride, + bool freed_tables) { - __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); + unsigned long flags = INVLPGB_PCID | INVLPGB_VA; + + if (!freed_tables) + flags |= INVLPGB_FINAL_ONLY; + + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, flags); } /* Flush all mappings for a given PCID, not including globals. */ diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 532911fbb12a..0254e9ebaf15 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -538,10 +538,10 @@ static void broadcast_tlb_flush(struct flush_tlb_info *info) nr = min(maxnr, (info->end - addr) >> info->stride_shift); nr = max(nr, 1); - invlpgb_flush_user_nr_nosync(kern_pcid(asid), addr, nr, pmd); + invlpgb_flush_user_nr_nosync(kern_pcid(asid), addr, nr, pmd, info->freed_tables); /* Do any CPUs supporting INVLPGB need PTI? */ if (static_cpu_has(X86_FEATURE_PTI)) - invlpgb_flush_user_nr_nosync(user_pcid(asid), addr, nr, pmd); + invlpgb_flush_user_nr_nosync(user_pcid(asid), addr, nr, pmd, info->freed_tables); addr += nr << info->stride_shift; } while (addr < info->end); @@ -1699,10 +1699,10 @@ void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, batch->used_invlpgb = true; migrate_disable(); } - invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false, false); /* Do any CPUs supporting INVLPGB need PTI? */ if (static_cpu_has(X86_FEATURE_PTI)) - invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false, false); } else { inc_mm_tlb_gen(mm); cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));