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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e37d0casm10891447f8f.11.2025.01.12.16.47.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:47:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 01/23] hw/mips/cps: Keep reference of vCPUs in MIPSCPSState Date: Mon, 13 Jan 2025 01:47:26 +0100 Message-ID: <20250113004748.41658-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When a QOM object create children with object_new(), it is better to keep reference to them for further use. In particular, this allow to remove one global &first_cpu use. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/cps.h | 1 + hw/mips/cps.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 05ef9f76b74..0968b57c5a0 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -40,6 +40,7 @@ struct MIPSCPSState { char *cpu_type; bool cpu_is_bigendian; + MIPSCPU **cpus; MemoryRegion container; MIPSGCRState gcr; MIPSGICState gic; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 293b405b965..494213b2ab6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -73,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) return; } + s->cpus = g_new(MIPSCPU *, s->num_vp); for (int i = 0; i < s->num_vp; i++) { MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); CPUMIPSState *env = &cpu->env; @@ -91,6 +92,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { return; } + s->cpus[i] = cpu; /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -146,7 +148,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); /* Global Configuration Registers */ - gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; + gcr_base = s->cpus[0]->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, From patchwork Mon Jan 13 00:47:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 362D5E77188 for ; Mon, 13 Jan 2025 00:49:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8cq-0004OC-83; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e8bea5sm160710605e9.31.2025.01.12.16.48.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 02/23] hw/mips/malta: Check CPU index instead of using &first_cpu Date: Mon, 13 Jan 2025 01:47:27 +0100 Message-ID: <20250113004748.41658-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since create_cpu_without_cps() creates the vCPUs iterating up to the machine SMP count, it knows the first CPU is created upon the first iteration, at index #0 :) Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4e9cccaa347..37be2330eda 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1042,12 +1042,13 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); - } - cpu = MIPS_CPU(first_cpu); - env = &cpu->env; - *i8259_irq = env->irq[2]; - *cbus_irq = env->irq[4]; + if (i == 0) { + env = &cpu->env; + *i8259_irq = env->irq[2]; + *cbus_irq = env->irq[4]; + } + } } static void create_cps(MachineState *ms, MaltaState *s, From patchwork Mon Jan 13 00:47:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65BABE7719F for ; Mon, 13 Jan 2025 00:49:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8cp-0004NJ-A2; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e8bea5sm160712395e9.31.2025.01.12.16.48.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 03/23] hw/mips/boston: Replace bl_gen_write_ulong() -> bl_gen_write_u64() Date: Mon, 13 Jan 2025 01:47:28 +0100 Message-ID: <20250113004748.41658-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "exec/hwaddr.h" defines: typedef uint64_t hwaddr; typedef struct MemMapEntry { hwaddr base; hwaddr size; } MemMapEntry; Since MemMapEntry::base is always of type uint64_t, we can directly use bl_gen_write_u64(). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 67044af962a..63dc654192a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -329,20 +329,20 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_CM].base); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, - boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); + bl_gen_write_u64(&p, regaddr, + boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* * Setup argument registers to follow the UHI boot protocol: From patchwork Mon Jan 13 00:47:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76E0FE77188 for ; Mon, 13 Jan 2025 00:49:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8cw-0004PK-5t; Sun, 12 Jan 2025 19:48:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8cu-0004Ov-Ep for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:20 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8cs-0000iw-FG for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:20 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-38a88ba968aso3123126f8f.3 for ; Sun, 12 Jan 2025 16:48:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729296; x=1737334096; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RaLd62FWqL+hLOLg3wMqHXBcHhygEQ6lOnbn557VnfU=; b=Bln4nT2gsqnj45JuwV7gPFg04XHta5A9o5MiNyFZpTdBRqdmAHimdTVRJDR76xKwQh GrQepBwijvx8jbZPS/w4LnvNZ5R7tZ5omTydP6qziEDia4Oq/HOl+gWjFhOWs2uWSi8Z S3uGq2VezZ+Lok6o/KdeZs98b9M53Szk9Yk0dcl8NI/gv3/K4tR7LPLPAI4u2ggFrVho 09/akvmXYR4k1esyCZ/MW1h49ZdkNguFR0aWNipUxyjg+tNy994BMvBZ5It0wc7QR817 F6nW/kOQhXClITrEGI0Evzka7w288HQk/XBoeM0kbRNVZ4ej6zLfTB9IHKRpZtJoZbJt HcTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729296; x=1737334096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RaLd62FWqL+hLOLg3wMqHXBcHhygEQ6lOnbn557VnfU=; b=fpeVwLn6dcYuh+3fmK70Wo4N7+m5yGKQTc6dxy1SkPywn0rvx1iuM9URF43rb9iaBA 1G8jh2vVthax4e6WIQ/+qEzhczRgReUR3YVgZGbI0ACbXG5VzCcDrsDXwwlwiJ6yDyM7 Or58vEM7xefgpu6ei2qkcax8Ook70s4eLx8SHmx5kRVMn0UjasEJjOaoQLbzMELEmAac 9aje1U6KnYQ5nE0vU7F3PZPp/SbrcWWMl3U7yAMMQuunDtta2OIv2AyYc8qM+3UmQSDK 6gwp0M00QdcT7oUOvmj7hx7di+S0saPfNMKs6K6wDY+f5LS7GpqdwkbUwigIDMLaqJRR qLVw== X-Gm-Message-State: AOJu0Yy2Klvf9FW1n+HU4JoHzWPymow/iZRzi2mTI8nLETlsq9csbJ4c fHKkp+7izu0DLKBXryl6lVKtYfz2SogF3aDf73mUq8waQpnjBDu4dCwBr6TzKJO/neE/r1Cdx51 xLZw= X-Gm-Gg: ASbGncuZsa7PWuezldNeoqWA/QckIvj1x947jUyfPVfJspR+rq8HvvmoVk9nNeAY6jE HqkooXrE2XiiDDOaHcKfuAe/6+D5lI+QiWfu40TnfrD1E4hUXbM3ylfK0QlKTcg4ZLVyCA+ZQ+/ 8IJQSEBFz1j2tnWYv/ZQkxvvPMOrq+4C7+oHOwX2T32hSU+tZUeMenQ1xtrevWWAkGmxnXbmXdi FmFwbnfhkzN2/pp1KMwWRTQBL0AdGAzNzsIFKOX0MX4+wT8d/1hsO0KdUJ2tWn3hsJ7+eZmscpA Ze/fcAuqVut0pm06DdMW534AiyEZZn8= X-Google-Smtp-Source: AGHT+IEQBvyWzkoQVjdmfmIfrw/yVEGP6lHCidH6Y561kN3oQGNTNDTy3rKw9FwrLDkMSjWO03wIew== X-Received: by 2002:a5d:6483:0:b0:385:fabf:13d5 with SMTP id ffacd0b85a97d-38a8730d55cmr18261118f8f.25.1736729296324; Sun, 12 Jan 2025 16:48:16 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b8299sm10825477f8f.74.2025.01.12.16.48.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 04/23] hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa() Date: Mon, 13 Jan 2025 01:47:29 +0100 Message-ID: <20250113004748.41658-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target specific CPU env to the locally declared bootcpu_supports_isa() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef20968..918ce7795c4 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -49,9 +49,9 @@ typedef enum bl_reg { BL_REG_RA = 31, } bl_reg; -static bool bootcpu_supports_isa(uint64_t isa_mask) +static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) { - return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); + return cpu_supports_isa(env, isa_mask); } static void st_nm32_p(void **ptr, uint32_t insn) @@ -69,7 +69,7 @@ static void st_nm32_p(void **ptr, uint32_t insn) /* Base types */ static void bl_gen_nop(void **ptr) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { st_nm32_p(ptr, 0x8000c000); } else { uint32_t *p = *ptr; @@ -120,7 +120,7 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, /* Single instructions */ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ @@ -129,7 +129,7 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) static void bl_gen_jalr(void **p, bl_reg rs) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { uint32_t insn = 0; insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */ @@ -196,7 +196,7 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { bl_gen_sw_nm(p, rt, base, offset); } else { bl_gen_i_type(p, 0x2b, base, rt, offset); @@ -205,7 +205,7 @@ static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ @@ -215,7 +215,7 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) /* Pseudo instructions */ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) { - if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); } else { @@ -235,7 +235,7 @@ static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) { - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_dli(p, rt, imm); /* 64bit */ } else { bl_gen_li(p, rt, imm); /* 32bit */ @@ -281,7 +281,7 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); - if (bootcpu_supports_isa(ISA_MIPS3)) { + if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } else { bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); From patchwork Mon Jan 13 00:47:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B51EE7719E for ; Mon, 13 Jan 2025 00:49:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8d1-0004Pl-O4; Sun, 12 Jan 2025 19:48:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8d0-0004PW-4l for qemu-devel@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 918ce7795c4..b2be9267516 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -67,9 +67,9 @@ static void st_nm32_p(void **ptr, uint32_t insn) } /* Base types */ -static void bl_gen_nop(void **ptr) +static void bl_gen_nop(const CPUMIPSState *env, void **ptr) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { st_nm32_p(ptr, 0x8000c000); } else { uint32_t *p = *ptr; @@ -247,7 +247,7 @@ void bl_gen_jump_to(void **p, target_ulong jump_addr) { bl_gen_load_ulong(p, BL_REG_T9, jump_addr); bl_gen_jalr(p, BL_REG_T9); - bl_gen_nop(p); /* delay slot */ + bl_gen_nop(&MIPS_CPU(first_cpu)->env, p); /* delay slot */ } void bl_gen_jump_kernel(void **p, From patchwork Mon Jan 13 00:47:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CADD8E77188 for ; Mon, 13 Jan 2025 00:48:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8dJ-0004bC-Lo; Sun, 12 Jan 2025 19:48:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8d7-0004Q9-4z for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:35 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8d5-0000kB-Kf for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:32 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-436326dcb1cso26093465e9.0 for ; Sun, 12 Jan 2025 16:48:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729308; x=1737334108; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ukhH1iiiSXOet6r1KeHPOcyBDqXGlGqoY2zWACEw3zE=; b=nc6YSx+5k920gc+1n6iFpV/nkMIQiAxTgIxLqUuViPuiaBgVJ6tlEdDL5F2S7XC92k L0O4O0r8LaiXxXKXqMl/IHapNQrZXdxFiJVUNHxILcBvuJwrMV8ARxXI9R4MJ4yebqKw uobk5CCtA+TcB4foIERUNku55wYdWRt4PlOloeP4AgH46gPmA3eAE1tonq0iUTwHR5PO z0aBPMVx+hhZ04dFUiiu65TMh4zCfmNw3s+z4gQz+mgAG1eTUDmrol0nn0Si85/mmSGR /QfdF9fnuiG6uBptNqhOSQC3cMnycw6FwTjK9ZQJVibzPWR30Lf62RikMYJydGMQu+7t zOXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729308; x=1737334108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ukhH1iiiSXOet6r1KeHPOcyBDqXGlGqoY2zWACEw3zE=; b=Ffot0/C4n4kCFh6izDMhI5hlJnk7NDE1O5aTDXPQrYFJjW5tr9UKOKKdKIKFa9djhQ viDYsoUtgw+Leauh1dKhCqCRPM/ISe8wPAbwxD1JOSRQEkyc41pRK4hgQpHfScTMJZMW MHO35lI0QbVn3q14B4wmP0iepvVA2BdZ5DS1BkiI8wGKHwvjV/1wShc/iiI9o7A3WkVU so51wRnYmOJmaA2vRjFk0D5sMap0x7IZeRW8Ht928ZRWV/7m9ck4YT6NzoCZhymguUeJ 0FnxBV57QRWw7aUCpGjwMZkKRrojh18nRqzBjNGhXOUfvYoohYRB6xZT3KMXoZpfz6eI J8fA== X-Gm-Message-State: AOJu0YxjUmYvC8TBJSFNSEdFGeSKGLdEJ5Nn7BvQOkE4x8TkC/xrxmrI wGVyuovP2S4XAa33+vp56wztO99ZeXzHrPdR/wdh8ScMsFVNwM6019x84OsY6ReRyTQd7Tjixy6 d5Eg= X-Gm-Gg: ASbGncvFp4NHP7dVbv30GfZoO/6laljNvUpuAp8z+ec8sxmoInxSa9YHHBjW34ZVHSE e+YeVM3X7mzc5K93Q4kxOtE05GOq6KQoRG7uW1M/MwM2gZxtNGwRQnSx7xvMquuQLYdV3JauIrk ZW8yUeMPjiaPGNoLFK3eX5Jm9VXoeY4nmJjTWIdxvd+mZUOvXMFrOQla23WNPas+B/hw0eNh3zr zpZXTUPyRS+mL9jHr6T756u0soM1V9DQbnxP68ScswDSea2zLUNUTtJpAGO6+4tGynlQ3ba1vEW U9+Jn0DOuRkTmMPrOiPkXSIIqb+N/70= X-Google-Smtp-Source: AGHT+IFin18wfPWieqTxDbYHm3MTwo3zreDZRLfY3F3DoHY2MbztU9z6jUzsz6c9hu+K6AVxajqdMw== X-Received: by 2002:a05:600c:4314:b0:434:a802:e9b2 with SMTP id 5b1f17b1804b1-436eedef4damr95366165e9.4.1736729308115; Sun, 12 Jan 2025 16:48:28 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index b2be9267516..7cf1f01d225 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -118,9 +118,10 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, } /* Single instructions */ -static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) +static void bl_gen_dsll(const CPUMIPSState *env, void **p, + bl_reg rd, bl_reg rt, uint8_t sa) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { + if (bootcpu_supports_isa(env, ISA_MIPS3)) { bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ @@ -227,9 +228,9 @@ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) { bl_gen_li(p, rt, extract64(imm, 32, 32)); - bl_gen_dsll(p, rt, rt, 16); + bl_gen_dsll(&MIPS_CPU(first_cpu)->env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); - bl_gen_dsll(p, rt, rt, 16); + bl_gen_dsll(&MIPS_CPU(first_cpu)->env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } From patchwork Mon Jan 13 00:47:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65804E77188 for ; Mon, 13 Jan 2025 00:54:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8dQ-0004p5-Gy; Sun, 12 Jan 2025 19:48:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8dB-0004Zd-Mh for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:37 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8dA-0000kk-5I for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:37 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4361fe642ddso39862105e9.2 for ; Sun, 12 Jan 2025 16:48:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729313; x=1737334113; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qoCXQwiSZHcZTwdJr/g1JL9VhUwkxRIR68QUTMcGTac=; b=TMILdDMPk2mOdAevYWKHZi6Z3ZkX5eHkoQXJMF6cVcEvNZDpVLIkYMLNRYy2T4dWoz SSjhvbz+0fxdEz/HREHLJCIC8XPf1ov1M6kG3BeocVdfl9o7DKV94D31tVG7BAOq75co HZvGxfc11r03J6k3uWhAUmfflE71K4BEWFE8zXkUaq55Z5eRpDGXjb4ekKb57aOxuD2q vRY+vLvXUKUeV37KwiE2rqZsKzwoq/09UKRKSA8PGov/kvJXisBT75GSp/LtwevAoT07 vTn7smHJUgk5HGXPrFrdXSxynvV4PRhG/9LCyY2tvJ7TgPtKqwj2dE9IdR2C5k+gbPpR lbJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729313; x=1737334113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qoCXQwiSZHcZTwdJr/g1JL9VhUwkxRIR68QUTMcGTac=; b=je2xgo4y0twN241s6sglrlVkfiKTG3EhiMjyvKepaBvbFdkC3kvKC9p0qZYPqFH8Eg eR8Vi8HKjZbkRWvEr9EOXplBWqZwVGo3XL3CjRyCPaMlYYTerRXbB2u9a8hez+RrNwMK wqcKgx2sz+xYDT0RcXsDBNBs3hcbVu1W1oVD1Qy/1rhVt4mwwXjpFC+Ktf+QDVXlss29 HG/lozc+27SPorMNfm+hCv6vdkClvCSatupQ+qIFbn4bzpwDXfEFwOgLUFC9ldeH+k9s nvAYxCeYMWbfNz+lK6D/1e9l0yOgbUupgo3bPgy3AGrnA+X2Vrai8b5wumzhaEGuMZ6S uIgw== X-Gm-Message-State: AOJu0YxjjHY/hFzmyMhq+pSyJjbwUc5uWWGZp28/Ss/1LYTupky5mzmF z9TjIXpOXAOYouDa5DrwO3mIRpj2BMcTvvIMQJOCjkipVlOOX08o7xoaLC1a5UgAi8VZfAIQuR2 KFSE= X-Gm-Gg: ASbGnctGdFqaSifeEPBmeDZKr+U5NyVs0c+VeiQx4f1p1y7iyxpwNhQJzQZ1cv66GW4 6vojPwU01lWktGwWvm2s6Y9NRw8BrP/+x8Yv9YMXZEUAyq2j1OaNWZst7SgkrIfliFm4dXhRclo +/CgCQAKEAW8vXZOW38EbJ83jxLwtb/hHjYqaXeIOecNxeq0lnzWTqZweWY6IjA3KZFP/ct27XM nh6jUMj6XNe6P4aJrVgGr9ylyYUmGvNQkv9GDmwNa8Pgxuhlr/6OOHsGvQxz32y/UNM9OHUx3+b PLzR7JXpX8Ue94cMorkI0ozRzzOcYkk= X-Google-Smtp-Source: AGHT+IGiG+AJlNOJFHnhARXFEvWsYcXfdEdWu/AR5EMlPmeQjlNQAPihA833yRDHRJEaNK8SHI6fjA== X-Received: by 2002:a5d:59ab:0:b0:386:37f5:99f6 with SMTP id ffacd0b85a97d-38a8733bf6dmr17067497f8f.53.1736729313372; Sun, 12 Jan 2025 16:48:33 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e37d154sm11057172f8f.10.2025.01.12.16.48.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 07/23] hw/mips/bootloader: Propagate CPU env to bl_gen_jalr() Date: Mon, 13 Jan 2025 01:47:32 +0100 Message-ID: <20250113004748.41658-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_jalr() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 7cf1f01d225..9f35b23653a 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -128,9 +128,9 @@ static void bl_gen_dsll(const CPUMIPSState *env, void **p, } } -static void bl_gen_jalr(void **p, bl_reg rs) +static void bl_gen_jalr(const CPUMIPSState *env, void **p, bl_reg rs) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { uint32_t insn = 0; insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */ @@ -247,7 +247,7 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) void bl_gen_jump_to(void **p, target_ulong jump_addr) { bl_gen_load_ulong(p, BL_REG_T9, jump_addr); - bl_gen_jalr(p, BL_REG_T9); + bl_gen_jalr(&MIPS_CPU(first_cpu)->env, p, BL_REG_T9); bl_gen_nop(&MIPS_CPU(first_cpu)->env, p); /* delay slot */ } From patchwork Mon Jan 13 00:47:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 779E2E7719F for ; Mon, 13 Jan 2025 00:49:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8dP-0004ha-81; Sun, 12 Jan 2025 19:48:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8dG-0004av-PJ for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:44 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8dF-0000lL-96 for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:48:42 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4361f664af5so43334625e9.1 for ; Sun, 12 Jan 2025 16:48:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729318; x=1737334118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v6Clg/N9h/uY9sG75mKmNN87S01issR08U/shM6098E=; b=qHxs/dOedUTiTcJjNhREer6+S0x0TK0losO7ZyryVYbJWM8EMQWvNIDRZ0Aa0N89fp TJIqv0n1V6av+YmSeaiHJeV7CA7Yb8Kdt+PES4XkWxHSokAqsPVkk2kA/UmkkdQKCZyH CZ1RO6GLP68vTB+orxbcXGwQDHF4lpzI2ohEn10cuQoucGG7gdMVLKq7vZeXcC2ZBaTs 1W03CiwieIuHbB7oXJgWFoprqIQW042CiDhQLc9bwB243yY+YDFvjtZdZGyUN0QZObQG Jna4AXFDhXGocJafgWTsA0udv9Kp6ZWA2Nd0kJit5US9NwCpWma0CWbLRvW6hu6krWB5 1vpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729318; x=1737334118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v6Clg/N9h/uY9sG75mKmNN87S01issR08U/shM6098E=; b=BvZT9z1sysUb5a4oBUGvBv5W7/bu3rreLVhDCd5ujXK/dDXq4VXhnNOhg1byNZK9JL dBkeK8Z+yUi/tcKikC2T8xHqqyZ1efXS1nw2Ld+auogne2//7eifteMg2DyxJjGXfjyF ZJHRDYDbODo/PHZOi7pmVjCD9nOLBwob0BiMCpaVj0884Ynn9MVe2d0dYEe9yfNyZiVA Urj0ji4SuPkayefTurp2LQs9EmzIeSV35TRIgGhnh9ly8VCPLrXALsa/fXPwI4xThzFu wNmQ84WhU9KT1zD070CswC1yIe1Rfu4fPkfRu13nuudjI4lG9TWyUrvHNBxQmr2hSX0K mU6g== X-Gm-Message-State: AOJu0YwQFhpoRkLYy56Qwb+QErnOAUxMBvyshn6O6p55IVGHr3nKA/aV ravQOJZLpDSseaUD/QiM61fccm9a7HL1uwf2Z1CK3CJfmkOg+ayx0iCjkoSNUmO0YphBgisDDHy PlJQ= X-Gm-Gg: ASbGnctDIs7CJ72it3VizKvAdlDe3Q+wMDyyPBPGbDTq24Kqh6N7+nc5zwk/t7b0Mhj WKms/uJT8LvAbZ0iRoNWuHqe4oWp+jT6PKG/BUo6govcgrRW0teZP90A+0GH+E8xaD6WVJ0oEz8 JCsllRbV5zY6vyGa3E3LdCjIvd1z83JwZRmW/8LooFh2r8AG5Zs48G1SfjqODl3eZ85iMUqYxxu WOjCx2uNkioGpCide99HtZCr7SRSLwu6M5dg3FrFzGPY/4SiYF2zOwc5BfnZJx/WhC707SW0wjc rYr0sYPJvDigkBz6AMtSXKmDrOnw3OI= X-Google-Smtp-Source: AGHT+IFfdVdQKpy0TwgzJRor6r4TqD7hz9G3DdJgVD0QXxOYq2yx6VaexUrCBHDyYO9tY/nGybpywQ== X-Received: by 2002:a05:6000:1f81:b0:386:7fe:af8e with SMTP id ffacd0b85a97d-38a872fb17fmr14396971f8f.12.1736729318623; Sun, 12 Jan 2025 16:48:38 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d26a7bsm130244375e9.0.2025.01.12.16.48.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:48:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 08/23] hw/mips/bootloader: Propagate CPU env to bl_gen_sw() Date: Mon, 13 Jan 2025 01:47:33 +0100 Message-ID: <20250113004748.41658-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_sw() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 9f35b23653a..30e6422d331 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -195,9 +195,10 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) st_nm32_p(ptr, insn); } -static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sw(const CPUMIPSState *env, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { bl_gen_sw_nm(p, rt, base, offset); } else { bl_gen_i_type(p, 0x2b, base, rt, offset); @@ -285,7 +286,7 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); } } @@ -293,7 +294,7 @@ void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) { bl_gen_li(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) From patchwork Mon Jan 13 00:47:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01D24E7719E for ; Mon, 13 Jan 2025 00:53:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8dP-0004h8-62; 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 30e6422d331..34c3043a563 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -205,9 +205,10 @@ static void bl_gen_sw(const CPUMIPSState *env, void **p, } } -static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sd(const CPUMIPSState *env, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { + if (bootcpu_supports_isa(env, ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ @@ -284,7 +285,7 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 34c3043a563..32811e48cdd 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -216,9 +216,10 @@ static void bl_gen_sd(const CPUMIPSState *env, void **p, } /* Pseudo instructions */ -static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(const CPUMIPSState *env, void **p, + bl_reg rt, uint32_t imm) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_NANOMIPS32)) { + if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) { bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); } else { @@ -229,7 +230,7 @@ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) { - bl_gen_li(p, rt, extract64(imm, 32, 32)); + bl_gen_li(&MIPS_CPU(first_cpu)->env, p, rt, extract64(imm, 32, 32)); bl_gen_dsll(&MIPS_CPU(first_cpu)->env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); bl_gen_dsll(&MIPS_CPU(first_cpu)->env, p, rt, rt, 16); @@ -241,7 +242,7 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_dli(p, rt, imm); /* 64bit */ } else { - bl_gen_li(p, rt, imm); /* 32bit */ + bl_gen_li(&MIPS_CPU(first_cpu)->env, p, rt, imm); /* 32bit */ } } @@ -293,7 +294,7 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) { - bl_gen_li(p, BL_REG_K0, val); + bl_gen_li(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); } From patchwork Mon Jan 13 00:47:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DB12E77188 for ; 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 32811e48cdd..95ee59f33c9 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -228,19 +228,20 @@ static void bl_gen_li(const CPUMIPSState *env, void **p, } } -static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(const CPUMIPSState *env, void **p, + bl_reg rt, uint64_t imm) { - bl_gen_li(&MIPS_CPU(first_cpu)->env, p, rt, extract64(imm, 32, 32)); - bl_gen_dsll(&MIPS_CPU(first_cpu)->env, p, rt, rt, 16); + bl_gen_li(env, p, rt, extract64(imm, 32, 32)); + bl_gen_dsll(env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); - bl_gen_dsll(&MIPS_CPU(first_cpu)->env, p, rt, rt, 16); + bl_gen_dsll(env, p, rt, rt, 16); bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { - bl_gen_dli(p, rt, imm); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc08eesm162988605e9.10.2025.01.12.16.48.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 12/23] hw/mips/bootloader: Propagate CPU env to bl_gen_load_ulong() Date: Mon, 13 Jan 2025 01:47:37 +0100 Message-ID: <20250113004748.41658-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_load_ulong() function. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 95ee59f33c9..e29eb5e92f3 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -238,19 +238,20 @@ static void bl_gen_dli(const CPUMIPSState *env, void **p, bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); } -static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, + bl_reg rt, target_ulong imm) { - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { - bl_gen_dli(&MIPS_CPU(first_cpu)->env, p, rt, imm); /* 64bit */ + if (bootcpu_supports_isa(env, ISA_MIPS3)) { + bl_gen_dli(env, p, rt, imm); /* 64bit */ } else { - bl_gen_li(&MIPS_CPU(first_cpu)->env, p, rt, imm); /* 32bit */ + bl_gen_li(env, p, rt, imm); /* 32bit */ } } /* Helpers */ void bl_gen_jump_to(void **p, target_ulong jump_addr) { - bl_gen_load_ulong(p, BL_REG_T9, jump_addr); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_T9, jump_addr); bl_gen_jalr(&MIPS_CPU(first_cpu)->env, p, BL_REG_T9); bl_gen_nop(&MIPS_CPU(first_cpu)->env, p); /* delay slot */ } @@ -264,19 +265,19 @@ void bl_gen_jump_kernel(void **p, target_ulong kernel_addr) { if (set_sp) { - bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(p, BL_REG_A3, a3); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A3, a3); } bl_gen_jump_to(p, kernel_addr); @@ -284,8 +285,8 @@ void bl_gen_jump_kernel(void **p, void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) { - bl_gen_load_ulong(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); } else { @@ -296,13 +297,13 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) { bl_gen_li(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) { bl_gen_dli(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm94008945e9.12.2025.01.12.16.49.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 13/23] hw/mips/bootloader: Propagate CPU to bl_gen_jump_to() Date: Mon, 13 Jan 2025 01:47:38 +0100 Message-ID: <20250113004748.41658-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_jump_to() function. Include "target/mips/cpu-qom.h" to get MIPSCPU typedef. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 3 ++- hw/mips/bootloader.c | 10 +++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index c32f6c28356..daa2b92e249 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -10,8 +10,9 @@ #define HW_MIPS_BOOTLOADER_H #include "exec/cpu-defs.h" +#include "target/mips/cpu-qom.h" -void bl_gen_jump_to(void **ptr, target_ulong jump_addr); +void bl_gen_jump_to(const MIPSCPU *cpu, void **ptr, target_ulong jump_addr); void bl_gen_jump_kernel(void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index e29eb5e92f3..6f055228392 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -249,11 +249,11 @@ static void bl_gen_load_ulong(const CPUMIPSState *env, void **p, } /* Helpers */ -void bl_gen_jump_to(void **p, target_ulong jump_addr) +void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_T9, jump_addr); - bl_gen_jalr(&MIPS_CPU(first_cpu)->env, p, BL_REG_T9); - bl_gen_nop(&MIPS_CPU(first_cpu)->env, p); /* delay slot */ + bl_gen_load_ulong(&cpu->env, p, BL_REG_T9, jump_addr); + bl_gen_jalr(&cpu->env, p, BL_REG_T9); + bl_gen_nop(&cpu->env, p); /* delay slot */ } void bl_gen_jump_kernel(void **p, @@ -280,7 +280,7 @@ void bl_gen_jump_kernel(void **p, bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A3, a3); } - bl_gen_jump_to(p, kernel_addr); + bl_gen_jump_to(MIPS_CPU(first_cpu), p, kernel_addr); } void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) From patchwork Mon Jan 13 00:47:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07F94E77188 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fc51sm127732735e9.7.2025.01.12.16.49.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 14/23] hw/mips/bootloader: Propagate CPU to bl_gen_jump_kernel() Date: Mon, 13 Jan 2025 01:47:39 +0100 Message-ID: <20250113004748.41658-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_jump_kernel() function. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 2 +- hw/mips/bootloader.c | 14 +++++++------- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index daa2b92e249..6b58eafb8bc 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -13,7 +13,7 @@ #include "target/mips/cpu-qom.h" void bl_gen_jump_to(const MIPSCPU *cpu, void **ptr, target_ulong jump_addr); -void bl_gen_jump_kernel(void **ptr, +void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 6f055228392..9804051ab2d 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -256,7 +256,7 @@ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr) bl_gen_nop(&cpu->env, p); /* delay slot */ } -void bl_gen_jump_kernel(void **p, +void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, @@ -265,22 +265,22 @@ void bl_gen_jump_kernel(void **p, target_ulong kernel_addr) { if (set_sp) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_SP, sp); + bl_gen_load_ulong(&cpu->env, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A0, a0); + bl_gen_load_ulong(&cpu->env, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A1, a1); + bl_gen_load_ulong(&cpu->env, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A2, a2); + bl_gen_load_ulong(&cpu->env, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_A3, a3); + bl_gen_load_ulong(&cpu->env, p, BL_REG_A3, a3); } - bl_gen_jump_to(MIPS_CPU(first_cpu), p, kernel_addr); + bl_gen_jump_to(cpu, p, kernel_addr); } void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 63dc654192a..3a06b776fe8 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -352,7 +352,7 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) * a2/$6 = 0 * a3/$7 = 0 */ - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel(MIPS_CPU(first_cpu), &p, true, 0, true, (int32_t)-2, true, fdt_addr, true, 0, true, 0, kernel_entry); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 16b6a5129e7..b87622ee6e3 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base, /* Second part of the bootloader */ p = (uint32_t *)(base + 0x040); - bl_gen_jump_kernel((void **)&p, + bl_gen_jump_kernel(MIPS_CPU(first_cpu), (void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 37be2330eda..fe9e06f48f4 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -678,7 +678,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); - bl_gen_jump_kernel(p, + bl_gen_jump_kernel(MIPS_CPU(first_cpu), p, true, ENVP_VADDR - 64, /* * If semihosting is used, arguments have already From patchwork Mon Jan 13 00:47:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 959FCE77188 for ; Mon, 13 Jan 2025 00:53:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8e4-0006Jj-BW; Sun, 12 Jan 2025 19:49:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8ds-00060O-V5 for qemu-devel@nongnu.org; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b82a4sm10918902f8f.72.2025.01.12.16.49.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 15/23] hw/mips/bootloader: Propagate CPU to bl_gen_write_ulong() Date: Mon, 13 Jan 2025 01:47:40 +0100 Message-ID: <20250113004748.41658-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_ulong() function. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 3 ++- hw/mips/bootloader.c | 13 +++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 6b58eafb8bc..a7f174e16bc 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -20,7 +20,8 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr, bool set_a2, target_ulong a2, bool set_a3, target_ulong a3, target_ulong kernel_addr); -void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); +void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, + target_ulong addr, target_ulong val); void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 9804051ab2d..c4fd85b9f42 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -283,14 +283,15 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p, bl_gen_jump_to(cpu, p, kernel_addr); } -void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, + target_ulong addr, target_ulong val) { - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); - if (bootcpu_supports_isa(&MIPS_CPU(first_cpu)->env, ISA_MIPS3)) { - bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_load_ulong(&cpu->env, p, BL_REG_K0, val); + bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr); + if (bootcpu_supports_isa(&cpu->env, ISA_MIPS3)) { + bl_gen_sd(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } } From patchwork Mon Jan 13 00:47:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7E98E77188 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4c1b44sm10901970f8f.90.2025.01.12.16.49.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 16/23] hw/mips/bootloader: Propagate CPU to bl_gen_write_u32() Date: Mon, 13 Jan 2025 01:47:41 +0100 Message-ID: <20250113004748.41658-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_u32() function. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 3 ++- hw/mips/bootloader.c | 9 +++++---- hw/mips/malta.c | 18 +++++++++--------- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index a7f174e16bc..cc2ffe3ab2c 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -22,7 +22,8 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr, target_ulong kernel_addr); void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, target_ulong addr, target_ulong val); -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); +void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint32_t val); void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index c4fd85b9f42..6f0222faf48 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -295,11 +295,12 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, } } -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const MIPSCPU *cpu, void **p, + target_ulong addr, uint32_t val) { - bl_gen_li(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); - bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_li(&cpu->env, p, BL_REG_K0, val); + bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr); + bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index fe9e06f48f4..5ccff2cb0c1 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -636,29 +636,29 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -669,12 +669,12 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); From patchwork Mon Jan 13 00:47:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDC6AE7719F for ; Mon, 13 Jan 2025 00:52:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8eP-0007GN-0V; Sun, 12 Jan 2025 19:49:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8e4-0006S8-GJ for qemu-devel@nongnu.org; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38325esm10765264f8f.27.2025.01.12.16.49.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 17/23] hw/mips/bootloader: Propagate CPU to bl_gen_write_u64() Date: Mon, 13 Jan 2025 01:47:42 +0100 Message-ID: <20250113004748.41658-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_u64() function. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 3 ++- hw/mips/bootloader.c | 9 +++++---- hw/mips/boston.c | 6 +++--- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index cc2ffe3ab2c..946580f6f5c 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -24,6 +24,7 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, target_ulong addr, target_ulong val); void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr, target_ulong addr, uint32_t val); -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_u64(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 6f0222faf48..c5bad03b528 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -303,9 +303,10 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p, bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const MIPSCPU *cpu, void **p, + target_ulong addr, uint64_t val) { - bl_gen_dli(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); - bl_gen_sd(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_dli(&cpu->env, p, BL_REG_K0, val); + bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr); + bl_gen_sd(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3a06b776fe8..09c4dfade12 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -329,19 +329,19 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9dc8802sm125761915e9.10.2025.01.12.16.49.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 18/23] hw/mips/boston: Propagate CPU to gen_firmware() Date: Mon, 13 Jan 2025 01:47:43 +0100 Message-ID: <20250113004748.41658-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In boston_mach_init(), resolves the first CPU from the CPS container using the QOM "cpu[0]" path. Propagate it to gen_firmware(), removing the &first_cpu use. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 09c4dfade12..f2c0e335e73 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -323,25 +323,26 @@ static void boston_register_types(void) } type_init(boston_register_types) -static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) +static void gen_firmware(const MIPSCPU *cpu, void *p, + hwaddr kernel_entry, hwaddr fdt_addr) { uint64_t regaddr; /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_u64(MIPS_CPU(first_cpu), &p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* @@ -352,7 +353,7 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) * a2/$6 = 0 * a3/$7 = 0 */ - bl_gen_jump_kernel(MIPS_CPU(first_cpu), &p, + bl_gen_jump_kernel(cpu, &p, true, 0, true, (int32_t)-2, true, fdt_addr, true, 0, true, 0, kernel_entry); @@ -825,7 +826,9 @@ static void boston_mach_init(MachineState *machine) } } - gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, + gen_firmware(MIPS_CPU(object_resolve_path_component(OBJECT(&s->cps), + "cpu[0]")), + memory_region_get_ram_ptr(flash) + 0x7c00000, s->kernel_entry, s->fdt_base); } else if (!qtest_enabled()) { error_report("Please provide either a -kernel or -bios argument"); From patchwork Mon Jan 13 00:47:44 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e37d0casm10893890f8f.11.2025.01.12.16.49.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 19/23] hw/mips/fuloong: Propagate CPU to write_bootloader() Date: Mon, 13 Jan 2025 01:47:44 +0100 Message-ID: <20250113004748.41658-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org mips_fuloong2e_init() created the vCPU so has its reference, propagate it to write_bootloader(), removing the &first_cpu use. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/fuloong2e.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index b87622ee6e3..1e55adacdd2 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -163,7 +163,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) return kernel_entry; } -static void write_bootloader(CPUMIPSState *env, uint8_t *base, +static void write_bootloader(const MIPSCPU *cpu, uint8_t *base, uint64_t kernel_addr) { uint32_t *p; @@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base, /* Second part of the bootloader */ p = (uint32_t *)(base + 0x040); - bl_gen_jump_kernel(MIPS_CPU(first_cpu), (void **)&p, + bl_gen_jump_kernel(cpu, (void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, @@ -258,7 +258,7 @@ static void mips_fuloong2e_init(MachineState *machine) loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(cpu); - write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); + write_bootloader(cpu, memory_region_get_ram_ptr(bios), kernel_entry); } else { filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: FULOONG_BIOSNAME); From patchwork Mon Jan 13 00:47:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D42EDE77188 for ; Mon, 13 Jan 2025 00:54:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8eQ-0007S9-7W; Sun, 12 Jan 2025 19:49:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8eK-0006wy-Os for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:49:49 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8eJ-0000zA-1s for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:49:48 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4362bae4d7dso26416475e9.1 for ; Sun, 12 Jan 2025 16:49:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729385; x=1737334185; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KxFKXXK5VzgQk+VMHxLlV5NbZtRQAbvkWoWKwyBHWBc=; b=bDRnCsCTIduA/tdlJqw/jffvsp7GOiZOac9rtHam1qWaURNI6PVmc2m9dMlZ8MrX0m 22dS5L3XzWuAyApr6tcOoDOIZmbcOcYUzGv1GezJaVVnXEosJ1mcs6YkmigTSquu4kLw 2L7xdgE23RCySMcS3z3KWs0gw6xJBqJ55PB3tqFe/x6B9H4aM/zGF7RtdNfrmTTnoQIR I0HawKY7KtRaHOpBlCvs5ZF7Ryqe2qryUrdO1E9Aqz/4yYBvhdHL00adDmsL9FUS9bqs IER6ghYCtwB6+Pdkx1EFK/uQv1uXKm3oMYvCuk3px3eYC7YyAJzykEm1LGgrCOVYFlj4 Gwng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729385; x=1737334185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxFKXXK5VzgQk+VMHxLlV5NbZtRQAbvkWoWKwyBHWBc=; b=gu5ZU+d8N7OM5L3iEcTV6rh+12XoTaBIUW36QiX50FM7n5Sw6xUY2DEc4AeGJjVj3V hGmeKkSC2o5/eV7V+9QatrXtUVaA50MoreZCKpvP4Mpj1nvlTaGsond25hxjHv9F7e0k 9CVZkPsVX0s1XVGo+kw+0KSyx/n1kh2eZ2Sk3Yw/650GnWkHHcwBYIBR+D3SRHFlA2w9 VseoCC3Wssh/z1ojgixql1zfzuHRTEiJi97PS5CbFQkXV8zJ7L3qmAgt22wi/V1y27Aq KkgqvpcFgosB9n2/pox6swKfKAx710XSactScG7mURSjZ38LWKkqQ085XTcJSgN1X5UE 8d6A== X-Gm-Message-State: AOJu0YxV5h1nwWEYTovcSHJFMg2siw5EnRFeNpJEjixwrkrflP2ZI8r0 rXvyzZflx83/5LveWA9T+olm2UEptj9nVEKq7lkC03xjagltMVS6dmQ/lKLwWaenq5enfPA/H5r rwqA= X-Gm-Gg: ASbGncscR+akj/iptqQChyge1izjKJJCl4RiM3sVoV9qKjGqUz8gCG642ZnWoKnAcxi MbNmDgrDOmVTNsyTMhaoiNwVyr/RRLRtzwMjX8+BTn7QrT9oTZYdJU9AGE6JUrWh8D/y0sruI7x bZy4EJElMKwVe0oH44ch36BYbPNp3Cw5b2L4J+BauFNMv9GIQPG7Z3xiUUKD1eNoaG6ZPC9tPZk aBO2wCbU0uLvJBt9FsYsmouwd1R46Qgi4mV/p5NG4zbZF2aPnONpvlzRN/v8TGgqrcqFyWnMwWC d412PjDZYb4yUt2nQ+KioH/y6nt20fg= X-Google-Smtp-Source: AGHT+IHeH/ubmLfesgunDG0PPKZJ/HXcyNYcyhxuKSk/XLr0oGh/WeW6MsqMmUg/ZeG8KFlt7AvIoA== X-Received: by 2002:a05:600c:4449:b0:435:192:63ca with SMTP id 5b1f17b1804b1-436e26f481dmr58567575e9.21.1736729385335; Sun, 12 Jan 2025 16:49:45 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9e03f8bsm125389885e9.23.2025.01.12.16.49.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 20/23] hw/mips/malta: Keep reference of vCPUs in MaltaState Date: Mon, 13 Jan 2025 01:47:45 +0100 Message-ID: <20250113004748.41658-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When a QOM object create children with object_new(), it is better to keep reference to them for further use. This will be helpful to remove &first_cpu uses in few commits. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 5ccff2cb0c1..a037ec2cc8d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -107,6 +107,7 @@ struct MaltaState { SysBusDevice parent_obj; Clock *cpuclk; + MIPSCPU **cpus; MIPSCPSState cps; }; @@ -1037,6 +1038,7 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, for (i = 0; i < ms->smp.cpus; i++) { cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, TARGET_BIG_ENDIAN); + s->cpus[i] = cpu; /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -1063,6 +1065,7 @@ static void create_cps(MachineState *ms, MaltaState *s, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); + memcpy(s->cpus, s->cps.cpus, ms->smp.cpus * sizeof(MIPSCPU *)); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); @@ -1070,9 +1073,11 @@ static void create_cps(MachineState *ms, MaltaState *s, *cbus_irq = NULL; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fd03sm129722785e9.6.2025.01.12.16.49.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 21/23] hw/mips/malta: Propagate MaltaState to write_bootloader() Date: Mon, 13 Jan 2025 01:47:46 +0100 Message-ID: <20250113004748.41658-22-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Pass MaltaState as argument to write_bootloader() so next commit can propagate it to bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index a037ec2cc8d..589e1a07e47 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -692,7 +692,8 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, kernel_entry); } -static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, +static void write_bootloader_nanomips(MaltaState *s, + uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { uint16_t *p; @@ -744,7 +745,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, * a2 - 32-bit address of the environment variables table * a3 - RAM size in bytes */ -static void write_bootloader(uint8_t *base, uint64_t run_addr, +static void write_bootloader(MaltaState *s, + uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { uint32_t *p; @@ -1172,10 +1174,10 @@ void mips_malta_init(MachineState *machine) kernel_entry = load_kernel(); if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { - write_bootloader(memory_region_get_ram_ptr(bios), + write_bootloader(s, memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } else { - write_bootloader_nanomips(memory_region_get_ram_ptr(bios), + write_bootloader_nanomips(s, memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } } else { From patchwork Mon Jan 13 00:47:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FDC0E7719E for ; Mon, 13 Jan 2025 00:52:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8ee-0008QQ-TB; Sun, 12 Jan 2025 19:50:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8eV-00083a-FT for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:49:59 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8eT-00012p-TD for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:49:59 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso25910615e9.3 for ; Sun, 12 Jan 2025 16:49:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729396; x=1737334196; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+QUcPQTSLIyjkEu3IRNgiae9ESabUrMs06G5+aRxsH0=; b=lM6VgTrQfYuHCskd5dXXjUTcIm1q2JYDpHdyhcwU9uAAuXWz1bjgN3zUSPCxpkzJeM GSa0Hg7qHfTU9LBHcpCoTPcbKJ9mMUtGX9fzQCwRoRmEv+nD6XC9ldmxfdMLDciUhqEi Irsu0m2bHcDRSXfwoeHMIfpzy2/pWCJBVNudUCEB4ejrAq8zxEeEoiJg3BjsIxOsUlYd LhDSM9/wS/pdu+i77IpapU3yHTI+MuC489AYjJ7eY+zkGnSZZ98hVOkuHakKi2uI8gvz 7md/pXVMRjzQxJBwPpTl+d+J5L/I+a3S/Juq+nmqMkoDYLz5LOxM2iu24BM8vJozyvbr LTxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729396; x=1737334196; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+QUcPQTSLIyjkEu3IRNgiae9ESabUrMs06G5+aRxsH0=; b=cyO1e6vgSrbUTYbn6mxNNaro2k5oKFcWSCa1C8y2Ge194yHFnsobjSaDXwqIHgYj3V QojryWOue1IGrypkzvWUW0zYjec+GY2Jw+48ldSplGK19Mnn5PxYvzThfbYF+hEuagjp IGhO/2HHoGCyJxhLJ2bw8SE77ARV6cpzRvk9vK/93qKn2vMlGvMu3C4psYAYv4DWZ/M+ 8Z/TFFw3Es1QSr2MlQ91R0UgMnMSWL5obgT7uN9m/8FO4MoQPdpkHdLk63B+P5Svu4R2 +6GI1h7yUqAsTwUavfTMTffd6d263VlwYDqRk5AYGhGa2lN4TPBzxbbzLAFZK2g+BTxG LO5w== X-Gm-Message-State: AOJu0Yxuf8OCCkyT0lj/gjezQeacACOBsjmQzhW+1x5oqCHX1Oj1vSue p0dAHgKqe4YLjkNSVY8WMsrtYK0prFUJ2hXIc0Pm7Dfc4eOQ9/kpYw0eoU/S+rb1qxyq6d5yuDQ Uve8= X-Gm-Gg: ASbGncvkP7MV8Dsvo1DwxIgk20TYXrDMjHcAYDOcdSWLtTxEl+6RwRl5XPk9KbnWEHI 0CA+U9jrQNPkB+F1w5Mr6rFGxTTIxOwUEg4UCI7hIORQgKPGEzIGoVOZYJel950azY4UgfxSxvZ s6lmTMGsZwRChk9i4+J56jQzChU49YBIbS3PiK9YvaNs6w8NdSUf83OQ5mchWNV0OGaPoU1hx/2 rUr5KJlkrO2/T4TAKxpK/UarODY3sXXIt2a4rI/8dMQzdt9rf7NduGJKdSppyZjAGky6B0OOqz/ ZmTB/87R2LlOEQR2dOXRKPn3OSbPGOk= X-Google-Smtp-Source: AGHT+IGmPYK4+yml9nEJ1vg0hf99C1ulpd2K6QbPMkfU7wlTpKi0fvy2lJc+zNbWUPdOnuTUBGFOwg== X-Received: by 2002:a05:600c:3554:b0:436:1be4:c9b4 with SMTP id 5b1f17b1804b1-436e26ff1b2mr151791665e9.27.1736729396028; Sun, 12 Jan 2025 16:49:56 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9dc895esm125348935e9.13.2025.01.12.16.49.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:49:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 22/23] hw/mips/malta: Propagate MaltaState to bl_setup_gt64120_jump_kernel() Date: Mon, 13 Jan 2025 01:47:47 +0100 Message-ID: <20250113004748.41658-23-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate MaltaState to bl_setup_gt64120_jump_kernel() so it can access the MaltaState::cpus[] array. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 589e1a07e47..61b47b0dcbb 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -620,7 +620,8 @@ static void network_init(PCIBus *pci_bus) pci_init_nic_devices(pci_bus, "pcnet"); } -static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, +static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, + uint64_t run_addr, uint64_t kernel_entry) { static const char pci_pins_cfg[PCI_NUM_PINS] = { @@ -720,7 +721,7 @@ static void write_bootloader_nanomips(MaltaState *s, /* to_here: */ - bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); + bl_setup_gt64120_jump_kernel(s, (void **)&p, run_addr, kernel_entry); } /* @@ -786,7 +787,7 @@ static void write_bootloader(MaltaState *s, * */ - bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); + bl_setup_gt64120_jump_kernel(s, (void **)&p, run_addr, kernel_entry); /* YAMON subroutines */ p = (uint32_t *) (base + 0x800); From patchwork Mon Jan 13 00:47:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13936647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FCCAE77188 for ; Mon, 13 Jan 2025 00:53:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tX8fC-0000VJ-1z; Sun, 12 Jan 2025 19:50:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tX8eh-0000CN-10 for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:50:12 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tX8ea-000153-V6 for qemu-devel@nongnu.org; Sun, 12 Jan 2025 19:50:08 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4361c705434so26498505e9.3 for ; Sun, 12 Jan 2025 16:50:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736729402; x=1737334202; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nkJ53c1g/A3oVfRH9YrVVOx2OwtqwRGMfXxog5aOHSQ=; b=Qkx3EAKx9rT9PDOGrRdLoM6tw4XqjH0FtGEsKs6I1f7KP15BNzENIf8L849Uv2ZHsn ySW1vyuA1RmyqMWu0Nd+W5kq865RgcgQLalslEX2d/6OxxMy60/QRfOnzA19DJNW3weB B94vhr8VGZyPFpAwhFI9uDR+TK7xruwS4gdaW/T/a/uiNOGohpQDtM2jZDH/OQ8wlN4/ WPI+JMi2m3vmrvA+BTjaNvmskKwPwhqsg4xWzBOPR9h4LuwBxmKaqwTUFrZjblEp8Gox 9n+SW2XPfND0e76Pmb15FA6s6zSn0v/hYsRCwudCDAotwLnibEFOQh+esLpByALoO2Kc gh6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736729402; x=1737334202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nkJ53c1g/A3oVfRH9YrVVOx2OwtqwRGMfXxog5aOHSQ=; b=qitcUCmwRZSIR8svJF1G4BOipiz8jQSIF/pMQh7YL2qyql/7ugjmTQTK/RougbTMLu 8Z+OJFadjsIxNUIT7Aayym2I2kHqrTv5w7PAQfjEbt5PonrfkfqWGFhGAHXZv0QpVxjG 21kCPT9Ye2gzLVIRhSpZYdpSDtYDIbbrbUD7b0k8ubigqMRRx6a6OQ/N5utgvQy8TOyO Sbn5LZfJnEXlMpicVX//S+nPMw2PwJOo9S0wy9TIzmqZ+H7gfD4XjI/pH4p+IhPz6AcY 6tHnCdO2+a7nMjmxIsv2huoJjFJXkKjUFEnyznkvopInWFcmZyE5BYQegnId7ufl3krt BL+Q== X-Gm-Message-State: AOJu0YwSphyY8B+D/sriWWa4z7MAq7628cCc2TAwgEpigceONmIQUTnE 6p1HmNFoipxaeILbiD+WKcnYdqI/8xceuJYGk0lk+yyL0mDnuyK8P00UgXF+Rz7+qzgUBtFtozX HBOI= X-Gm-Gg: ASbGnctvz5Mw0CfIA8aqDkGfum+E2ZzPGzWql6E2qlEPsmn7k9uQOqzQR/ED8aaayH+ igc0RVABkq6mua3zggwUypm8tqyqNsUbJJI8o0BvBqDMfbIo68TVPtxRh6lVqCtQAMYxviHqmKo 7oQ16KdUi2aOuoqbzmrV/+RkSs3TZ7dwu2oNnu8KESuZT7hQGFiW9SVajz9Unws65VKF30dFAjh Ux2pBdXPVCN7xjwE8UoKvbU8La5RTIsFU8RS2WrWsShck1aeA2PY86gygRJgM+YMc+DC2J0Imw/ 1fHTXDRlA1EaypZPUWl8KmaOWI/6Ou8= X-Google-Smtp-Source: AGHT+IFRFBAoVg0Hr+JW3DVRqrODAWytXr5Rr97D7olpsZBeFvs5Ypcx9kgpBq62cd0MSG+VtBtgvg== X-Received: by 2002:a5d:5985:0:b0:38a:2798:c3e0 with SMTP id ffacd0b85a97d-38a87358f3bmr15835355f8f.54.1736729402089; Sun, 12 Jan 2025 16:50:02 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436dd11ddfdsm122124485e9.1.2025.01.12.16.49.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:50:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 23/23] hw/mips/malta: Remove all uses of &first_cpu global Date: Mon, 13 Jan 2025 01:47:48 +0100 Message-ID: <20250113004748.41658-24-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now than bl_setup_gt64120_jump_kernel() has access to the MaltaState::cpus[] array, it doesn't need the &first_cpu global anymore. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 61b47b0dcbb..9622e122b4a 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -638,29 +638,29 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_ISD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0IOLD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0IOHD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M0LD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M0HD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M1LD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M1HD */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -671,16 +671,16 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(s->cpus[0], p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); - bl_gen_jump_kernel(MIPS_CPU(first_cpu), p, + bl_gen_jump_kernel(s->cpus[0], p, true, ENVP_VADDR - 64, /* * If semihosting is used, arguments have already