From patchwork Mon Jan 13 08:43:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936916 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2074.outbound.protection.outlook.com [40.107.212.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D27C42343CF for ; Mon, 13 Jan 2025 08:44:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.74 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757861; cv=fail; b=n1uVr18SUgmvSWufZ1TNyXDUn13yog6S1aaLZPZEgFwTkkVTN+gnsG7cM3nlOeMGhSbHM/U+Ec2piJfrXPc+sBJwTK7PGA2A7u7k8RXziqdVBh57RJVEHcmai+p646wCcPrzpA79TJZMsGmUyVLoACZM08cmZ1X3UE7Z0qySxQ8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757861; c=relaxed/simple; bh=eWSbmUsnWUXm4nEj1mn7jGnY45RMMSai8bR78TLUSew=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=COZgOrCoBx90K7Bg3MMLttUAIhn9wrKbpm3JQZcz9NDuhvkmCuHS0/Qj4PhpQeWUBZv0uK363BaSVEDttHTfVfnaO/hhntvwg267uCmXMLPIAEpRezzR+NYIPHkFx85VRxG5pPrF0AcgVpN5sx2iTnkf/NN8R1J3l28kDVdJB9o= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=t3EVKAIJ; arc=fail smtp.client-ip=40.107.212.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="t3EVKAIJ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WYnrPRqG+lIqHpx4eNh1SLpYPQ3Ui/T+qJQrh0R6BLfcmZkQySEy1jhqv0AhepFOZwQDOPL0QAAWEZSf4/Jc8Onv8G78gfmAlhftUdY28xh+Xy/7YPUWz7osc5Upfrxny7IaSZk6Qg1NrVM0Yq4+Bq4XRnxAzDgJ3Ll52aDIQ3O3456AHf/WHoSrl7v6Tyrwnq5mb1LsXfNTvzlxxbcjzR3+mpPmqxtTHXSH7e34iNEPkPUAyBqJ8JDc4+OiyAPCXB7MGj/nne4iJ6Pz0ra7JsUkQg/7q7EMBg+ue9AF++8wHYF8YNPuXnuzYsM1/RohghT+Jg8KnbzmqrzbXp1szQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=t1VkwW4uLzksdkSRXDmXecCM+z/ASEcZrsg9oTV1EXs=; b=unLsSjgr6RAZXjmvowrsugKmS6YuaahDUT5KWgpjH9N074MJlwp9Gf3+1+61E0zMwFYrtie5iuvA+zaUS2uJPoqBNZc238egS2nLRxWD5H9YacdFNk62xwHAiwxjrkRtVwpa7lAWyrdL36nfXNvCgXv3AEILt4SXYw9LjLl65sRhoHGZZpYRVuA5r6Hxeu6MtkGj2EZrJazEL2jwfMhvb+BVqEDX0/3gqpExXqbpknpi04Sd+92QQEJdx9LvRfs3MG9dXzvApGZs2ZtcbBE8k5TAeKS7SGvZHfmA841Tk3+E/nbUWamRt99d93eQMncvIT5i8yV7sM9MWbhyQj5hEg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t1VkwW4uLzksdkSRXDmXecCM+z/ASEcZrsg9oTV1EXs=; b=t3EVKAIJcTqBgXu6y1+gNdpkvc+sELAuhXcVgDwnALwxAIvOxz0kcQEpKEHnMlORCOXsciGBBXeUkcN2wMrT9zbKI3FmHNYFUYAkjjvhwvNryUGptzJDNCS19o9zN5rXWZdkbhazwHHyeMm2dHVmmRtpWT5ehtZEdIjbR4R7uIriuq3OylCD9ye+lNSBSK6B/CgntBYoabUJzdiI+UZQ/Phj02plukDgYGwDGeo8O7OCGkgPRK6lwF+Kx9d4Xb90Z7v4mbrqCmHFw74KnkCN+H0QyVKpBQDzybzxvjg43Xjg7OV/VH2sZO+bIFR9XOg6oCsIhu0Usna1ZW5M92d3hg== Received: from SN7PR04CA0023.namprd04.prod.outlook.com (2603:10b6:806:f2::28) by MW4PR12MB6731.namprd12.prod.outlook.com (2603:10b6:303:1eb::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Mon, 13 Jan 2025 08:44:15 +0000 Received: from SN1PEPF0002636B.namprd02.prod.outlook.com (2603:10b6:806:f2:cafe::4f) by SN7PR04CA0023.outlook.office365.com (2603:10b6:806:f2::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:44:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF0002636B.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:44:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:02 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:43:59 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 01/10] mellanox: Relocate mlx-platform driver Date: Mon, 13 Jan 2025 10:43:23 +0200 Message-ID: <20250113084337.24763-2-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|MW4PR12MB6731:EE_ X-MS-Office365-Filtering-Correlation-Id: a2c943cf-fb42-4fd8-2f40-08dd33ae759f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|30052699003|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?XISsAdI2q8wcSN6vwB52bNbW+x3wL43?= =?utf-8?q?4gOKbWkB8sYhQjk/hbZ3GJy0Kbvn5jkJpMKkLFGwA2MeyoHldi6aAVnHpJTAmJ7oA?= =?utf-8?q?gAtrwmTt71FrKlAS7JyJa1nWDdDFfla/arftYhQN3D+QIB29On8pF3IAhH/YloRit?= =?utf-8?q?61cqwC0HW7RHwg6K/DkKu8M+Rv33dQ1tQ8K4rR+l84aSrA592/w9PGw1j1h75VcJH?= =?utf-8?q?cX+MVEAdeDQyiqTg9l4TmpAy4YTvlKkp/1tjjIRoQyU+ClmQCdu2OCg9ajIwGK4on?= =?utf-8?q?3O7g/wJa3qbZdJPMAZQkH5AlfM/1wHZLS4U8Hnx1gbL3R66vaX9CfYGOrgDXt+57M?= =?utf-8?q?znvoAW2vlmJc9Xh0T7jLJS/kQJeggsklPIh7WIQVqnDj44QQ9oDWU5Yqe1oq9TCtP?= =?utf-8?q?nYwzgiZUQde0bvgQmXHVZsJ3UrfuWqMQn0jacVuw2JBtp6znVoT3/Ir7VC3cZrddI?= =?utf-8?q?xTGdud8A8foaLhbXV7UwR02xHsT6WCAHBKxFOxO+/vXMlNbvUIkKhMSQBR14mCWJd?= =?utf-8?q?O4cdNzBRu8nBTrqMAJ3w9bwO4RIzH+mXudMK+g/GkkJtkbu2dr77lrGksth6X2sBg?= =?utf-8?q?f7Bk5yJ59pApB5aOfmukZSo+cX7/9fieR2F+42P3lfsQ1Im67BvEdjN4BTLta/Q+y?= =?utf-8?q?SxEn6kTbO0kr1lYZd28UEgO8Yy1el/81WNqFjq358Vh0fk7l/yMpmmbTA7MQdGQ9U?= =?utf-8?q?rHV/qSfuXK8N7fAmzqNGZzeormffIUJe81V3b6tsJ2+/GV5RHpLqiFqUspOEhMgI0?= =?utf-8?q?/H8t1YI84dSFdqxi6K5+zffkDsBQg1l0CWzlfmLM59S37IECsPq60/jjLaxOVG/oC?= =?utf-8?q?XuRSAYSGRvsqND5iex51v1U82MKj1x3GhTUhRp+EDKfvavVjdsAZQdGjeS69j5Pf5?= =?utf-8?q?yqPnr+6RitSMv5wbiq+hgA7obmBYcaTPiIpUUqgASVbiYq9OmtzgOCoQfMmlA5BOm?= =?utf-8?q?yudkPoBPQxNh6T2KAvHorZpPCH3VBlczzlWO/JyYrA5mS0cpWSrTCtLdrXcL5FO1i?= =?utf-8?q?LCo9hwXw7PkW+BU8vm939Rj0VaUGuWa4Vd8srez0zSuQ4i4gQOrnfZppJSHhlg8FK?= =?utf-8?q?vbw4xARqqdqQ3tHrGjFDDbEf9LTlOSd0ZRWNKUhpZKIcFlkMMh0wf6ejBmFwH8tnY?= =?utf-8?q?tK6gWKRx2k3t9ia/q+jGLzMK28k7HLhZJTVbbYg/cQQm2PM3Gs4Vtn5qtvj1dqcGb?= =?utf-8?q?Oz0xhvBMW1iNKzEPAwMTqGCZ5lNs71X0dHW0mmyTBApqo1d/Af6X93lRWH+kT6h45?= =?utf-8?q?4axjsY50ag/YNKFkAuBKIygK+orCmSOh7HnRdX067emcHRTIAwBNVVz7HFSLTVXaf?= =?utf-8?q?lsGFlUE9ni2i5PMVW+VWjtztAGwgup5Ge5TChY2X9ZoeMSvBXsZ2qCk4LLXDPkm4Q?= =?utf-8?q?ksU1i2aKHg7dWeaTxC9DOlbZTkfowsoDQ18KyvQvXcNX9E5RZ9mvas=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(30052699003)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:44:14.5608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2c943cf-fb42-4fd8-2f40-08dd33ae759f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6731 Move 'mlx-platform' driver 'x86' to 'mellanox' folder. Motivation to allow running it on systems with ARM architecture. Since drivers/platform/x86/mlx-platform.c is rellocated to folder drivers/platform/x86/, remove "MELLANOX PLATFORM DRIVER" item. This driver will be located under "MELLANOX HARDWARE PLATFORM SUPPORT" item. Add reference for Documentation/ABI/testing/sysfs-driver-mlxreg-io under "MELLANOX HARDWARE PLATFORM SUPPORT". Reviewed-by: Michael Shych Signed-off-by: Vadim Pasternak --- MAINTAINERS | 7 +------ drivers/platform/mellanox/Kconfig | 13 +++++++++++++ drivers/platform/mellanox/Makefile | 1 + drivers/platform/{x86 => mellanox}/mlx-platform.c | 0 drivers/platform/x86/Kconfig | 13 ------------- drivers/platform/x86/Makefile | 1 - 6 files changed, 15 insertions(+), 20 deletions(-) rename drivers/platform/{x86 => mellanox}/mlx-platform.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 6bb4ec0c162a..7d12a8f08f52 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14705,6 +14705,7 @@ M: Ilpo Järvinen M: Vadim Pasternak L: platform-driver-x86@vger.kernel.org S: Supported +F: Documentation/ABI/testing/sysfs-driver-mlxreg-io F: Documentation/ABI/testing/sysfs-platform-mellanox-bootctl F: drivers/platform/mellanox/ F: include/linux/platform_data/mlxreg.h @@ -14775,12 +14776,6 @@ F: Documentation/leds/leds-mlxcpld.rst F: drivers/leds/leds-mlxcpld.c F: drivers/leds/leds-mlxreg.c -MELLANOX PLATFORM DRIVER -M: Vadim Pasternak -L: platform-driver-x86@vger.kernel.org -S: Supported -F: drivers/platform/x86/mlx-platform.c - MEMBARRIER SUPPORT M: Mathieu Desnoyers M: "Paul E. McKenney" diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig index f7dfa0e785fd..aa760f064a17 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig @@ -14,6 +14,19 @@ menuconfig MELLANOX_PLATFORM if MELLANOX_PLATFORM +config MLX_PLATFORM + tristate "Mellanox Technologies platform support" + depends on ACPI && I2C && PCI + select REGMAP + help + This option enables system support for the Mellanox Technologies + platform. The Mellanox systems provide data center networking + solutions based on Virtual Protocol Interconnect (VPI) technology + enable seamless connectivity to 56/100Gb/s InfiniBand or 10/40/56GbE + connection. + + If you have a Mellanox system, say Y or M here. + config MLXREG_HOTPLUG tristate "Mellanox platform hotplug driver support" depends on HWMON diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile index 04703c0416b1..ba56485cbe8c 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile @@ -3,6 +3,7 @@ # Makefile for linux/drivers/platform/mellanox # Mellanox Platform-Specific Drivers # +obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c similarity index 100% rename from drivers/platform/x86/mlx-platform.c rename to drivers/platform/mellanox/mlx-platform.c diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 3875abba5a79..92a3d5be0e36 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1010,19 +1010,6 @@ config SERIAL_MULTI_INSTANTIATE To compile this driver as a module, choose M here: the module will be called serial-multi-instantiate. -config MLX_PLATFORM - tristate "Mellanox Technologies platform support" - depends on ACPI && I2C && PCI - select REGMAP - help - This option enables system support for the Mellanox Technologies - platform. The Mellanox systems provide data center networking - solutions based on Virtual Protocol Interconnect (VPI) technology - enable seamless connectivity to 56/100Gb/s InfiniBand or 10/40/56GbE - connection. - - If you have a Mellanox system, say Y or M here. - config TOUCHSCREEN_DMI bool "DMI based touchscreen configuration info" depends on ACPI && DMI && I2C=y && TOUCHSCREEN_SILEAD diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile index e1b142947067..8849c0a36419 100644 --- a/drivers/platform/x86/Makefile +++ b/drivers/platform/x86/Makefile @@ -122,7 +122,6 @@ obj-$(CONFIG_TOPSTAR_LAPTOP) += topstar-laptop.o # Platform drivers obj-$(CONFIG_FW_ATTR_CLASS) += firmware_attributes_class.o obj-$(CONFIG_SERIAL_MULTI_INSTANTIATE) += serial-multi-instantiate.o -obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o obj-$(CONFIG_TOUCHSCREEN_DMI) += touchscreen_dmi.o obj-$(CONFIG_WIRELESS_HOTKEY) += wireless-hotkey.o obj-$(CONFIG_X86_ANDROID_TABLETS) += x86-android-tablets/ From patchwork Mon Jan 13 08:43:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936917 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2056.outbound.protection.outlook.com [40.107.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2243223315A for ; Mon, 13 Jan 2025 08:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757864; cv=fail; b=LPu5G/0i3Sx4j/c05WFdcfaKHm3NFLPimVC4W5QTORjfH+h5QWJGYIAqjpIur9mnQOy2IeaZewx2tJDbFgMJ5eZsjtm96XpIEMMuDZ72wYfoeCDLuSr9xgNYW2gYXjjhajqA6a+ZBtPaeffbvAB67XA7i4th9AJbmKg9HjdBEEE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757864; c=relaxed/simple; bh=fOXasMPhAxVyO022JLtlQMYsX+Zzg2orDaXyH9KOgvA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o9R0LKtbCERfAH3t6ggGFR4y8oVe4duyWVCFBgrrzalRxdM3M3tC0HbM2DeGitzm8E2u3FGTtBoZyTfQct2Uc+R+CP97/8qYRUGGS22Zs3RrIR4F2X+DvlDmCpfZ2V5Q76nIEGnz2H6SDJDzka3aSV3U8Yr5hp5CANjZOjy7Ps8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=hU41Csnl; arc=fail smtp.client-ip=40.107.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="hU41Csnl" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uJAb1vuAhPwo4rDM3QXRcBohZ53El1xi2ksvK5m9HzxdEi1ke/yMDcac+FdWPq4jDxpxBZslUifJEVdgYTtlmeV60dsGEh6nJuMFOrAmUR+yEZTpvDlLWy/VahHY1nlgu0vLJMYdg59l2IKq4syAsHQtju9EzmXb72QPjSX1Moc5V5hZdbst9LV+n8sbdxnJHYoBq6Gti6Ver9WqpDFb8dVlV0GdTbwcHxwf79RY+Q67ZI8+tbg1DLR9fqohJKD2c4a+8qqIBCr8cTTilmQztY51l9xuoGc3d2W66++Dzdub141vbK+P9c3rpOmHzVeSQjyMj/Isu7jafY/ZnAKUvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7OeRSr6qQ2KgXRb9k9jUoEzMC77JJfo85Tjq4c7DDO4=; b=HQjTTAWLYd9fgDhDdlwau34RsSXl+LtSHRtSsG3nrHiTxkNA5QzO6IiktaYhTbv6WOTAQEpKQLuW9D13cl6y5UufdVZ+RJZEDoQLRsjSOzFkGj4+AZ03enDK26KJE86KWS12rhmHCqe1FrDR8UHQ1BqfldpJZiYnMfp3T04vY8D6UOs7K1CQuKPLeVgGw124+tU+i/3Vb1hp2xo8IQj7PRR39kt454Kx5pcAJIz0eWyhnQvwR9AqQD/z0gPO+d9jFwblE540N76gR7zVHpdho7SC8yBmfubSmtoe0c1QMuevifoDFYAS+RQe9XjaEbNwPhkieQVXqGjsWS0z7LUIww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7OeRSr6qQ2KgXRb9k9jUoEzMC77JJfo85Tjq4c7DDO4=; b=hU41Csnlwl0lOngVnGf8Z6sEaFUH9gn0LZ10u3QlymgdyU/ZwBkJ24iAAtRfaBCp02U+jCIx3soMvCONB1IrdtHzlLEWoRvD7OChQZl3tbNnqqIGuIB+jR2qupsYrKaW6P70qxR+SoZTejZyzY8ph3o6nOJNCpH7DPa53QVlby6tT9TOD2rTvXbV/XQHYm0EvowUMPFfT6BK28jPhcGTXRp/FEbNFKLSzYdrf8SIE0GxfqlVN+sBvLCIxn8HDix84knvYfzOBYFGSD72+IWrjeFRm29QipSH8Nuq6n2UpRpAVmRcs3tupJDPRpJPtRjeGac/LQj1f6dJe0K8E27ugg== Received: from CH2PR03CA0021.namprd03.prod.outlook.com (2603:10b6:610:59::31) by MW4PR12MB7168.namprd12.prod.outlook.com (2603:10b6:303:22d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.17; Mon, 13 Jan 2025 08:44:19 +0000 Received: from DS2PEPF0000343B.namprd02.prod.outlook.com (2603:10b6:610:59:cafe::1a) by CH2PR03CA0021.outlook.office365.com (2603:10b6:610:59::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:44:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:44:19 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:06 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:03 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 02/10] platform: mellanox: mlx-platform: Cosmetic changes Date: Mon, 13 Jan 2025 10:43:24 +0200 Message-ID: <20250113084337.24763-3-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|MW4PR12MB7168:EE_ X-MS-Office365-Filtering-Correlation-Id: 15e19b64-1ba2-419b-2bb9-08dd33ae7857 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: cmTAXXMxu/1X/lcF866uIvJ3lNog1ckrOAbBmoyAI5MKw1hP/lCIaKdsh94MBZqo+MmF++s3oly6HwOPsi2UN2j7tv7HIKSd2PK5N2dgc5vAdFFXGC4r5zhlp40k9qsXiIEhAXDTNrMxQyei8P9glIRZ9kB5ocZPICKqBimhb+/0k5URUd1IKlYKVbAHqxPpM87VglxAuzhbykfJuqIh/vlI/GNb19C9tB3Ly3u9Y7JitqVtiRA4EdJSZvXI2KUd4w4kWgoiQuRHZuDL0W5p7vrwNBEe+5NJH05IqpIunpw0kJj3i9yGAtLeMsP8D8Gn8/CGiC4JhbekOTj9UivQn3lWxh9+neyEKCG35n6RBv7C/mNWE8i5QC/+7V8DaWg3noPwSNSnRvIQO4NhNBPlHyQBWvPVYR5rXIdEBEMvU2zLlCy1Fn5iOj4Ttq64xpHBGF8MgYbCQx/8z5zzYJJOFJX5EirXI3I9gPsVmvvceOmsIfWiecCSm8lk6hAp3dMPJUJuv4lF7tL34AC8YDCfrlT+/toVYGNdC4m26ZxVy97HvA6pLqiT0hK+qvkM+MSi0+yoGS1d/F531AmPdNWG1llCv503g46HH7DOSFmUsnGyTeg9NDtRCAo2U6QcUNcmyCHnVJQ/ttZ56s1hiF+f9/2IlBkO5wuJtQbdvcIGm14X99TL4SFknsE+cjE3Co+1SIa32qCYsMr6mVjJmu+4dMRbkn6zeJN4JZ3dFJ5+EIzm1y4DjRQlkfbmZwhWsFRNTUPIsuEbd8ujTMHKMKx5uwIy3qzbiKa9taor4xNEUI8f8pyWrwDUL3MBMA8Jg3wgsyuLKROupTq2zEl9cTN8E/CdEZgq8CsvmbQ4A+tGDJ5y4uForzMvtkdL/oXYrwP1cyQMLNrOvqS25Co8+8DL3eq8nrWE5yN9291gcb+8euWwHxU+gafBAnVMFGWsEL7l1oPoUUtzh5aSrBSvkgltWZgj9QTInqbf8fufqwzm4xPb0t9VL/Nx7ZXW3qYgdUkICh47Bwmes8qO313pPJOQdt378rB06GP+R1hPt+fUHWagtGR+LYA841l0M4WkECWU8QNdyiTzd22NkIvK0eKIxGgfziOtz2kJF9g5+DTxg3AqVlgnP+hs8/yZgzfMF4BaZZCW0oTonS6R0Q1NMvASYdmxdLjqNF0pMPCY+nwOqMrJNidA2ng3MtYpHn9wESXu0BGB31RU32ZYCLkWJA21khvWt+mQYI4nhTNkluonMGPit6awERKyq6oDKMqJB7ft3krENcQnOj7O68a2taM0nzgwCKt2KTJ76vJv0vVaSzhW3VT3UhCFKmGH74yWWPSmCx00ZRcPu4mlspYv1IPPY6xOrXAks8ts1T+4b7LXugEa4PFgXIbjSSA/Sw+3dlf+eAwcd8xJYtD0jmKsRjkuflAtsunce7DnJUlzzJvIC37OuC2i+OmpMcsUddMX4YHAqcTsOZS3HQ+HfXZcrnraTdg8y6V5cDROjZCRlhhlE7Q= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:44:19.1220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15e19b64-1ba2-419b-2bb9-08dd33ae7857 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7168 Remove redundant spaces. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/mlx-platform.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c index 1a09f2dfb7bc..8207447aae16 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -2247,7 +2247,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, }; -/* Platform hotplug for NVLink blade systems family data */ +/* Platform hotplug for NVLink blade systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { { .label = "global_wp_grant", @@ -2279,7 +2279,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, }; -/* Platform hotplug for switch systems family data */ +/* Platform hotplug for switch systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { { .label = "erot1_ap", @@ -2387,7 +2387,7 @@ static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_ .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, }; -/* Platform hotplug for l1 switch systems family data */ +/* Platform hotplug for l1 switch systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { { .label = "power_button", @@ -4401,7 +4401,7 @@ static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), }; -/* Platform register access for chassis blade systems family data */ +/* Platform register access for chassis blade systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { { .label = "cpld1_version", @@ -6573,7 +6573,7 @@ static int mlxplat_probe(struct platform_device *pdev) } /* Set default registers. */ - for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { + for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { err = regmap_write(priv->regmap, mlxplat_regmap_config->reg_defaults[i].reg, mlxplat_regmap_config->reg_defaults[i].def); From patchwork Mon Jan 13 08:43:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936918 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2041.outbound.protection.outlook.com [40.107.223.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FD34231A45 for ; Mon, 13 Jan 2025 08:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757870; cv=fail; b=tGJAPzmF3/Jt2K7q6azg/FBvXtqvJgtlnNzqnWWaUxSx7O3MBlnWIqya2nUbd88d8U7Kxu8xX0HyRollBZu12HNpxJW3vfMx6yTOI2oCpdVa/k4xrJmwTdbQXq450cJL3AEIo5ZP1/sa9oFXPvipcjHHAiAZ9MQVZQF71o6bep0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757870; c=relaxed/simple; bh=1UwpzhNQvMCufmER8NgOMZrTt2zm487oYz1f+wtefig=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bPBZOIw+0V3bLYyYKt+cIpeDQGbkkAQ1DH522LKD4JPPU+eCFFumt85ytXjPEPXMfboj4AJ8bpVngbm8Xr7p2aulVVHy4wDbKw2XZ76HPYaajXYgUhev2Q+uL+TeOyj60yW05k+RSOTa47R4w4OYIG7byZDqZ7xx+D2wFoZ4u/0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=fwB12JS1; arc=fail smtp.client-ip=40.107.223.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="fwB12JS1" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Dl0YE8vtWOnLBPvmtV4mPxm5C4kV5VnNOjdLtC5rt9NCa8X0cMPwkK4WPJl6VkLLKM2MojeGlSr2IHzqKTWSPEpEF9uRhDwtFG43gUDZGOpVnj4FX6kZbI5rTahQyMRQjYhd5KuRlBticg2nr/OwJ4fKFcJY+sQvTn///XnMcHP4x+h5sBTxBtoY5DC/jrvXTgkhlPN1gCucn5bY7rJrkRyXy8Y4dnjOKJjDl0Cxri3lNZohLF3OlupO7eVEGGMVmmdUvHVU29sO0iSv496241b1j9r0ueZp2Lih9dNC0kgsL4zDK0upVKAuudIai/hLuDs4XQJIq3n1WS4Fk6K2QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NolxlxjhTQwMsO0MIZlMyjZnrOVFHCPAkuGvtlxz1FM=; b=dSx/w+QW6eF/3NDvlP/ub0xx1LGRGjea0luGgk/WUcq/Z3iAM+8oNbw7CYbK713w2Rc9Jsii9PeSYLzjc+mZjSBeIjgkirOS+WTz8ziIRkWJ2EjxqjzhSc5TP+CXK8D/8rGrujOGPQ20OU1Y5vn0ZCuHM5c3o0Zg3+1AFgcef1t2XU3T3ukj4ldqUU0VUlLFDscGyyGIo6js2i58xMCSvjb+oSvcqJgZzubVjQh1TOhCs0dkkp3vx7qeFKSxorGhbj7o+Wtfi7iXyLKxvNCM8cDmrWj35ellSJrfRhvzKiIVKqYzVqdN7QkbnvqvGiwof7Q7BT8l+41PBHTnkk5WAg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NolxlxjhTQwMsO0MIZlMyjZnrOVFHCPAkuGvtlxz1FM=; b=fwB12JS1mT4mirIpasEVu0W8Mz3rCktlkJSuU12Lhdr+FP1igWUk+Xin26bzdWeD836L10fi5Dg9cm16kwC6cdfi9OYXfXNvVqqt+DjApIZ/jYAzDVSnJ4CqXLZj51jb7aqdgsY8rdiccFm/FLHP6XvuuRv0rO6Q3aTGgAhXXQAk9muAu4P1HJrBRXLBPg2y9C/M1tx0wZeSElCEyUe1Iu/w49x8f38bcYjh25LyQo6cnBDPJ0kL8tPX3tOIP5DSyeEKpJV5ioJGp7mLEYUzs12JwjGM6SadLafKZqoakNLzHIW9xqCD0cgdQFT/dCW5CwGp+/ZdPF13z2MGcQ1dgQ== Received: from SA1PR03CA0007.namprd03.prod.outlook.com (2603:10b6:806:2d3::16) by SN7PR12MB7180.namprd12.prod.outlook.com (2603:10b6:806:2a8::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.10; Mon, 13 Jan 2025 08:44:22 +0000 Received: from SN1PEPF0002636D.namprd02.prod.outlook.com (2603:10b6:806:2d3:cafe::14) by SA1PR03CA0007.outlook.office365.com (2603:10b6:806:2d3::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:44:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:44:22 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:10 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:07 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 03/10] platform: mellanox: mlx-platform: Change register name Date: Mon, 13 Jan 2025 10:43:25 +0200 Message-ID: <20250113084337.24763-4-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|SN7PR12MB7180:EE_ X-MS-Office365-Filtering-Correlation-Id: 769b6784-5a71-492f-a2d8-08dd33ae7a6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: /oaaqnxwyfkob6an4oMIrnb5mgycTpKzhaeasHVAucR60VN/lpGCTNQI+5J6201uD58tKC9PCxPrn66fNf+FQdD3r5sXU9V5TbMJQhA8Mwjzr2k4/12iHsnQiWgNPGuonoHwTajFib40KMpnIV4wKik/SkDSle7H0ZAzr4QGO/KiqZy4fbx41Z2BirOpn/ORobk9fsxD1Vm7it+wXQPRSpAGq4xF0i0XAlNXMvEn3keu54mh7zXC9XEEdhxOuuWaMRQ9JixN12CMfRb9liZJXjEaNNt128T278m52l9YUc2yFP5XJN8E6eSGeua2xbkcI8I/58ytp4DlUKrv080Ajn8GCBJ+AqCV6Y7LIKTcrssTxNSUCoBC+oYYdUN3nD3Rg6Jx77NmAgNo1T4PHMCAEoiVfIxGfCI943YdaWbIT74gTDXrRmdw2bXegbQP/GfX4/1RY1IXCK6I4/peKr+InM0h3qs7QSlizE5ua6dpjuCekm6IPj5Ghsqqb6t+QhUgpmn/EGnzwJAT9l/Y+1Ps47ZPQ2TYagsx0A1UycL7IBtyxNqhhosBJbI93uq43hNvYqdogZT2vYrdsj5vPAeDyufDc5yWf5DypZGbRDfPQzoq8A4VxRvEf5JQ1qxFvGzA/CY2wnjmiBvvgLurNzBkcuyPMBNJ5DzL0mF7S7RY6rmIcx1dID7K7byrJxhyjCE4kbvtqU+Ipq2PzD10OjZtUbrsDx8ViZcyYWpVhLehGyeZ2YZxaYXh6g0ssgS72KzD8aRpTCSr9FRcg3hgmz3nEueHnQ/C73YFlukUbjHumRwhajfG40ZMrgGk1BXZ0Y32PMjiKPGpSdt1ghV4PY5aMfPaXmxDmUkKaNpcRvpJaI4Lg5uz41wfReYw/WzO9EvgBp/LaWjDSvkd88YPCqMGS96XQwXlmWLquYVCzj+5Zf7qpyQEowwXFHuv9ycCjoWyGlyWiM6ndif2ipznm8LaaUKiTqHgwBwe2uQHdAGO9OnjpUSEMszx0bVEyih8ccrBXLNnOnZfo4MCqQzISFe60oC9xpRwk16Y+8nFBPc17fjP17oVsldokfuyClRHWphVyUqTlgTpyUqHHahpv7CDWy7Y5LeyZVL5PzPe3XBieGQEZ7Ynqo82SJz/ZsZQOLJmMKydnW08YqVgOah2AEtKaDYJEDuNwgXKw0264LADsjmAdPyRK++w9IWV+8P7Q479fuiUXRb+YUpzm5h1wofKClcdBP59xQ8aqMf6z91uTpiQ01yhbWXTtXHENeOG714cs+NrqJbKNTrUN8tO02PBeBS0hh9qqlMwKGhROEVP4X/FfgRClEsPZXGkHHT5ZT/i78AdUNMaZZcEmbYXom+4HSRgwE3L34bce9BsMzze7RilaFZBgtlHAtIjO9Tou4di+KW0RPzir1uJxGU/KUuCaJxz8N6FrgAvJBATsc6JiPtyljOtPSYoO3/165C0a+rc+2P6cqOH2ilgVJnYTj5fTQPfixqBxwN/69I8t3gXCVc= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:44:22.6403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 769b6784-5a71-492f-a2d8-08dd33ae7a6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7180 Register 0xd9 was repurposed on new systems. Change its name to correctly reflect the new functionality. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/mlx-platform.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c index 8207447aae16..bd3bb06ff8f2 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -145,7 +145,7 @@ #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 -#define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 +#define MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET 0xd9 #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc @@ -5050,7 +5050,6 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: @@ -5186,7 +5185,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: @@ -5343,7 +5342,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: From patchwork Mon Jan 13 08:43:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936919 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2070.outbound.protection.outlook.com [40.107.94.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A67F5187554 for ; Mon, 13 Jan 2025 08:44:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.70 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757872; cv=fail; b=QHgzcJFUy1KZl86VxqQC2W1jsDmlRkyNnQOMwweL3Fz1GMmrgoczdSFq8JxFNnEX//B7heIEa7Bd03YZ3nNoCf/rNS1/Hoe32BtrRBJe1gcCCeeOYbkkZ1FGlJc+KJvGyWGrJ6uaUbOlCclgZrXSTRjBGdiXOoxd7D3ftP0M4K8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757872; c=relaxed/simple; bh=67Kzs4hbM6GH/F1cHitOcDbje/kTVRrKd1hP6rgPzBE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C+RW+uzrWA/HsczjkhyBn8+Ptfag2cjgBNfZMwqwl9CLDegdZ86dy5ExVg7kaO7wrSyDLn00IEzK/bnLaiOXJeq3Ronqqwqo7SehVnVPcuRTJjJs5E+Nl+ji6w7JoCEfgXrML8WqvIW60slMwGoxjmcnrnIL2YiHt+v+2kNW9aI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=HksleZho; arc=fail smtp.client-ip=40.107.94.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="HksleZho" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=SgKk/livEJhNzaxr1lrjslHPtc5Dp+VRjz9A6dJwajjBZ6O2IsmlBfl2dpqP0wExrfb+PKk1o1hiX0ELBMlDYzDLKTML1epqiELDVyxRxzC897X0Y3PvjY7T7e8+ATAcW780yAXTeIVLTglO//ntce/H3XWHbrNDDzUCfflvAWUqysE4ij9HC9UvqReIisweqtsRjLv87EDrnIr8+r+C4RU1jzwHn+SVnfRrWKQAeiYWveALSLTx4SHkKiO27+J/bBC3Gt7REdNfla5fLLv0YoMzUYUO8NPl8RLj/7jiwpWaMmWmOIHghcVznvsKVBRjrSk6vdlCzw4Fj14yHhpWxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=l3s/5943YPllt4mq0NYheL/grPLWxI1/6HbAyx1QBFI=; b=hF1/EJEMcaiipPue/KN3q0bmR3V8LA0nOzPec5E7n7IloTstmAUOfzQN5qDl8JYrkpxWp5kjhsW39EmZmCB7JzkpHfroXrOsP6N6QYEFfrn5XNqF5ri8kUJKBxGqFytIiI5nhqi1tS8JHt8D1YIlPEd92b8Z8miAKIPHZOcGkK2uw1JeP6aF49r2NGaEkhstA00NM182AOfjL8LSL6TNVqkypbpN5vph3kPyaNWvRSM1VdE2pA0kQZtPrQHx1GEUBNNSA0anyRHZJYWThi5OsN8W5lia5VHJUo2VNm2rEVH5cR2GeDeCAfjJMLXIpM/34UExgT/WwJer61ItXiQ3ew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=l3s/5943YPllt4mq0NYheL/grPLWxI1/6HbAyx1QBFI=; b=HksleZhoRELAFWnzy6zg2xZhjOd9WWazdzyIpn5hFNuAhek8mwOZ/gACbTxxg8f+WRcyeSfpwOelpjhNYwlKDeWNnNIsRQsK+TJ6v5+akVQnVs/WMqokYTnysvE4/tcmOsp9gVGTGGkoLvDDM+DW8itbYGFAQpdejIRjU+up9Fjma6juT75VjJxZabQRNIPbU4WbvgxjLq8IgXGtxX7S7Zj8IJcSNz/D6IUH/ickVNO3h8eKLXOR4boXNH5hJa8maIb/CU2qvbqmY5X8Rfh90xowfzABhKPMWuHrPQEnuTnm66YwlHAnH8ZpjV8QvrhA9UAQn0hE62s72cCYqH6Cpw== Received: from CH2PR03CA0023.namprd03.prod.outlook.com (2603:10b6:610:59::33) by SN7PR12MB7449.namprd12.prod.outlook.com (2603:10b6:806:299::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.17; Mon, 13 Jan 2025 08:44:27 +0000 Received: from DS2PEPF0000343B.namprd02.prod.outlook.com (2603:10b6:610:59:cafe::5c) by CH2PR03CA0023.outlook.office365.com (2603:10b6:610:59::33) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:44:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:44:27 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:13 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:44:11 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 04/10] platform_data/mlxreg: Add capability bit and mask fields Date: Mon, 13 Jan 2025 10:43:26 +0200 Message-ID: <20250113084337.24763-5-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|SN7PR12MB7449:EE_ X-MS-Office365-Filtering-Correlation-Id: f591bd69-c1c8-4fd6-29fd-08dd33ae7d49 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: czInE3zgP6JBDSDyKWpYPRRcLKS5nwRkGLKR+CwFbV6RrTkVUg2Nc9t6w38RkBvFBEjVyUxeCYfv7fqTO+lBceybZDLyBh2kXtcOcZxzLZuMDIPW/DIz7Rxs6oQOioFbMdf8G0Q7D8cq/wRqsljm/Ic7z3pJCPUmPhGTovY24ttpiHQjTZsLduTTqbjHBFTOQC/IUlI5PzFk9GsKBLGQs/2/o7JUaL34aPj+/T/NmRZdUVuC0S3/Le/EUY7opWZfDnp/LmX7YeXaJ+92YBfz5XOZSpyEsNqz14VYXjiJeDhwkoIYLKicrPiU80vF1w98s2Z6TLt8wBub5Nez9at8tp5FFMYFr72xvORrm4rLQZSnAxSbHF/Fwg4Y0b8iGeb7t+ybdP17VpkTJ1LvoAk5TkTDoKpNYlvUqPSqPeClUPqnZUmyoVOTAE6A6j3I+0H7bNh70NDacwvWiprURH8RTEbLJeYiMSDJfOUx926Ix9WUqplCR6dBfZA4s7I67Htqi9KB7WpgtOMWptm05m0XtBbrKe1/zyPlFWiz2+uCnJGe0CQaqBxdUOsfHPGUI6mitFREn/dyvd2iD8mI78dRY05kbQTKGzhfK5NnA6ncyK/BjANowvqjvYG4TCwHHrQFMQ+xqF4QgSxr5s0Eni+I/cn+wP+TTEJtVXS88nDeurxNIoK0s5mLByHHQAbSUQ9cHyW5T71XwYTkZGD2mTefNE4uffB1zMRAlhp00U7Dyl29ylzH7SisRxS75yvt+QARRKubTtfT5U44D3bftrrUF277s9zToXwaV/I3IbvPL2JcKxHpdASLj6wGAawgQNrdiD94idQ3NhtzAABMrjbMQKG/NpQ0kcZoy40jGYQwBLMzHbpRAp0AHUDcpU/rW42AZIK6rhpXCKmJTUs7zTc6uVfXWs5lZKB+L6SsGFV4F9Ee9z3zpGhUeJTH1tHt05AZIXc+DjoW86IinJN5Ft2ZDOaWwis9xRaTVtybk28zoGfaIIAUsp4NqLja8NQDbG3A24SvjBlozdSQcGw5vtt6PAfW0vcoyEKbHmpvTVJbRL8iyD/jdRKXeXxipfr8j50QcO6t7+rLolNKV/ztbZcAoMXyK9uAGTJ/IIc+vFnuLPda9cxQBQsAIRm1TeA+YcWWttSazOUGwoYnnoTNflLgFo5IHGde4FheyvQtKfrwCdtgnXFQuNvgc7ZpHW4cnDobVuVlbznK5tmnr52I58XokKEWodh6Sve5TM77EUMGkp/GmvL85/8ANSNSGCLFf1MaDmpbDGmpoVoXjb16aXCPIt6ftZsTkLtf8DVM1zWzKYY2Uwhb0iTowZc72f0zF+2zdBLA2VQ4UQjlY0C15gAKjFPQ3vxwKEHmL7IagZN98znbFjACFXp2N4LoasHT3Yo5VpLCwlMLSASrtEPhdy9BQk35wT6tS/jCJhUYwp8FbrlNI4o/Laqa6Bra/TgmDWkwRN1QWb5rKxG8ebcul5wiwJoIb1Gz6pE2scbKU7Gba0k= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:44:27.4345 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f591bd69-c1c8-4fd6-29fd-08dd33ae7d49 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7449 Some 'capability' registers can be shared between different resources. Add new fields 'capability_bit' and 'capability_mask' to structs 'mlxreg_core_data' and 'mlxreg_core_item' for getting only relevant capability bits. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- include/linux/platform_data/mlxreg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 0b9f81a6f753..d9f679752226 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -118,6 +118,8 @@ struct mlxreg_hotplug_device { * @mask: attribute access mask; * @bit: attribute effective bit; * @capability: attribute capability register; + * @capability_bit: started bit in attribute capability register; + * @capability_mask: mask in attribute capability register; * @reg_prsnt: attribute presence register; * @reg_sync: attribute synch register; * @reg_pwr: attribute power register; @@ -138,6 +140,8 @@ struct mlxreg_core_data { u32 mask; u32 bit; u32 capability; + u32 capability_bit; + u32 capability_mask; u32 reg_prsnt; u32 reg_sync; u32 reg_pwr; @@ -162,6 +166,8 @@ struct mlxreg_core_data { * @reg: group interrupt status register; * @mask: group interrupt mask; * @capability: group capability register; + * @capability_bit: started bit in attribute capability register; + * @capability_mask: mask in attribute capability register; * @cache: last status value for elements fro the same group; * @count: number of available elements in the group; * @ind: element's index inside the group; @@ -175,6 +181,8 @@ struct mlxreg_core_item { u32 reg; u32 mask; u32 capability; + u32 capability_bit; + u32 capability_mask; u32 cache; u8 count; u8 ind; From patchwork Mon Jan 13 08:43:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936920 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2088.outbound.protection.outlook.com [40.107.244.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A728233153 for ; Mon, 13 Jan 2025 08:45:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.88 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757955; cv=fail; b=hltEbVlZHmcLCvNlAlCaIPy8T7U2iuJdDDgHDXJks4mP6aCh4h96F2olc3ydiUdQRsvu2gaU7hXmcNvRVMx1EkrZ4DxB6LZ/erM7eqhFxPojtoKVC9up2nEfw1kn64QtSZ5+F7TMrqbYJnfF+4hZ6j+AGS+Gvm6cqEqQGafmKEA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757955; c=relaxed/simple; bh=slgIsnCDjpuCDAjpbJRmmt6GVWKl6sjvz7ghqpWGR8I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kXjKLX776RLaYoCR+anU3HMxl9sGAB9VaqbA2NWDDkIvzjZo8SV5vJH2HvN17saJO47ro+Rw/cHXOIN2pPZ0xC0At2Wozo7KyxkFnx7Fm5P1CckDXmaqGuARaUYmdIcPRMSNf0Sy9AJCgH9IK+Y4gRaJmy4hmiUxLyJIfCMRvcQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=TUrTsChy; arc=fail smtp.client-ip=40.107.244.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="TUrTsChy" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZtF0y5Pz9zqcUcOFejsyCQBy9w4r6zxwoGOHi6z3b6sWP2RbXeOb0PktqR8r/Rx0u00OjrD7kxfeL6N6QhqadwGH/zEi9ZPdciis6gg8ABcOzWIx23xYIZMzmZ1NbdK8OZ8exgTirri4gt+FU+mMkT4SmH6ux52dlS7zpLKRMSLuG5czNee24gzanCLRaLnR3IWT1fUlvDrtrtgDXCg4OOD8b+jwoTSE7SMC8M/FrpeafH6Ajp2o7IKp3Zi0Sm+4nc3A9hqHnZOTAmgAgyBsNnzkWe7UngjOdMhrPEnO48yL9/rPj81xuwtP1GZTidgdr5+onzGEcYWm+nPrexfKTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/avKyCENM+ZTXtGNAoqJqAQNA0lodrcGv0oTC2FzRw8=; b=mhyNmUU3levLV8EbV1+hoI7H6NM2KfUSSGjR4Xm7Ct8Fp0VzQmOinWw33P2mtEwbBmsAj59bjsqfjgblhy/UAWygnHQcsmsbBC9VUdChfmImidvJLYVgK5Cs9Dj5zIXQa1KDSUlPZsYRwjZKi0e6oOiIKcV/lf81G352go9SE0Ogngcjt4jfWvwB5ITZUxac9v5Yur24AuIALlc4dJyrdcGuKdtOokMRdFJu5vvBxo5wyS4kKQCu08Gr9TPQ6xPU2GScY0kPIXtNNkWVUESljWNjR/8NRdiyu5avO5m03hXkXtqodZioyP2nwMmcNBq3nOzN3zV/7llQC8HqQ1ADyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/avKyCENM+ZTXtGNAoqJqAQNA0lodrcGv0oTC2FzRw8=; b=TUrTsChyE3kr8KzMhJ21N1jmXXkT9jJ0FhuIZUXH7fwdGwg0zObDgwKqXHX/3Vewy7NlZHKI979IRI0kYHwUXQHvevc68YunFK03YeBYMei7FuGJghPhEhd8UBj0fVIAeWqYMU1xOZsr7k0GnLG62aObtd7qMqiK0OH2atyQ5wRiM6ISXNxTbB7Dg4D3JcEOgRtRgZNaEilGbZxzmK74YynePsnl6BoY5qxOHG3RvvvS2gHbB54rHEDcmINbfKiyt/0K0Us0ikAXzxBe09PIkk7I7lfpn6s7FnATckb+ShIuUEK1qxFZY5py9tRP53YSmtq+IrNJOg6Nt8bGKI2RJA== Received: from CH0P220CA0021.NAMP220.PROD.OUTLOOK.COM (2603:10b6:610:ef::11) by PH8PR12MB7448.namprd12.prod.outlook.com (2603:10b6:510:214::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Mon, 13 Jan 2025 08:45:50 +0000 Received: from CH2PEPF0000009D.namprd02.prod.outlook.com (2603:10b6:610:ef:cafe::8a) by CH0P220CA0021.outlook.office365.com (2603:10b6:610:ef::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:45:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009D.mail.protection.outlook.com (10.167.244.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:45:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:37 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:34 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 05/10] platform/mellanox: mlxreg-hotplug: Add support for new flavor of capability registers Date: Mon, 13 Jan 2025 10:43:27 +0200 Message-ID: <20250113084337.24763-6-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009D:EE_|PH8PR12MB7448:EE_ X-MS-Office365-Filtering-Correlation-Id: ce10d5b5-42ea-4044-bae9-08dd33aeae1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: +Bw5ga14iGq+RBXhjDmBCCIvCGBbXzFdtYbypgp9AxUdjNUTgFEBXF3zxFHtz4ALt5fkHv7tAb6nZ5QS21lbYqsPBEw3Ig7IouWk3a7Gr5Ch9OgSHLT8J6BxPFND7o9g3rLe0Nak58DKzabGHP0U208/Ym/NP8AU4pWnU7KgFZ7/5FLX5uI2hteuxn29Uji5MovM1w5s2hAmhpqYxVvr0bsjqoQ913PyC2RKLqqowHN3QVyz5EPGa7cYWAScMYPVrFd/DClJ5CRAlsSVVB2EynwWS3GfHFeTXka6yF5BGd0j1TEeCfETVIYmpEZPM8vNKfKdF35zx30aiYQ1PuD0R8HVHggkrNSu44Tf2YssQlwjvdVBG/EdgSdlFK2vRzNO7foGAU42vSl8wc4hHFmB0qsSJ/qLHUKVkzLyew8Q0JK9hcGoW2sI3OyFomQpq3A09mg/8DU1P1EtFDUv1goPnT+iRD4E5tu7zy0MLsJi8g4YHgM2m60Eqv2g7XoNQ8tLYh+Rol9z5hQqzc9pXIsFxA5/PgfDvgAv4d1gMsMTxkLnbb4ZNDo9jOTkRMiFjqCzXzn8TaKsykalULmYMu8ImiSC1fFVXpAEs14sLje5z3kQlWjOIbb/llEe0l3crFRsg3HoMzjKCHWF20PirRNFxgsWz+CZ6jeuAAm+XTK+KqL/lGVSR2MviuHaMz2Ln3swB6a6MqZNH52Mu9Mx+PVjFsdiuFIRquiIhKe2f5IA5aozDo4Sztavx8nRPWrEAHh3/eKfRHhS1GpnCdku59/JS76xaKHUQsM77O5KZFf4icvVXUbfRV2nBq4T7dZKZQaOCqiEATxHcwQI0b5TXel+RdO6r8U3og4N5A6AVwaZyvkbi4Rlxr1emNpzaBFNqkFp4B4K0CA07VspUz1P+e3hrz1i/xiTiiQR+KO9Iyr92Uq//HX0+FGEmJ45BgWJIMTBr6iEwvKHGVsellf3Av3vmbb0ji1rwMtIw8oj3xSev8ts2vGGVPkMf60prs4SZwVnJAfpgtfmLOWxOWIcgX2byrU4F38yk25Rs9jnSuZvnpKkygfSv04vvdgwPbcuy4YWpHFTFCIfwetjTk8pTAVK4cCiiBKg6dLTC+v4Daq/jd3y3V5NCi89CqTGD9jrLb5as5o4iixy8nDbHN6m3AklKfJ9CTUw2Jvo0ecoduRDVwuWM0v647cQEkxdANbYM3p2TXQXzIT5gMaGYINzlmL/RMsqlcBSESSOnPzo+deQ7wP67SH6t0FLXvGULg+1x3jFaVJnI9kPCskhE9N35m4zhlcpsQBDvxyRc9YoYdTzV37vX9f1LNozrp/2ULnJSlFzrOEQK6EWTXjBVjP0nxti2AJ9LDBv6s86Y+y/8XNUubDFSDu5GS0xfA+YR8DmYKYmOhSeNlF4EhvElR+z1+wmidf9u9g1P/sukTqs69Wxs4IiACItOjvt2psGfdFyHPzQGOmhPdjHp5QctUT7klVXowzW04+YGacP6ubkVw80YBQ= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:45:49.3269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce10d5b5-42ea-4044-bae9-08dd33aeae1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7448 Hotplug platform data is common across the various systems, while hotplug driver should be able to configure only the instances relevant to specific system. For example, platform hoptplug data might contain descriptions for fan1, fan2, ..., fan{n}, while some systems equipped with all 'n' fans, others with less. Same for power units, power controllers, ASICs and so on. For detection of the real number of equipped devices capability registers are used. These registers used to indicate presence of hotplug devices through the bitmap. For some new big modular systems, these registers will provide presence by counters. Use slot parameter to determine whether capability register contains bitmask or counter. Some 'capability' registers can be shared between different resources. Use fields 'capability_bit' and 'capability_mask' for getting only relevant capability bits. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/mlxreg-hotplug.c | 23 ++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index 0ce9fff1f7d4..3e480c322353 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -274,6 +274,13 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) if (ret) return ret; + if (!regval) + continue; + + /* Remove non-relevant bits. */ + if (item->capability_mask) + regval = rol32(regval & item->capability_mask, + item->capability_bit); item->mask = GENMASK((regval & item->mask) - 1, 0); } @@ -294,7 +301,19 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) if (ret) return ret; - if (!(regval & data->bit)) { + /* + * In case slot field is provided, capability + * register contains counter, otherwise bitmask. + * Skip non-relevant entries if slot set and + * exceeds counter. Othewise validate entry by + * matching bitmask. + */ + if (data->capability_mask) + regval = rol32(regval & data->capability_mask, + data->capability_bit); + if (data->slot > regval) { + break; + } else if (!(regval & data->bit) && !data->slot) { data++; continue; } @@ -611,7 +630,7 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv) if (ret) goto out; - if (!(regval & data->bit)) + if (!(regval & data->bit) && !data->slot) item->mask &= ~BIT(j); } } From patchwork Mon Jan 13 08:43:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936921 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2089.outbound.protection.outlook.com [40.107.220.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2967014F9F9 for ; Mon, 13 Jan 2025 08:46:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.89 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757967; cv=fail; b=VebARyr5RRCkSpnensJu0rHd2jNXLh5hRXKCTrkfgVT3d/OUsfJdWRCX0oeHV/v5xSJ6W6M6FwW6TU2XAuSqP/yiQ3sqysqlI/DBU5Oy5NpR76L4y+7nx6A6JtlwjwuUGZrVq+EuwwHFYeZOEJH2yEl/Xh/NsFbJJD8qaL8ZN2E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757967; c=relaxed/simple; bh=2u18qFSqcP5zaBMVkRJUBviU5An/MHenJCQxKPdhZOs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q0kjZT17xiqQqX1lTYgPdiD/zEjjsiQz+QgC2geuCc4N5zomJl3KC7l9lTsUQqliMM/JU6zA5T+PBKnCWtGmdmHb7ieUsy3DDAhOZOdpU8tb4+OijyQkohzpcXQEYUFW52RDI4iBtw9h4TUm5iil749zZmoZznt4HgGcGqjkeC8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=I289Y/jj; arc=fail smtp.client-ip=40.107.220.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="I289Y/jj" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KMqw0O2Xopkf+hybNwjtz14TqzDs70i8m7JPaN+Gj5g4j5fD3CgBk1E2CrCQ9nM4cNaMh5bHE7g511Idh2seAXKN+M7iLeG1qXvO65h4oMWs2boI0rhKrybXiKs3UV18woYDF4zIlOgeDqS9vfIjmYZGk8pDj43Z0yzpdE72W8CE5BV1qTYJHwauRQuSq+2TtZfsRcQtMcnZD6FvNcXxMAK8RBwCXTm9SgzkbbEy01BhHTBoYmLx1K9VWUUEokmuLlXKfT3hnp73izN3tOEG3sPNPIOl5Xhp2OZrFCF7/zLg5Qh6ZB6YucDKDgewdfZeqOUd6Ej5bAFTbK3NxNEXuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zB27EZ7FulJGErm011Ef6M9koA9fOwJmIAeR9T6PMYg=; b=rL1C7z41vOBYtlpl8SExW0mztRgc3UCS2fFiyd/gu4gfHRRPn8WJ9V+HQP6iffHZAFLCCUglPXxfA5kJGPE89w1QDSRwoEc0pT/Eyb48pVItN9OL9wnPC5qMHnD6yzPYzGuvy/TT6CP6suMG63m+/Mvv7H/AYkaHzNd4HwEbLyWloJWyc4K+2ZvNYfqHlDsLd9Ifi8aIkqvS0NrMVhDauor1A3GzYROGHLHqAmsonyzRgNphZHe91AnctD8r/FlBHJzAeoDCtbbTMl8xmQhLWKyct4/EdVI7twUFDjZARIbRgSprfMbNClpANJRbNLoAIrfqbWhMwoCG4nG7KtqRrQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zB27EZ7FulJGErm011Ef6M9koA9fOwJmIAeR9T6PMYg=; b=I289Y/jjO604S+mi1hy6PuzCw9OpLuFD8ySBae5bxCshPIM70cot1tD7wARkMW1C3qbPGRg45qniMKqRSATEwPNFwxVA2PGf8+0D6y6ye6K3pMrzT6miBDr9JwaxAImHCI2fHm2wbiudlnaGLk51MBQFS1Icc7UX9MugwiiHqoU4zDlgC+Bn71/z3EjK1+ynmSbHd1Z0x6Nx7cJKNfsiuz6nSnKiLNymL+WnNd82XfldRGiuXQ9zIfCEiX3/Oki5quu/3YeNU6Nlbqeu+WvdRtTSbAtJI1TzIV5XTmv2C8ZaMZvOn3OMi+cxs8E+cYSsSm+0P6b8uuy/rZdJnU7ZAw== Received: from SA0PR11CA0048.namprd11.prod.outlook.com (2603:10b6:806:d0::23) by SN7PR12MB7180.namprd12.prod.outlook.com (2603:10b6:806:2a8::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.10; Mon, 13 Jan 2025 08:45:57 +0000 Received: from SN1PEPF00026369.namprd02.prod.outlook.com (2603:10b6:806:d0:cafe::d2) by SA0PR11CA0048.outlook.office365.com (2603:10b6:806:d0::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.17 via Frontend Transport; Mon, 13 Jan 2025 08:45:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF00026369.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:45:56 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:42 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:38 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 06/10] platform/mellanox: mlxreg-dpu: Add initial support for Nvidia DPU Date: Mon, 13 Jan 2025 10:43:28 +0200 Message-ID: <20250113084337.24763-7-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026369:EE_|SN7PR12MB7180:EE_ X-MS-Office365-Filtering-Correlation-Id: ab108c0c-c2c3-44aa-c625-08dd33aeb291 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?QPWVIAJ5dwyktQmah3xQsU9JmDnxU/2?= =?utf-8?q?Adr72FP/wu8A3xyAjOZCKVrX5LxIVPTshpuLV5L4Mey1JDhhcqW6S9wcb8nGESXwE?= =?utf-8?q?ltqUoj6Ktbe7v1ZjQYWnhHn8txCQoWlE6le0tnpJpaSI5/+eJwjc5DPnWkzn65Aw3?= =?utf-8?q?nLZvY/acQEl6c9uBK8iQ3C5wa7rObWgHguqRGiFdGguPDGA6+voD4Oxj6CpMsHYk2?= =?utf-8?q?0eTyVgiKNEwIz29YkvsYyiPBm/IsFCpYJ5tZzfxXvpkOgXmtVEzRbw2iM7yy4e6p0?= =?utf-8?q?YuBQRuC7LEHtIcYlWIbxAd4HVzzX8D85fTODTl1BZk681ay3ODLnfrngLxiaiaBkE?= =?utf-8?q?mqQ8Tk1eAgESgsiyfGeMR/GSpOJUXZgGNU/NO8ml6Oj05Gofzzcxvm4AMbb/sQ4A+?= =?utf-8?q?xNKW6o2zfYl+hTlphfj/AAmCijNNe/MPGl1D1q6aXGOAqNXLT0gwmM2u6lid6M5Tx?= =?utf-8?q?xDe1qIhFD58nTzCv8WB8hS6ca/0xMr+O6SueTiokHDno4GFUsRN+fXg3awrBwekN/?= =?utf-8?q?2NIC/i9pfm7/9rjWla0bVcoAWhh4K4zyRnY0xx0Up7DsCeAM+3G7SVYCW0/p5jUZM?= =?utf-8?q?uuApKiRXYCbR7nubqmSkddVW66uXlYQXzxkrKsXijqFLKf4lwTWh1ljF227ZrJW0l?= =?utf-8?q?7ySODWrfqR8LRrIOkVSBG9bnsQxzS67zsEF8F3Ll6PXhGx47GdE3Hx2aYJ11Rxxy6?= =?utf-8?q?MiYrfHMKfsgTHn33/9H63lYA5+QWgwXRogo/o/oIJRJ2PK7z/9xAlXBWwgPS/Fjbb?= =?utf-8?q?uC2jN/SEWX6sxktLL6dKt1V1cDTyZaWSp4AwjSHvQL7+pO+IvLsNo9TYToCmGorBK?= =?utf-8?q?qCgzdjg5UGxSc+PyD4zspBrFqeV2yGoUJvoFL4aDZ7HBRBvvFyUe9BTc2vlkU57DJ?= =?utf-8?q?xPmkTZP9DuXUBzyIh2QoHnqiw5wrtHwE6oHTEm/OwmbDEmEXCKh1I/zOdOkJIuM1S?= =?utf-8?q?9LMHd1LGhiCShQ7E9cBb13hEAk6UIJJ+Z1Vt0tRP2/Nw7guPKe8rziHnzrivjqrkS?= =?utf-8?q?mktPcqQb8pHDio9ya7ERx5UM/5aK7plT0wJa6nTZJFarIOaj2VCPHcRDBoTHXf+AX?= =?utf-8?q?wU4EDqknx/lPylsS8ztEYt4cfh402Zy6Atmw37YWfeQPW9m3zQF1q4OFIFvg9XXoJ?= =?utf-8?q?C+l6bvJMctRrxDKaR4YLDLd3IoKUfCTtWoUe7Fmb+OUOj4ypn71LYl7H9pfgsQKN6?= =?utf-8?q?z6ZgEip4pvTuI3HxM0HXr84h9/sNCaCgdfogMg1qoS06evIt7e7qQszEdDxcGGOtl?= =?utf-8?q?R49IEwGVhtVyuc7r4fzPreljmeEWETTh6juFqH82lG2yR2SbUp4gY5gxlmKztcB+m?= =?utf-8?q?PgJzuZIA53RsePi2rIDctCNy/SYzqKrJ5IqistE5DfDf6lIUeGWzzvlESNpOp80GC?= =?utf-8?q?BHZH5AZPD0lHCXTb1l6blNwYuMY6Yro1a/wfyndNWgnzMw3P+G3wSo=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:45:56.8296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab108c0c-c2c3-44aa-c625-08dd33aeb291 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026369.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7180 Provide platform support for Nvidia (DPU) Data Processor Unit for the Smart Switch SN4280. The Smart Switch equipped with: - Nvidia COME module based on AMD EPYC™ Embedded 3451 CPU. - Nvidia Spectrum-3 ASIC. - Four DPUs, each equipped with Nvidia BF3 ARM based processor and with Lattice LFD2NX-40 FPGA device. - 28xQSFP-DD external ports. - Two power supplies. - Four cooling drawers. Drivers provides support for the platform management and monitoring of DPU components. It includes support for health events, resets and boot progress indications logic, implemented by FPGA device. Reviewed-by: Ciju Rajan K Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/Kconfig | 12 + drivers/platform/mellanox/Makefile | 1 + drivers/platform/mellanox/mlxreg-dpu.c | 622 +++++++++++++++++++++++++ 3 files changed, 635 insertions(+) create mode 100644 drivers/platform/mellanox/mlxreg-dpu.c diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig index aa760f064a17..7da0fc46b1e7 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig @@ -27,6 +27,18 @@ config MLX_PLATFORM If you have a Mellanox system, say Y or M here. +config MLXREG_DPU + tristate "Nvidia Data Processor Unit platform driver support" + select REGMAP_I2C + help + This driver provides support for the Nvidia BF3 Data Processor Units, + which are the part of SN4280 Ethernet smart switch systems + providing a high performance switching solution for Enterprise Data + Centers (EDC) for building Ethernet based clusters, High-Performance + Computing (HPC) and embedded environments. + + If you have a Nvidia smart swicth system, say Y or M here. + config MLXREG_HOTPLUG tristate "Mellanox platform hotplug driver support" depends on HWMON diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile index ba56485cbe8c..e86723b44c2e 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o +obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o diff --git a/drivers/platform/mellanox/mlxreg-dpu.c b/drivers/platform/mellanox/mlxreg-dpu.c new file mode 100644 index 000000000000..2288595310e3 --- /dev/null +++ b/drivers/platform/mellanox/mlxreg-dpu.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia Data Processor Unit platform driver + * + * Copyright (C) 2025 Nvidia Technologies Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* I2C bus IO offsets */ +#define MLXREG_DPU_REG_FPGA1_VER_OFFSET 0x2400 +#define MLXREG_DPU_REG_FPGA1_PN_OFFSET 0x2404 +#define MLXREG_DPU_REG_FPGA1_PN1_OFFSET 0x2405 +#define MLXREG_DPU_REG_PG_OFFSET 0x2414 +#define MLXREG_DPU_REG_PG_EVENT_OFFSET 0x2415 +#define MLXREG_DPU_REG_PG_MASK_OFFSET 0x2416 +#define MLXREG_DPU_REG_RESET_GP1_OFFSET 0x2417 +#define MLXREG_DPU_REG_RST_CAUSE1_OFFSET 0x241e +#define MLXREG_DPU_REG_GP0_RO_OFFSET 0x242b +#define MLXREG_DPU_REG_GP0_OFFSET 0x242e +#define MLXREG_DPU_REG_GP1_OFFSET 0x242c +#define MLXREG_DPU_REG_GP4_OFFSET 0x2438 +#define MLXREG_DPU_REG_AGGRCO_OFFSET 0x2442 +#define MLXREG_DPU_REG_AGGRCO_MASK_OFFSET 0x2443 +#define MLXREG_DPU_REG_HEALTH_OFFSET 0x244d +#define MLXREG_DPU_REG_HEALTH_EVENT_OFFSET 0x244e +#define MLXREG_DPU_REG_HEALTH_MASK_OFFSET 0x244f +#define MLXREG_DPU_REG_FPGA1_MVER_OFFSET 0x24de +#define MLXREG_DPU_REG_CONFIG3_OFFSET 0x24fd +#define MLXREG_DPU_REG_MAX 0x3fff + +/* Power Good event masks. */ +#define MLXREG_DPU_PG_VDDIO_MASK BIT(0) +#define MLXREG_DPU_PG_VDD_CPU_MASK BIT(1) +#define MLXREG_DPU_PG_VDD_MASK BIT(2) +#define MLXREG_DPU_PG_1V8_MASK BIT(3) +#define MLXREG_DPU_PG_COMPARATOR_MASK BIT(4) +#define MLXREG_DPU_PG_VDDQ_MASK BIT(5) +#define MLXREG_DPU_PG_HVDD_MASK BIT(6) +#define MLXREG_DPU_PG_DVDD_MASK BIT(7) +#define MLXREG_DPU_PG_MASK (MLXREG_DPU_PG_DVDD_MASK | \ + MLXREG_DPU_PG_HVDD_MASK | \ + MLXREG_DPU_PG_VDDQ_MASK | \ + MLXREG_DPU_PG_COMPARATOR_MASK | \ + MLXREG_DPU_PG_1V8_MASK | \ + MLXREG_DPU_PG_VDD_CPU_MASK | \ + MLXREG_DPU_PG_VDD_MASK | \ + MLXREG_DPU_PG_VDDIO_MASK) + +/* Health event masks. */ +#define MLXREG_DPU_HLTH_THERMAL_TRIP_MASK BIT(0) +#define MLXREG_DPU_HLTH_UFM_UPGRADE_DONE_MASK BIT(1) +#define MLXREG_DPU_HLTH_VDDQ_HOT_ALERT_MASK BIT(2) +#define MLXREG_DPU_HLTH_VDD_CPU_HOT_ALERT_MASK BIT(3) +#define MLXREG_DPU_HLTH_VDDQ_ALERT_MASK BIT(4) +#define MLXREG_DPU_HLTH_VDD_CPU_ALERT_MASK BIT(5) +#define MLXREG_DPU_HEALTH_MASK (MLXREG_DPU_HLTH_UFM_UPGRADE_DONE_MASK | \ + MLXREG_DPU_HLTH_VDDQ_HOT_ALERT_MASK | \ + MLXREG_DPU_HLTH_VDD_CPU_HOT_ALERT_MASK | \ + MLXREG_DPU_HLTH_VDDQ_ALERT_MASK | \ + MLXREG_DPU_HLTH_VDD_CPU_ALERT_MASK | \ + MLXREG_DPU_HLTH_THERMAL_TRIP_MASK) + +/* Hotplug aggregation masks. */ +#define MLXREG_DPU_HEALTH_AGGR_MASK BIT(0) +#define MLXREG_DPU_PG_AGGR_MASK BIT(1) +#define MLXREG_DPU_AGGR_MASK (MLXREG_DPU_HEALTH_AGGR_MASK | \ + MLXREG_DPU_PG_AGGR_MASK) + +/* Voltage regulator firmware update status mask. */ +#define MLXREG_DPU_VOLTREG_UPD_MASK GENMASK(5, 4) + +#define MLXREG_DPU_NR_NONE (-1) + +/* + * enum mlxreg_dpu_type - Data Processor Unit types + * + * @MLXREG_DPU_BF3: DPU equipped with BF3 SoC; + */ +enum mlxreg_dpu_type { + MLXREG_DPU_BF3 = 0x0050, +}; + +/* Default register access data. */ +static struct mlxreg_core_data mlxreg_dpu_io_data[] = { + { + .label = "fpga1_version", + .reg = MLXREG_DPU_REG_FPGA1_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "fpga1_pn", + .reg = MLXREG_DPU_REG_FPGA1_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "fpga1_version_min", + .reg = MLXREG_DPU_REG_FPGA1_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "perst_rst", + .reg = MLXREG_DPU_REG_RESET_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { + .label = "usbphy_rst", + .reg = MLXREG_DPU_REG_RESET_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "phy_rst", + .reg = MLXREG_DPU_REG_RESET_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { + .label = "tpm_rst", + .reg = MLXREG_DPU_REG_RESET_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { + .label = "reset_from_main_board", + .reg = MLXREG_DPU_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { + .label = "reset_aux_pwr_or_reload", + .reg = MLXREG_DPU_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { + .label = "reset_comex_pwr_fail", + .reg = MLXREG_DPU_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_dpu_thermal", + .reg = MLXREG_DPU_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { + .label = "reset_pwr_off", + .reg = MLXREG_DPU_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "dpu_id", + .reg = MLXREG_DPU_REG_GP0_RO_OFFSET, + .mask = GENMASK(3, 0), + .mode = 0444, + }, + { + .label = "voltreg_update_status", + .reg = MLXREG_DPU_REG_GP0_RO_OFFSET, + .mask = MLXREG_DPU_VOLTREG_UPD_MASK, + .bit = 5, + .mode = 0444, + }, + { + .label = "boot_progress", + .reg = MLXREG_DPU_REG_GP0_OFFSET, + .mask = GENMASK(3, 0), + .mode = 0444, + }, + { + .label = "ufm_upgrade", + .reg = MLXREG_DPU_REG_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, +}; + +static struct mlxreg_core_platform_data mlxreg_dpu_default_regs_io_data = { + .data = mlxreg_dpu_io_data, + .counter = ARRAY_SIZE(mlxreg_dpu_io_data), +}; + +/* Default hotplug data. */ +static struct mlxreg_core_data mlxreg_dpu_power_events_items_data[] = { + { + .label = "pg_vddio", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_VDDIO_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_vdd_cpu", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_VDD_CPU_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_vdd", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_VDD_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_1v8", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_1V8_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_comparator", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_COMPARATOR_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_vddq", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_VDDQ_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_hvdd", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_HVDD_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "pg_dvdd", + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_DVDD_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, +}; + +static struct mlxreg_core_data mlxreg_dpu_health_events_items_data[] = { + { + .label = "thermal_trip", + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HLTH_THERMAL_TRIP_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "ufm_upgrade_done", + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HLTH_UFM_UPGRADE_DONE_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "vddq_hot_alert", + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HLTH_VDDQ_HOT_ALERT_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "vdd_cpu_hot_alert", + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HLTH_VDD_CPU_HOT_ALERT_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "vddq_alert", + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HLTH_VDDQ_ALERT_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, + { + .label = "vdd_cpu_alert", + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HLTH_VDD_CPU_ALERT_MASK, + .hpdev.nr = MLXREG_DPU_NR_NONE, + }, +}; + +static struct mlxreg_core_item mlxreg_dpu_hotplug_items[] = { + { + .data = mlxreg_dpu_power_events_items_data, + .aggr_mask = MLXREG_DPU_PG_AGGR_MASK, + .reg = MLXREG_DPU_REG_PG_OFFSET, + .mask = MLXREG_DPU_PG_MASK, + .count = ARRAY_SIZE(mlxreg_dpu_power_events_items_data), + .health = false, + .inversed = 1, + }, + { + .data = mlxreg_dpu_health_events_items_data, + .aggr_mask = MLXREG_DPU_HEALTH_AGGR_MASK, + .reg = MLXREG_DPU_REG_HEALTH_OFFSET, + .mask = MLXREG_DPU_HEALTH_MASK, + .count = ARRAY_SIZE(mlxreg_dpu_health_events_items_data), + .health = false, + .inversed = 1, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxreg_dpu_default_hotplug_data = { + .items = mlxreg_dpu_hotplug_items, + .counter = ARRAY_SIZE(mlxreg_dpu_hotplug_items), + .cell = MLXREG_DPU_REG_AGGRCO_OFFSET, + .mask = MLXREG_DPU_AGGR_MASK, +}; + +/* mlxreg_dpu - device private data + * @dev: platform device; + * @data: pltaform core data; + * @io_data: register access platform data; + * @io_regs: register access device; + * @hotplug_data: hotplug platform data; + * @hotplug: hotplug device; + */ +struct mlxreg_dpu { + struct device *dev; + struct mlxreg_core_data *data; + struct mlxreg_core_platform_data *io_data; + struct platform_device *io_regs; + struct mlxreg_core_hotplug_platform_data *hotplug_data; + struct platform_device *hotplug; +}; + +static bool mlxreg_dpu_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXREG_DPU_REG_PG_EVENT_OFFSET: + case MLXREG_DPU_REG_PG_MASK_OFFSET: + case MLXREG_DPU_REG_RESET_GP1_OFFSET: + case MLXREG_DPU_REG_GP0_OFFSET: + case MLXREG_DPU_REG_GP1_OFFSET: + case MLXREG_DPU_REG_GP4_OFFSET: + case MLXREG_DPU_REG_AGGRCO_OFFSET: + case MLXREG_DPU_REG_AGGRCO_MASK_OFFSET: + case MLXREG_DPU_REG_HEALTH_EVENT_OFFSET: + case MLXREG_DPU_REG_HEALTH_MASK_OFFSET: + return true; + } + return false; +} + +static bool mlxreg_dpu_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXREG_DPU_REG_FPGA1_VER_OFFSET: + case MLXREG_DPU_REG_FPGA1_PN_OFFSET: + case MLXREG_DPU_REG_FPGA1_PN1_OFFSET: + case MLXREG_DPU_REG_PG_OFFSET: + case MLXREG_DPU_REG_PG_EVENT_OFFSET: + case MLXREG_DPU_REG_PG_MASK_OFFSET: + case MLXREG_DPU_REG_RESET_GP1_OFFSET: + case MLXREG_DPU_REG_RST_CAUSE1_OFFSET: + case MLXREG_DPU_REG_GP0_RO_OFFSET: + case MLXREG_DPU_REG_GP0_OFFSET: + case MLXREG_DPU_REG_GP1_OFFSET: + case MLXREG_DPU_REG_GP4_OFFSET: + case MLXREG_DPU_REG_AGGRCO_OFFSET: + case MLXREG_DPU_REG_AGGRCO_MASK_OFFSET: + case MLXREG_DPU_REG_HEALTH_OFFSET: + case MLXREG_DPU_REG_HEALTH_EVENT_OFFSET: + case MLXREG_DPU_REG_HEALTH_MASK_OFFSET: + case MLXREG_DPU_REG_FPGA1_MVER_OFFSET: + case MLXREG_DPU_REG_CONFIG3_OFFSET: + return true; + } + return false; +} + +static bool mlxreg_dpu_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXREG_DPU_REG_FPGA1_VER_OFFSET: + case MLXREG_DPU_REG_FPGA1_PN_OFFSET: + case MLXREG_DPU_REG_FPGA1_PN1_OFFSET: + case MLXREG_DPU_REG_PG_OFFSET: + case MLXREG_DPU_REG_PG_EVENT_OFFSET: + case MLXREG_DPU_REG_PG_MASK_OFFSET: + case MLXREG_DPU_REG_RESET_GP1_OFFSET: + case MLXREG_DPU_REG_RST_CAUSE1_OFFSET: + case MLXREG_DPU_REG_GP0_RO_OFFSET: + case MLXREG_DPU_REG_GP0_OFFSET: + case MLXREG_DPU_REG_GP1_OFFSET: + case MLXREG_DPU_REG_GP4_OFFSET: + case MLXREG_DPU_REG_AGGRCO_OFFSET: + case MLXREG_DPU_REG_AGGRCO_MASK_OFFSET: + case MLXREG_DPU_REG_HEALTH_OFFSET: + case MLXREG_DPU_REG_HEALTH_EVENT_OFFSET: + case MLXREG_DPU_REG_HEALTH_MASK_OFFSET: + case MLXREG_DPU_REG_FPGA1_MVER_OFFSET: + case MLXREG_DPU_REG_CONFIG3_OFFSET: + return true; + } + return false; +} + +/* Configuration for the register map of a device with 2 bytes address space. */ +static const struct regmap_config mlxreg_dpu_regmap_conf = { + .reg_bits = 16, + .val_bits = 8, + .max_register = MLXREG_DPU_REG_MAX, + .cache_type = REGCACHE_FLAT, + .writeable_reg = mlxreg_dpu_writeable_reg, + .readable_reg = mlxreg_dpu_readable_reg, + .volatile_reg = mlxreg_dpu_volatile_reg, +}; + +static int mlxreg_dpu_copy_hotplug_data(struct device *dev, struct mlxreg_dpu *mlxreg_dpu, + struct mlxreg_core_hotplug_platform_data *hotplug_data) +{ + struct mlxreg_core_item *item; + int i; + + mlxreg_dpu->hotplug_data = devm_kmemdup(dev, hotplug_data, + sizeof(*mlxreg_dpu->hotplug_data), GFP_KERNEL); + if (!mlxreg_dpu->hotplug_data) + return -ENOMEM; + + mlxreg_dpu->hotplug_data->items = devm_kmemdup(dev, hotplug_data->items, + mlxreg_dpu->hotplug_data->counter * + sizeof(*hotplug_data->items), + GFP_KERNEL); + if (!mlxreg_dpu->hotplug_data->items) + return -ENOMEM; + + item = mlxreg_dpu->hotplug_data->items; + for (i = 0; i < mlxreg_dpu->hotplug_data->counter; i++, item++) { + item = devm_kmemdup(dev, &hotplug_data->items[i], sizeof(*item), GFP_KERNEL); + if (!item) + return -ENOMEM; + item->data = devm_kmemdup(dev, hotplug_data->items[i].data, + hotplug_data->items[i].count * sizeof(item->data), + GFP_KERNEL); + if (!item->data) + return -ENOMEM; + } + + return 0; +} + +static int mlxreg_dpu_config_init(struct mlxreg_dpu *mlxreg_dpu, void *regmap, + struct mlxreg_core_data *data, int irq) +{ + struct device *dev = &data->hpdev.client->dev; + u32 regval; + int err; + + /* Validate DPU type. */ + err = regmap_read(regmap, MLXREG_DPU_REG_CONFIG3_OFFSET, ®val); + if (err) + return err; + switch (regval) { + case MLXREG_DPU_BF3: + /* Copy platform specific hotplug data. */ + err = mlxreg_dpu_copy_hotplug_data(dev, mlxreg_dpu, + &mlxreg_dpu_default_hotplug_data); + if (err) + return err; + + mlxreg_dpu->io_data = &mlxreg_dpu_default_regs_io_data; + + break; + default: + return -ENODEV; + } + + /* Register IO access driver. */ + if (mlxreg_dpu->io_data) { + mlxreg_dpu->io_data->regmap = regmap; + mlxreg_dpu->io_regs = + platform_device_register_resndata(dev, "mlxreg-io", data->slot, NULL, 0, + mlxreg_dpu->io_data, + sizeof(*mlxreg_dpu->io_data)); + if (IS_ERR(mlxreg_dpu->io_regs)) { + dev_err(dev, "Failed to create regio for client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, + data->hpdev.brdinfo->addr); + err = PTR_ERR(mlxreg_dpu->io_regs); + goto fail_register_io; + } + } + + /* Register hotplug driver. */ + if (mlxreg_dpu->hotplug_data && irq) { + mlxreg_dpu->hotplug_data->regmap = regmap; + mlxreg_dpu->hotplug_data->irq = irq; + mlxreg_dpu->hotplug = + platform_device_register_resndata(dev, "mlxreg-hotplug", data->slot, NULL, 0, + mlxreg_dpu->hotplug_data, + sizeof(*mlxreg_dpu->hotplug_data)); + if (IS_ERR(mlxreg_dpu->hotplug)) { + err = PTR_ERR(mlxreg_dpu->hotplug); + goto fail_register_hotplug; + } + } + + return 0; + +fail_register_hotplug: + platform_device_unregister(mlxreg_dpu->io_regs); +fail_register_io: + + return err; +} + +static void mlxreg_dpu_config_exit(struct mlxreg_dpu *mlxreg_dpu) +{ + /* Unregister hotplug driver. */ + platform_device_unregister(mlxreg_dpu->hotplug); + /* Unregister IO access driver. */ + platform_device_unregister(mlxreg_dpu->io_regs); +} + +static int mlxreg_dpu_probe(struct platform_device *pdev) +{ + struct mlxreg_core_data *data; + struct mlxreg_dpu *mlxreg_dpu; + void *regmap; + int err; + + data = dev_get_platdata(&pdev->dev); + if (!data || !data->hpdev.brdinfo) + return -EINVAL; + + mlxreg_dpu = devm_kzalloc(&pdev->dev, sizeof(*mlxreg_dpu), GFP_KERNEL); + if (!mlxreg_dpu) + return -ENOMEM; + + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); + if (!data->hpdev.adapter) + return -EPROBE_DEFER; + + /* Create device at the top of DPU I2C tree.*/ + data->hpdev.client = i2c_new_client_device(data->hpdev.adapter, + data->hpdev.brdinfo); + if (IS_ERR(data->hpdev.client)) { + dev_err(&pdev->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); + err = PTR_ERR(data->hpdev.client); + goto i2c_new_device_fail; + } + + regmap = devm_regmap_init_i2c(data->hpdev.client, + &mlxreg_dpu_regmap_conf); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "Failed to create regmap for client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); + err = PTR_ERR(regmap); + goto devm_regmap_init_i2c_fail; + } + + /* Sync registers with hardware. */ + regcache_mark_dirty(regmap); + err = regcache_sync(regmap); + if (err) { + dev_err(&pdev->dev, "Failed to sync regmap for client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); + err = PTR_ERR(regmap); + goto regcache_sync_fail; + } + + mlxreg_dpu->data = data; + mlxreg_dpu->dev = &pdev->dev; + platform_set_drvdata(pdev, mlxreg_dpu); + + /* Configure DPU. */ + err = mlxreg_dpu_config_init(mlxreg_dpu, regmap, data, data->hpdev.brdinfo->irq); + if (err) + goto mlxreg_dpu_config_init_fail; + + return err; + +mlxreg_dpu_config_init_fail: +regcache_sync_fail: +devm_regmap_init_i2c_fail: + if (data->hpdev.client) { + i2c_unregister_device(data->hpdev.client); + data->hpdev.client = NULL; + } +i2c_new_device_fail: + i2c_put_adapter(data->hpdev.adapter); + data->hpdev.adapter = NULL; + return err; +} + +static void mlxreg_dpu_remove(struct platform_device *pdev) +{ + struct mlxreg_core_data *data = dev_get_platdata(&pdev->dev); + struct mlxreg_dpu *mlxreg_dpu = platform_get_drvdata(pdev); + + mlxreg_dpu_config_exit(mlxreg_dpu); + if (data->hpdev.client) { + i2c_unregister_device(data->hpdev.client); + data->hpdev.client = NULL; + i2c_put_adapter(data->hpdev.adapter); + data->hpdev.adapter = NULL; + } +} + +static struct platform_driver mlxreg_dpu_driver = { + .probe = mlxreg_dpu_probe, + .remove = mlxreg_dpu_remove, + .driver = { + .name = "mlxreg-dpu", + }, +}; + +module_platform_driver(mlxreg_dpu_driver); + +MODULE_AUTHOR("Vadim Pasternak "); +MODULE_DESCRIPTION("Nvidia Data Processor Unit platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_ALIAS("platform:mlxreg-dpu"); From patchwork Mon Jan 13 08:43:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936922 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2055.outbound.protection.outlook.com [40.107.94.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3776714F9F9 for ; Mon, 13 Jan 2025 08:46:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757972; cv=fail; b=N09Aagq2p1KmE+pgPvs1ovGBoBs1o2R5SYg+nsHdV6wRsSKseE0eImc8ZE/DA6AE0Y+dpIiUu+GTaESY0Gjxo3FLnmdj1p3IAx9URITfKyeqNY0kSwTnqg0eXuH4TiNQ6rrKjCGC0LMnQW9GprjC7rPpFCmhNyODm2E67GvW+ds= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757972; c=relaxed/simple; bh=T+M8EUKv2EYSB73wQRRqiIVuyCv67keUNFezHLoa2NA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cAmAPAYmkB4/4fEn6GX69+ozvDvgVL5M7rfhvptHKrb1PftjFgVDGUJI0Oz3fZ2uHwTijSS0R1fb+lghex8eW/+IXhUKL9ASCS2n7bAv7QDnaPtG32a7lqa5NdCcUXaHyG5kvduzLwiYcHgdD9jg1LACmM4pRD3G4si8hA70rVI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=EFdolQZ3; arc=fail smtp.client-ip=40.107.94.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="EFdolQZ3" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Dih3H88UrBlUnyJYQWcjBY3q9TTh3Og9yhMcTFoRgcFqfJi/2quUg9I2NdaTPfNIv2mjqL+1hbHUnxdbldjeCqk6ZXNkaKkWhbKqlYcA+WjeJqMEwwtwdXjVQn9GNpniqbXR9WDAPd2RUCOYwKIdYTP/IB6QBnjsAOivIW3+FhIff7WqHgS+6WoubxvD5MhKIYYKhn87Z8sGfGZmXuQedJNJxKuZd9FrC/HYBrYKeCLVYE0h0egZSWoEsZswqwCX+Tj1DDAvw9OWBpxOR8hKEw/biHsG2emZ3IR1j5N/IPXf/jacMSAmVwR2uJDr+rHBeh/LjsgFlbBXCESGA+qTiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Cyknm6o1PmM7HOc2ScpauDlA/KDvuJfnBWeHc4O2RGE=; b=Dd8u+N7uSgpRwCWEGGce0340kPeuLsd+D1RycEUmwRqiZOidEwvIEYeQc9Iq1LsabfF1Hnh29YYbotx+9383Qp+y+6BzwYL7/b69aUUmD8T0HDcumcTkCs5EGd9MH3sKCg9uoEtkDdqPHTDepv9DJvWp+ugoNIqzozmUCqTSbb6EuJox1nV/fqImrLZMFsAYEc66T1QuwI7KN84HurZHWAMtr9J8AtYMY34eTyKMwQjG9cXA3CIlTu2XeEb37sULzxtpS026z5OrEEbz57o5LNJ3iND+Ya7BWjGt9NAqn0jmrBWJiS8iU7pLwD8fuYp+BvHoq/GFQoW5mPLzkSe+JQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Cyknm6o1PmM7HOc2ScpauDlA/KDvuJfnBWeHc4O2RGE=; b=EFdolQZ3rqOP30V3CMHeb+z3x/AJWGAp/zOGX55iRqSII81x/JOaypTLBw0rGQxqX55WVZx8sKMXHPsJ8UvqF3Yzt37uyhqpqGyAD4tCZvGEf5EofSzktHT7572Eir/mjtp+y7YOTp8pt93e6T1TZ/VEGMSkxKBESQrbXbalcCDy8majrBC/RHYjGwXm4m+DUIjrKkXXGVbMUmmSSKlAimi6/ApDEcw9xHS37TudgdaWZDxPvoMKN6Fe6W61BU82JImIwsg/nkvVj8mK8ADVzI2jd1twaU9bbQiqTg9oFUuZpPTO6YHMxfeEbbolO2WofX2Ov2Fcgj8UhguwWIXmnA== Received: from SN6PR01CA0010.prod.exchangelabs.com (2603:10b6:805:b6::23) by CH3PR12MB7716.namprd12.prod.outlook.com (2603:10b6:610:145::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Mon, 13 Jan 2025 08:46:02 +0000 Received: from SN1PEPF00026367.namprd02.prod.outlook.com (2603:10b6:805:b6:cafe::93) by SN6PR01CA0010.outlook.office365.com (2603:10b6:805:b6::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:45:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF00026367.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:46:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:47 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:43 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 07/10] platform: mellanox: Introduce support of Nvidia smart switch Date: Mon, 13 Jan 2025 10:43:29 +0200 Message-ID: <20250113084337.24763-8-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|CH3PR12MB7716:EE_ X-MS-Office365-Filtering-Correlation-Id: 3393dc2b-d93c-4df1-d7dd-08dd33aeb5a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?XezkrCiOFgTljIGXI/EG1kzqPjT0hVe?= =?utf-8?q?RYZwO8/if6yYw6K5QJUWUCtbLTVM0PAR8dLWTszYL2Qjt70SuUbP+yIbOo6n8roaB?= =?utf-8?q?CfyZz5O7CAx4BfMqJStMU5Um3xEhPTlswuLz+pA5C98I/+KVtGMhyxdRx61D/1kd/?= =?utf-8?q?JHZRGluTvhC/46DMu1km77QUFGmktjQAQvGQPoHrCDIdkyYCSCxS+dv+j8oHkuNf2?= =?utf-8?q?JIIRJBvugOhw2Td7rs7RI64cMoLrZ7QXgaQMf7hFJ3bDUd1kp59HMgr2OQTPjzbtp?= =?utf-8?q?CIosDk48zz3lKhsXo7b8KSW/TFW9RSBxYfMzAVzfSinRSJCe/+QYkswNdNQje9BPu?= =?utf-8?q?ktk99p2rpgS3vsUsN+eEXUc37HubmZ8fDAAoialYd+TkIql4tAr4RarU0kyBRbGZ/?= =?utf-8?q?Ief2oQpGwJH7SkH6WEGakC4PkmQLATmzZtf0zJ/vqXjPMo/3sFJwNGIbf9ljW5HjT?= =?utf-8?q?zlk0Tdie8e2GTMn5Qp1I1Co7IM1tR1720/i7SCfMB1n7GpEAwOqTUrpp6RKMXQ1Nw?= =?utf-8?q?mGDyxLr75YHFvcmlygH42PAwxDS+zKDe6JynPloYzaKjJ85EZLbSgg3pGr/PAffc/?= =?utf-8?q?G0gev6p0+nR87Ki78pP3u2n8kbQs/tcADfAu1huoZp7Pol9iJdFolVItfw9ShPiz/?= =?utf-8?q?2UTCbgrw4M8+ICgJePZ462nDXVb1IHGPMUwvBSnu9mdmUX/KsG+DU+FXTfZjhwPGt?= =?utf-8?q?GwUs2cEdYTXXBdWz/vTZAX7Y/hDrRz6WY58fJ6fEUvsZvVJmp0CSD+sawKG3hjW0X?= =?utf-8?q?VKm7KA3HH+X4FIa/PUwp9mgzl+nGSZD9faNYuVahoPxvOSDy7UlBXwtt87josYHfw?= =?utf-8?q?YwVuDbqzPvNpEJAylmaB9G6UUyMjuoWl40Dpl+IuVZl9eBfhHzJGwFmejtQu85l+z?= =?utf-8?q?A6+f821lguIsdrFNS1TGWvIevts2QvYZPQVjuaV9DJ3j0Gs4DsSWZ6yCaYE3iJrRr?= =?utf-8?q?HlRaxzU6uMyc8AnvtRFVNz4pFY+xzJNTEbFIa08pEiAqUS9tt+yfX1dybt3E3qTWI?= =?utf-8?q?FgV1P4wPBWdnIkSNsKnafPx65nsW46oW3NuqNAk0VyKqva6W/pYXxQE6ziFi5DXIB?= =?utf-8?q?b8QOMGzlDvNYJctZJXwGgmnftl2TNiDJvIPMdn1o0hE7iOWRASs8L2GlJD/+w+v+f?= =?utf-8?q?nwXpSp/B1mG7Bo192TgbCG1v0+U/u/lUExv9HjsAKTv3DqsmIPsNhj96FWyI3mVUo?= =?utf-8?q?eldKEu5WZeNt3BAJMnwVzaH7h2vT3KHSCzvWg+wnd3hRP/jsRdA4m1U571ROYgJQI?= =?utf-8?q?JiRgCr2b9AmYAZoYHXn7Balo4wxJEDoVjgbGSqgv1ITgWfM1hhAqfUIPv2JhxxlnY?= =?utf-8?q?Zj5DVHXQD2QFvliAsO7NHQsx07k53KMazQmMxnIRg91ImDmeBC6JdFXplZJU/3/hn?= =?utf-8?q?LLruOF9syFhmtd2zTJ8MkfsCOQdxUnr6z+3ax2HnIi4rLtpd8Rgy/4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:46:01.9943 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3393dc2b-d93c-4df1-d7dd-08dd33aeb5a5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7716 Provide platform support for Nvidia Smart Switch SN4280. The Smart Switch equipped with: - Nvidia COME module based on AMD EPYC™ Embedded 3451 CPU. - Nvidia Spectrum-3 ASIC. - Four DPUs, each equipped with Nvidia BF3 ARM based processor and with Lattice LFD2NX-40 FPGA device. - 28xQSFP-DD external ports. - Two power supplies. - Four cooling drawers. Introduce configuration structures for the new systems to allow proper activation of the required platform drivers. Reviewed-by: Ciju Rajan K Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/mlx-platform.c | 1965 +++++++++++++++++++--- 1 file changed, 1711 insertions(+), 254 deletions(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c index bd3bb06ff8f2..9d237852d3e0 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -38,6 +38,7 @@ #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b #define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 +#define MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET 0x1b #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e @@ -49,9 +50,11 @@ #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 +#define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0x27 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d +#define MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET 0x2c #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 @@ -71,12 +74,14 @@ #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 +#define MLXPLAT_CPLD_LPC_REG_GP3_OFFSET 0x46 #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c +#define MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET 0x4e #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 @@ -88,15 +93,20 @@ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a +#define MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET 0x5e #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 +#define MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET 0x6a #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a +#define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b +#define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c +#define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 @@ -128,10 +138,15 @@ #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 +#define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0xb4 +#define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0xb5 #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 +#define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0xba +#define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0xbb +#define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0xc1 #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 @@ -182,6 +197,9 @@ #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd +#define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe +#define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff + #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL @@ -210,9 +228,15 @@ #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) +#define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4) +#define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5) #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ MLXPLAT_CPLD_AGGR_MASK_COMEX | \ MLXPLAT_CPLD_AGGR_MASK_LC) +#define MLXPLAT_CPLD_AGGR_MASK_SMART_SW (MLXPLAT_CPLD_AGGR_MASK_COMEX | \ + MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ + MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | \ + MLXPLAT_CPLD_AGGR_MASK_DPU_CORE) #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) @@ -235,15 +259,24 @@ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) +#define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0) +#define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0) #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) +#define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) +#define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) +#define MLXPLAT_CPLD_PSU_CAP_MASK GENMASK(7, 0) +#define MLXPLAT_CPLD_FAN_CAP_MASK GENMASK(7, 0) +#define MLXPLAT_CPLD_ASIC_CAP_MASK GENMASK(7, 0) +#define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1) +#define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) @@ -267,6 +300,9 @@ /* Masks for aggregation for modular systems */ #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) +/* Masks for aggregation for smart switch systems */ +#define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0) + #define MLXPLAT_CPLD_HALT_MASK BIT(3) #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) @@ -297,15 +333,18 @@ #define MLXPLAT_CPLD_NR_NONE -1 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 +#define MLXPLAT_CPLD_PSU_XDR_NR 3 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 #define MLXPLAT_CPLD_NR_ASIC 3 #define MLXPLAT_CPLD_NR_LC_BASE 34 +#define MLXPLAT_CPLD_NR_DPU_BASE 18 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) #define MLXPLAT_CPLD_LC_ADDR 0x32 +#define MLXPLAT_CPLD_DPU_ADDR 0x68 /* Masks and default values for watchdogs */ #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) @@ -320,6 +359,7 @@ #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 +#define MLXPLAT_CPLD_DPU_MAX_DEVS 4 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 @@ -346,6 +386,7 @@ * @pdev_io_regs - register access platform devices * @pdev_fan - FAN platform devices * @pdev_wd - array of watchdog platform devices + * pdev_dpu - array of Data Processor Unit platform devices * @regmap: device register map * @hotplug_resources: system hotplug resources * @hotplug_resources_size: size of system hotplug resources @@ -360,6 +401,7 @@ struct mlxplat_priv { struct platform_device *pdev_io_regs; struct platform_device *pdev_fan; struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; + struct platform_device *pdev_dpu[MLXPLAT_CPLD_DPU_MAX_DEVS]; void *regmap; struct resource *hotplug_resources; unsigned int hotplug_resources_size; @@ -626,6 +668,21 @@ static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { }, }; +static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = { + { + I2C_BOARD_INFO("dps460", 0x5d), + }, + { + I2C_BOARD_INFO("dps460", 0x5c), + }, + { + I2C_BOARD_INFO("dps460", 0x5e), + }, + { + I2C_BOARD_INFO("dps460", 0x5f), + }, +}; + static struct i2c_board_info mlxplat_mlxcpld_fan[] = { { I2C_BOARD_INFO("24c32", 0x50), @@ -2370,205 +2427,665 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, }; -/* Callback performs graceful shutdown after notification about power button event */ -static int -mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, - u8 action) -{ - if (action) { - dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); - kernel_power_off(); - } - - return 0; -} - -static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { - .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, -}; - -/* Platform hotplug for l1 switch systems family data */ -static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { +/* Platform hotplug XDR and smart switch system family data */ +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { { - .label = "power_button", - .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, - .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, + .label = "psu1", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, .hpdev.nr = MLXPLAT_CPLD_NR_NONE, - .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, - .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, }, -}; - -/* Callback activates latch reset flow after notification about intrusion event */ -static int -mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, - u8 action) -{ - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - u32 regval; - int err; - - err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); - if (err) - goto fail_regmap_read; - - if (action) { - dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); - err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, - regval | MLXPLAT_CPLD_LATCH_RST_MASK); - } else { - dev_info(&mlxplat_dev->dev, "System latch is properly closed"); - err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, - regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); - } - - if (err) - goto fail_regmap_write; - - return 0; - -fail_regmap_read: -fail_regmap_write: - dev_err(&mlxplat_dev->dev, "Register access failed"); - return err; -} - -static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { - .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, -}; - -static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { { - .label = "thermal1_pdb", - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, + .label = "psu2", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, { - .label = "thermal2_pdb", - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, + .label = "psu3", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, { - .label = "intrusion", - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_INTRUSION_MASK, + .label = "psu4", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, .hpdev.nr = MLXPLAT_CPLD_NR_NONE, - .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, - .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, }, { - .label = "pwm_pg", - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_PWM_PG_MASK, + .label = "psu5", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(4), + .slot = 5, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, -}; - -static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { - { - .data = mlxplat_mlxcpld_default_ng_fan_items_data, - .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, - .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, - .mask = MLXPLAT_CPLD_FAN_NG_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), - .inversed = 1, - .health = false, - }, - { - .data = mlxplat_mlxcpld_erot_ap_items_data, - .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, - .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, - .mask = MLXPLAT_CPLD_EROT_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), - .inversed = 1, - .health = false, - }, { - .data = mlxplat_mlxcpld_erot_error_items_data, - .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, - .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, - .mask = MLXPLAT_CPLD_EROT_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), - .inversed = 1, - .health = false, + .label = "psu6", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(5), + .slot = 6, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, { - .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, - .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, - .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, - .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), - .inversed = 1, - .health = false, + .label = "psu7", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(6), + .slot = 7, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, { - .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, - .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), - .inversed = 1, - .health = false, - .ind = 8, + .label = "psu8", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = BIT(7), + .slot = 8, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, }; -static -struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { - .items = mlxplat_mlxcpld_l1_switch_events_items, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), - .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, - .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, - .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, -}; - -/* Platform led default data */ -static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { { - .label = "status:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "pwr1", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "status:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + .label = "pwr2", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "psu:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr3", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "psu:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr4", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "fan1:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "pwr5", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(4), + .slot = 5, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, }, { - .label = "fan1:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "pwr6", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(5), + .slot = 6, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, }, { - .label = "fan2:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr7", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(6), + .slot = 7, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, }, { - .label = "fan2:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr8", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(7), + .slot = 8, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { { - .label = "fan3:green", + .label = "fan1", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(0), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan2", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(1), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan3", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(2), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan4", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(3), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan5", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(4), + .slot = 5, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(4), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan6", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(5), + .slot = 6, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(5), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan7", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(6), + .slot = 7, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(6), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "fan8", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = BIT(7), + .slot = 8, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(7), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { + { + .label = "asic1", + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + } +}; + +/* Platform hotplug for smart switch systems families data */ +static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = { + { + .label = "dpu1_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "dpu2_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "dpu3_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "dpu4_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data[] = { + { + .label = "dpu1_shtdn_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "dpu2_shtdn_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "dpu3_shtdn_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "dpu4_shtdn_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +}; + +static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { + { + .data = mlxplat_mlxcpld_xdr_psu_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = MLXPLAT_CPLD_PSU_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_xdr_pwr_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = MLXPLAT_CPLD_PWR_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_xdr_fan_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_xdr_asic1_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), + .inversed = 0, + .health = true, + }, + { + .data = mlxplat_mlxcpld_smart_switch_dpu_ready_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = MLXPLAT_CPLD_DPU_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_ready_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = MLXPLAT_CPLD_DPU_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, + .capability_mask = MLXPLAT_CPLD_DPU_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data), + .inversed = 1, + .health = false, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = { + .items = mlxplat_mlxcpld_smart_switch_items, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX | + MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, +}; + +/* Smart switch data processor units data */ +static struct i2c_board_info mlxplat_mlxcpld_smart_switch_dpu_devs[] = { + { + I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, + { + I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, + { + I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, + { + I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { + { + .label = "dpu1", + .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[0], + .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE, + .slot = 1, + }, + { + .label = "dpu2", + .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[1], + .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 1, + .slot = 2, + }, + { + .label = "dpu3", + .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], + .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 2, + .slot = 3, + }, + { + .label = "dpu4", + .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], + .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 3, + .slot = 4, + }, +}; + +/* Callback performs graceful shutdown after notification about power button event */ +static int +mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, + u8 action) +{ + if (action) { + dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); + kernel_power_off(); + } + + return 0; +} + +static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { + .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, +}; + +/* Platform hotplug for l1 switch systems family data */ +static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { + { + .label = "power_button", + .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, + .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, + }, +}; + +/* Callback activates latch reset flow after notification about intrusion event */ +static int +mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, + u8 action) +{ + struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); + u32 regval; + int err; + + err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); + if (err) + goto fail_regmap_read; + + if (action) { + dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); + err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + regval | MLXPLAT_CPLD_LATCH_RST_MASK); + } else { + dev_info(&mlxplat_dev->dev, "System latch is properly closed"); + err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); + } + + if (err) + goto fail_regmap_write; + + return 0; + +fail_regmap_read: +fail_regmap_write: + dev_err(&mlxplat_dev->dev, "Register access failed"); + return err; +} + +static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { + .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { + { + .label = "thermal1_pdb", + .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, + .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "thermal2_pdb", + .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, + .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { + .label = "intrusion", + .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, + .mask = MLXPLAT_CPLD_INTRUSION_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, + }, + { + .label = "pwm_pg", + .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, + .mask = MLXPLAT_CPLD_PWM_PG_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +}; + +static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { + { + .data = mlxplat_mlxcpld_default_ng_fan_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = MLXPLAT_CPLD_FAN_NG_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_erot_ap_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, + .mask = MLXPLAT_CPLD_EROT_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_erot_error_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, + .mask = MLXPLAT_CPLD_EROT_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, + .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, + .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), + .inversed = 1, + .health = false, + .ind = 8, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { + .items = mlxplat_mlxcpld_l1_switch_events_items, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, +}; + +/* Platform led default data */ +static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "status:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "psu:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "psu:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan1:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan2:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan3:green", .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, }, @@ -3088,67 +3605,241 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { .bit = BIT(1), }, { - .label = "fan2:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .label = "fan2:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(1), + }, + { + .label = "fan3:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(2), + }, + { + .label = "fan3:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(2), + }, + { + .label = "fan4:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(3), + }, + { + .label = "fan4:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(3), + }, + { + .label = "fan5:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(4), + }, + { + .label = "fan5:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(4), + }, + { + .label = "fan6:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(5), + }, + { + .label = "fan6:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(5), + }, + { + .label = "uid:blue", + .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { + .data = mlxplat_mlxcpld_l1_switch_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), +}; + +/* Platform led data for XDR and smart switch systems */ +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "status:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "psu:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "psu:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 1, + }, + { + .label = "fan1:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 1, + }, + { + .label = "fan2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 2, + }, + { + .label = "fan2:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 2, + }, + { + .label = "fan3:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 3, + }, + { + .label = "fan3:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 3, + }, + { + .label = "fan4:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 4, + }, + { + .label = "fan4:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 4, + }, + { + .label = "fan5:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 5, + }, + { + .label = "fan5:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 5, + }, + { + .label = "fan6:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 6, + }, + { + .label = "fan6:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 6, + }, + { + .label = "fan7:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .slot = 7, + }, + { + .label = "fan7:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(1), + .slot = 7, }, { - .label = "fan3:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .label = "fan8:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(2), + .slot = 8, }, { - .label = "fan3:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .label = "fan8:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(2), + .slot = 8, }, { - .label = "fan4:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .label = "fan9:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(3), + .slot = 9, }, { - .label = "fan4:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .label = "fan9:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(3), + .slot = 9, }, { - .label = "fan5:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .label = "fan10:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(4), + .slot = 10, }, { - .label = "fan5:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .label = "fan10:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(4), - }, - { - .label = "fan6:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(5), - }, - { - .label = "fan6:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(5), + .slot = 10, }, { .label = "uid:blue", @@ -3157,9 +3848,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { }, }; -static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { - .data = mlxplat_mlxcpld_l1_switch_led_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), +static struct mlxreg_core_platform_data mlxplat_xdr_led_data = { + .data = mlxplat_mlxcpld_xdr_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_led_data), }; /* Platform register access default */ @@ -4396,19 +5087,240 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { }, }; -static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { - .data = mlxplat_mlxcpld_modular_regs_io_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), +static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { + .data = mlxplat_mlxcpld_modular_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), +}; + +/* Platform register access for chassis blade systems family data */ +static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + { + .label = "cpld1_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld1_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "cpld1_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "reset_aux_pwr_or_ref", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { + .label = "reset_from_comex", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "reset_comex_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_platform", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "reset_soc", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "reset_comex_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { + .label = "reset_voltmon_upgrade_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { + .label = "reset_system", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { + .label = "reset_sw_pwr_off", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { + .label = "reset_comex_thermal", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_reload_bios", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "reset_ac_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { + .label = "reset_long_pwr_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "pwr_cycle", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, + }, + { + .label = "pwr_down", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, + }, + { + .label = "global_wp_request", + .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { + .label = "jtag_enable", + .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "comm_chnl_ready", + .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0200, + }, + { + .label = "bios_safe_mode", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "bios_active_image", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "bios_auth_fail", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { + .label = "bios_upgrade_fail", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "voltreg_update_status", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, + .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, + .bit = 5, + .mode = 0444, + }, + { + .label = "vpd_wp", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { + .label = "pcie_asic_reset_dis", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "global_wp_response", + .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { + .label = "config1", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "config2", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "config3", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "ufm_version", + .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { + .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), }; -/* Platform register access for chassis blade systems family data */ -static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { +/* Platform register access for smart switch systems families data */ +static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_regs_io_data[] = { { .label = "cpld1_version", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, .bit = GENMASK(7, 0), .mode = 0444, }, + { + .label = "cpld2_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld3_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, { .label = "cpld1_pn", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, @@ -4416,12 +5328,116 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { .mode = 0444, .regnum = 2, }, + { + .label = "cpld2_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "cpld3_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, { .label = "cpld1_version_min", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, .bit = GENMASK(7, 0), .mode = 0444, }, + { + .label = "cpld2_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld3_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "kexec_activated", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "asic_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { + .label = "eth_switch_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "dpu1_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0200, + }, + { + .label = "dpu2_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, + }, + { + .label = "dpu3_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, + }, + { + .label = "dpu4_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, + }, + { + .label = "dpu1_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0200, + }, + { + .label = "dpu2_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, + }, + { + .label = "dpu3_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, + }, + { + .label = "dpu4_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, + }, + { + .label = "reset_long_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { + .label = "reset_short_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, { .label = "reset_aux_pwr_or_ref", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, @@ -4429,9 +5445,33 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_from_comex", + .label = "reset_swb_dc_dc_pwr_fail", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_swb_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { + .label = "reset_asic_thermal", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "reset_sw_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { + .label = "reset_aux_pwr_or_reload", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), .mode = 0444, }, { @@ -4453,13 +5493,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_comex_wd", + .label = "reset_pwr", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), + .mask = GENMASK(7, 0) & ~BIT(7), .mode = 0444, }, { - .label = "reset_voltmon_upgrade_fail", + .label = "reset_pwr_converter_fail", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, .mask = GENMASK(7, 0) & ~BIT(0), .mode = 0444, @@ -4483,23 +5523,103 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_reload_bios", + .label = "reset_ac_pwr_fail", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(5), + .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, { - .label = "reset_ac_pwr_fail", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), + .label = "voltreg_update_status", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, + .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, + .bit = 5, .mode = 0444, }, { - .label = "reset_long_pwr_pb", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(7), + .label = "port80", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "bios_status", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = MLXPLAT_CPLD_BIOS_STATUS_MASK, + .bit = 2, + .mode = 0444, + }, + { + .label = "bios_start_retry", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "bios_active_image", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "vpd_wp", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { + .label = "pcie_asic_reset_dis", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "shutdown_unlock", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { + .label = "fan_dir", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, + .bit = GENMASK(7, 0), .mode = 0444, }, + { + .label = "dpu1_rst_en", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0200, + }, + { + .label = "dpu2_rst_en", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, + }, + { + .label = "dpu3_rst_en", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, + }, + { + .label = "dpu4_rst_en", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, + }, + { + .label = "psu1_on", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0200, + }, + { + .label = "psu2_on", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, + }, { .label = "pwr_cycle", .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, @@ -4513,72 +5633,117 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { .mode = 0200, }, { - .label = "global_wp_request", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(0), + .label = "jtag_cap", + .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, + .mask = MLXPLAT_CPLD_FU_CAP_MASK, + .bit = 1, + .mode = 0444, + }, + { + .label = "jtag_enable", + .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, + .mask = GENMASK(1, 0), + .bit = 1, + .mode = 0644, + }, + { + .label = "non_active_bios_select", + .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "bios_upgrade_fail", + .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "bios_image_invert", + .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0644, }, { - .label = "jtag_enable", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), + .label = "me_reboot", + .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), .mode = 0644, }, { - .label = "comm_chnl_ready", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), + .label = "dpu1_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), .mode = 0200, }, { - .label = "bios_safe_mode", - .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), - .mode = 0444, + .label = "dpu2_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, }, { - .label = "bios_active_image", - .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(5), - .mode = 0444, + .label = "dpu3_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, }, { - .label = "bios_auth_fail", - .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0444, + .label = "dpu4_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, }, { - .label = "bios_upgrade_fail", - .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(7), + .label = "ufm_done", + .reg = MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET, + .bit = GENMASK(7, 0), .mode = 0444, }, { - .label = "voltreg_update_status", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, - .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, - .bit = 5, + .label = "asic_health", + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .bit = 1, .mode = 0444, }, { - .label = "vpd_wp", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(3), + .label = "psu1_ac_ok", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), .mode = 0644, }, { - .label = "pcie_asic_reset_dis", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), + .label = "psu2_ac_ok", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), .mode = 0644, }, { - .label = "global_wp_response", - .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, + .label = "psu1_no_alert", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { + .label = "psu2_no_alert", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "asic_pg_fail", + .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), .mode = 0444, }, + { + .label = "spi_chnl_select", + .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, + .mask = GENMASK(7, 0), + .bit = 1, + .mode = 0644, + }, { .label = "config1", .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, @@ -4605,9 +5770,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { }, }; -static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { - .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), +static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { + .data = mlxplat_mlxcpld_smart_switch_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data), }; /* Platform FAN default */ @@ -4751,6 +5916,185 @@ static struct mlxreg_core_platform_data mlxplat_default_fan_data = { .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, }; +/* XDR and smart switch platform fan data */ +static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { + { + .label = "pwm1", + .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, + }, + { + .label = "tacho1", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 1, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho2", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 2, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho3", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 3, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho4", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 4, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho5", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 5, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho6", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 6, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho7", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 7, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho8", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 8, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho9", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 9, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho10", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 10, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho11", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 11, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho12", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 12, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho13", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 13, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho14", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 14, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho15", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 15, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho16", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 16, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + }, + { + .label = "tacho17", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 17, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, + }, + { + .label = "tacho18", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 18, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, + }, + { + .label = "tacho19", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 19, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, + }, + { + .label = "tacho20", + .reg = MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET, + .mask = GENMASK(7, 0), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, + .slot = 20, + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, + }, + { + .label = "conf", + .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { + .data = mlxplat_mlxcpld_xdr_fan_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_data), + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .version = 1, +}; + /* Watchdog type1: hardware implementation version1 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). */ @@ -4975,6 +6319,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) { switch (reg) { case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: @@ -4983,12 +6329,14 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: @@ -5012,10 +6360,14 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: @@ -5083,6 +6435,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: @@ -5094,15 +6448,18 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: @@ -5122,6 +6479,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: @@ -5134,12 +6492,17 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: @@ -5213,6 +6576,13 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: @@ -5248,6 +6618,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: @@ -5259,13 +6631,16 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: @@ -5285,6 +6660,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: @@ -5297,9 +6673,11 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: @@ -5370,6 +6748,13 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: @@ -5431,6 +6816,15 @@ static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, }; +static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { + { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, + MLXPLAT_CPLD_LPC_SM_SW_MASK }, +}; + struct mlxplat_mlxcpld_regmap_context { void __iomem *base; }; @@ -5539,6 +6933,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { .reg_write = mlxplat_mlxcpld_reg_write, }; +static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 255, + .cache_type = REGCACHE_FLAT, + .writeable_reg = mlxplat_mlxcpld_writeable_reg, + .readable_reg = mlxplat_mlxcpld_readable_reg, + .volatile_reg = mlxplat_mlxcpld_volatile_reg, + .reg_defaults = mlxplat_mlxcpld_regmap_smart_switch, + .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_smart_switch), + .reg_read = mlxplat_mlxcpld_reg_read, + .reg_write = mlxplat_mlxcpld_reg_write, +}; + static struct resource mlxplat_mlxcpld_resources[] = { [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), }; @@ -5550,6 +6958,7 @@ static struct mlxreg_core_platform_data *mlxplat_regs_io; static struct mlxreg_core_platform_data *mlxplat_fan; static struct mlxreg_core_platform_data *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; +static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; static const struct regmap_config *mlxplat_regmap_config; static struct pci_dev *lpc_bridge; static struct pci_dev *i2c_bridge; @@ -5921,6 +7330,29 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) return mlxplat_register_platform_device(); } +static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi) +{ + int i; + + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; + mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); + mlxplat_mux_data = mlxplat_ng800_mux_data; + mlxplat_hotplug = &mlxplat_mlxcpld_smart_switch_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; + mlxplat_led = &mlxplat_xdr_led_data; + mlxplat_regs_io = &mlxplat_smart_switch_regs_io_data; + mlxplat_fan = &mlxplat_xdr_fan_data; + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_data); i++) + mlxplat_dpu_data[i] = &mlxplat_mlxcpld_smart_switch_dpu_data[i]; + mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_smart_switch; + + return mlxplat_register_platform_device(); +} + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { { .callback = mlxplat_dmi_default_wc_matched, @@ -6015,6 +7447,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), }, }, + { + .callback = mlxplat_dmi_smart_switch_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), + }, + }, { .callback = mlxplat_dmi_msn274x_matched, .matches = { @@ -6390,8 +7828,25 @@ static int mlxplat_platdevs_init(struct mlxplat_priv *priv) } } + /* Add DPU drivers. */ + for (i = 0; i < MLXPLAT_CPLD_DPU_MAX_DEVS; i++) { + if (mlxplat_dpu_data[i]) { + priv->pdev_dpu[i] = + platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", + i, NULL, 0, mlxplat_dpu_data[i], + sizeof(*mlxplat_dpu_data[i])); + if (IS_ERR(priv->pdev_dpu[i])) { + err = PTR_ERR(priv->pdev_dpu[i]); + goto fail_platform_dpu_register; + } + } + } + return 0; +fail_platform_dpu_register: + while (--i >= 0) + platform_device_unregister(priv->pdev_dpu[i]); fail_platform_wd_register: while (--i >= 0) platform_device_unregister(priv->pdev_wd[i]); @@ -6412,6 +7867,8 @@ static void mlxplat_platdevs_exit(struct mlxplat_priv *priv) { int i; + for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0 ; i--) + platform_device_unregister(priv->pdev_dpu[i]); for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) platform_device_unregister(priv->pdev_wd[i]); if (priv->pdev_fan) From patchwork Mon Jan 13 08:43:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936923 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2047.outbound.protection.outlook.com [40.107.220.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9858C23315F for ; Mon, 13 Jan 2025 08:46:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757974; cv=fail; b=jR6BZ3srsVLymYwMF4/ivE8wY/GcP1ihlHn+b1/8gL4ZGlNKaNppVhHQaLIpyST3p9UKyeiclySQje8FLWdoUNNV7rTTl82M7rWpDZfSs+VzkqlgqI9hrywv8bZ6X945ap3acG1Ar5fE0u0tUVWArHR2d/v9G6SaWl7/UnnPrnE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757974; c=relaxed/simple; bh=FlhE7wUbVwI4zwwrI+uVoKL2S1ZwhcZ453BWVWUJ6PQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uiYOPP8jSmECNCHuX6e6EkrDn3zBhIE8neloROhCl0C4krCz+eEoHuPVppgadVL0V3YNKdCffjGldFrYCngQGCZHtqH7ZPbC1QoYLh02BEdJEz2zEMQC0ETvZwmshU4+J0vsBTLqxKdUkFON6CyOgOs63sgEqBln5Gy96zFq51o= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=El9ee7y2; arc=fail smtp.client-ip=40.107.220.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="El9ee7y2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=K10zsg3ROGlgOd/MneFRbiSTgHoLWqPqXYw1dNWKVqlScS1/W5cXMQInfF6+sGWcZ4G3eoHqTx0KcHJYjD6gcm157I+mZkjjTktOF0XtwOC/x9fILVaUD+Puy0VCSCReXi3ncww1ts8y3hyKx2D9saSHCV2j8oBSgyTsWC4yus8f1HBoqMf1OAcxU3D8IKeKG2cAwBZCLURRmQPCUJIaJtfJRlKPINBI5aVW15MygGLtgFUvAa5MHoxIuTs7262UD8taWr5dCcwt/pUXVyBH9Mm1CXe9lY7zAPuVcpMmNvf/UZe000y6rqDaR1zVj9u5WGEMDKPXPg4XY1aSpNZKxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=K0PFaQVu6fHILm1Ro2he1a9Jgvf86qDUDK0kUWe4LAI=; b=nv1JYsS45M/mq0EvcCZ2idVbxFwXTzkBTKbIsAhoomeYutJN3gRJPJxHXQSrHSvhW1MI1U9lYL2OKEwATtPr/sdgoB+/YSHh2unY1PmdmGsGMY61X17yoqcJ3jYIXG5LETYXIkck5Oljc084ea+uwQKptjbt+0sprDroFAUQjFFEbS+GRuD1wQRNCexW6ULWfoHq+B2L1VplkjYNPPNoKDVKUN0buzWjRIMfFY2Xzr+Tax5pprOK1aGttT7pZNqQ3XepVjRBXBatxE5ygZM7gQjWQucuJN4LuoWpzg4hE6Ctck+GOhHVLOCMyPcLvS+uQGd0Vxd0pjljbyS4uJEuCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=K0PFaQVu6fHILm1Ro2he1a9Jgvf86qDUDK0kUWe4LAI=; b=El9ee7y2k05gvvXhgq5kWOR1+pfeZwv9ycksUmnFqsx8IKoj3X54tj/A8iRTUbGIymge5blZbtJ/7ksf4P20zfAPpOfLUyK3Akt/OT+m0gQqJ3Z4uF6+XD/9lnLEmrCpeu+hHlimiyjmXXLjPLm+RHwyTyRlQijgs68ByLYcqeTFHwPDJGuo4W8OSay492b+fCs+1/E8q4EzCkT56e1c2C5NFKD6ji8rLlYZUr0vdMZtnMgmjmaGmrN9SCvWMywG72plOv1Om7H792PqnQmAVExVu7XoPNEMUmOP3zq7Y1nZYXSOQXTPm3qB2WtdhK9WH2Df3RhLttCayM3oeDxQ7A== Received: from CH0P223CA0019.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:116::7) by LV3PR12MB9411.namprd12.prod.outlook.com (2603:10b6:408:215::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Mon, 13 Jan 2025 08:46:09 +0000 Received: from CH2PEPF0000009A.namprd02.prod.outlook.com (2603:10b6:610:116:cafe::91) by CH0P223CA0019.outlook.office365.com (2603:10b6:610:116::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:46:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:46:08 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:50 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:47 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 08/10] platform: mellanox: mlx-platform: Add support for new Nvidia system Date: Mon, 13 Jan 2025 10:43:30 +0200 Message-ID: <20250113084337.24763-9-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|LV3PR12MB9411:EE_ X-MS-Office365-Filtering-Correlation-Id: 70cc4dbd-7cdf-4a70-6de9-08dd33aeb99c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: pB2RxaYWYNN25E1Y5dYPMtw19YdddeD5WjSJWZxStL1Guc4tKJ6Kxe8oPs/RTrRgJ+kEf5g53gl7WZY0OZyc8KaudmXppo/06k/tcV0RgZJlDtMfCycYrqNT4u485SjTwFg3p+HC/62DwAe3oUl4oCpyQNC3vPFRMTTBRVQ2nQfUiSvYbBUX1bBkcD6KPNTWxiebpS/vP2FuF92ZQnNUDp46Bd3zf56ks8Quhe1EowHSxTx/amoZr8iYfJxpXS88pbXCBGVMDg7+s5N57GxoLSwHRXq0iY7Cr+m2vDrrTTKQlocj76ScMyW9Gx3ypo9tRl0A7TMB23Vu0JORMsYa/bvQT2JW2NRTxIBCSU3cUklruFc15agGCW3hdHElkcLcE6W7S9cF2YbUtNSb4SDkvAFVUvkAD7l+RhoyKD5Ky/liSf6gVCsuNnFXIV14WOZfftKpG01diOpW9VHae8FYuiMbCRkQt08uEMTdXdfvTCPQtIi0kv3xLeqqJV+wZTysInUTpon7uFpBuV35jMuAwPVpM65bOIUv87uNix4RYFzJBDedvwGWp5/dWOZfAXwS/w2pzusY9X7caUu+6h5ivj9HO4Ns2gVPfcxrIGL3afMLw/qW/OOGyeiM4VApJBJD0FT2gUX7/gLHf1anuVEP6InlCAokezZwbSUAgmspLnd1Keg3DnFVQSwJ0ZwBbtDa0vsyy+lqU3/zy/oeGv1zptcQXoZlDW6adteMn6eZf1hUuYIQ/LpKAbVsqf+l0EiurBOFSBo7fzcwkGDA+ipwy1EakFkUmhaSBE27g4lM2sv3ikuvIh22vOO2SIhuuPNF4N641i/ZiFZh6QHdLcwgwxyLS4gpTEahVb+CXBaR8aqcniMCehDB9dtm2xdidlKKzjuJtvxihYApfSdx3Zm89mGnV9HPNG03gVIaJozutYlnej7tiTrOg26r6akpJSW/yJtj84Apoqyum9hLwGahr/WJigMRhgmPHYerjGj2FwDYoWHRuUr8zWXQ9rOQ15gcXVMl9QsJ9xa8WLiQgxEJrQ+z3i0ONt6pHCljVZx3jLeLUvlqmOZGDmjzMTovknpWqxe69upCOyPUl2srUq+u+La2f+OHqPBcrzYYfJ4N6b3lL+BrJ9V5zcIrRKZGXu0+fUumDwFeEnNZqZdXcCtkI7wmVDcRbHhdFMmZJF5GhUFtG2BxPC8/a4yLOwjWN7SaWiJJDIm8+WDa8TnrEihnJDGWxO+M1wesaHJhLKMNrlU7AobKXxAOWY34PTASRdX3pH3aUB5rPc5Fkd+MnJoWmHtdx0C48j31CHw7osIiehfaMV/SSktjlcMBfgvyTbsTWLDQ9mDcSrdXxCwoc0KFBBajCbv68Gkmh+/u3R9XmyqznbifRZc3ivVvjr6vhFzzOuryRVXyCO7yc4g6H7cCc7Tlcyy9ybTPJejS7tjtq+iuO3oi5EEXXC/TK6SYD0BEG77tWZXE37fMBtODDGfhtWe0WPyYuJ4b4jjEM6+DtTo= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:46:08.6122 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70cc4dbd-7cdf-4a70-6de9-08dd33aeb99c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9411 Add support for SN5640 Nvidia switch. SN5640 is a 51.2Tbps switch based on Nvidia SPC-5 ASIC. It provides up-to 400Gbps full bidirectional bandwidth per port. The system supports 64 OSFP cages and fits into standard 2U racks. SN5640 Features: - 64 OSFP ports supporting 2.5Gbps - 400Gbps speeds. - Air-cooled with 4 + 1 redundant fan units. - 2 + 2 redundant 2000W PSUs. - System management board based on AMD CPU with secure-boot support. Reviewed-by: Oleksandr Shamray Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/mlx-platform.c | 95 ++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c index 9d237852d3e0..5ede7eb5977d 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -3042,6 +3042,60 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, }; +/* Platform hotplug for next-generation 800G systems family data */ +static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { + { + .data = mlxplat_mlxcpld_ext_psu_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = MLXPLAT_CPLD_PSU_EXT_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_pwr_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = MLXPLAT_CPLD_PWR_EXT_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_xdr_fan_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_default_asic_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), + .inversed = 0, + .health = true, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = { + .items = mlxplat_mlxcpld_ng800_hi171_items, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, +}; + /* Platform led default data */ static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { { @@ -4528,6 +4582,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0644, }, + { + .label = "shutdown_unlock", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, { .label = "erot1_ap_reset", .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, @@ -7353,6 +7413,27 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d return mlxplat_register_platform_device(); } +static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) +{ + int i; + + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; + mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); + mlxplat_mux_data = mlxplat_ng800_mux_data; + mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; + mlxplat_led = &mlxplat_default_ng_led_data; + mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; + mlxplat_fan = &mlxplat_xdr_fan_data; + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i]; + mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; + + return mlxplat_register_platform_device(); +} + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { { .callback = mlxplat_dmi_default_wc_matched, @@ -7453,6 +7534,20 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), }, }, + { + .callback = mlxplat_dmi_ng400_hi171_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), + DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI171"), + }, + }, + { + .callback = mlxplat_dmi_ng400_hi171_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), + DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"), + }, + }, { .callback = mlxplat_dmi_msn274x_matched, .matches = { From patchwork Mon Jan 13 08:43:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936924 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2056.outbound.protection.outlook.com [40.107.93.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 165F6249F9 for ; Mon, 13 Jan 2025 08:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757975; cv=fail; b=HV6v5oX/ESTpC8sdM+H3CntqLBjIRqtkvfFLVeuqZo28zB/72WX/vSMpuTe9vBbfG8vItRC56vXziMDDNPC8cjQh4gB4HglTWJvopoERXmR6p582UH8Qvnw2PLhBrt8djjobkc3TK1s1WKWWAEmydTf7Zvq0abggSLhbKPuDHdY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736757975; c=relaxed/simple; bh=mn74NDgOxcRIn3REBF9+4Pa/tnknw/2pfA5WnaAXbv4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HpZT75h/utvxwLeKLsUX+PcY26OwE1tJinLODXYhOFSDXh1WAk+JUBeJeeirPdZAAIB2UqPmQ7Px/1MmFrwFe0ibvG8REHBAEFLCBTSuZiAs6CDbAx2+QFH3Y7WelMbo24lRSWAnHNIRqIj193oExMhZAgrWkSEhB5WwESaaeyY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=okYUHGI8; arc=fail smtp.client-ip=40.107.93.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="okYUHGI8" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=T8Nwp87/rr9jY8D2cO2MvgN/hjjpRLhq+RJDon5858bWHVia53HntKtbeDc9eRmXg1xolOdkpOM3fw/gi+jqKY1fooQKXXtbttyoxAVSkGqJojzb1wu6vJ/ljiW1PFfgJ96MZVpTQe0hxg1fTR0zW/fEAPqfXKT96Za6+6Oe6I2zJ/MNmuGhmwkmHrfQTsoGrSKAYuHUdBPyEig5lSXJgkAdG4bSZsSu4WdjOZPYgO+1Wo+jlS1nXQ+yR0UzJoEhuKi/tXNMjiOo6B/vZhbIzoQ+wUVCkZ5Sc2nPEDZk8/2kJ6YtTf2zU4QHG8WQdhitMrq1dKh0Sm+/8H45vfXJ2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TNaAnfqdepDO4LNWDVFetwUAZMfYmfqBejEWo27SGrc=; b=kw5Q/WKmoeSJuDxxETzA5pAIFa/Zg61UjS9mbaTPFxhYRGRipOxMGZUX2hUqKGkda5T5fXeXw7tUW3Sum8M7y/SSolkLrfmH3q5MGuYGbTx5pOBBZXRtwg4V1C0FpcIh8568Qi7YUQvxbl++fiVwMmp/OOPXWyPlnP5ixr2qt92jHa3jlTBbOThb+GGq8kwUiqL80fxixQMHJkLTAXtIs/mG6A63Y4GNn1Wg2CguGjKdRHk5wnQD5LFtTa0Edpx1/eWvVR5jn4jKtIf00lnUy9ICQjwLXBQvChJAAajTfilTa5NJX4xKUwcv2+NSd8nVKyi3Nb5JLXuo9FplF4P29g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TNaAnfqdepDO4LNWDVFetwUAZMfYmfqBejEWo27SGrc=; b=okYUHGI8+8SWTbktZ+Uqhk0y2SD0AkeUR60+p+HDS1fbxZJQEin70ulQQ2XRi1c6K9xOMxA+kvkGPDBnegkIf3Z9MZLw/lYGjTQtIsrT82diPh+neLXaVOwlhru5Cff6He0KcYaO5nKrg5wL4aHg99mU2HhzTu6bVCssZweHL8JPgguRrGB+f0hGM441VpThWgbekh7xLhrITVRUczflWMtufDtEE1R2A5a0N0aqgkqcCKMw6P9Jql8ObxwsViiRHaSAxwr0+RH88jl5H+sc1rnsJAQw5BPu85WS1G0OCNfpLYaz7tmUFzqaaMduTr8FJyqPpGWdSQvOympnOi9fUg== Received: from SN6PR05CA0030.namprd05.prod.outlook.com (2603:10b6:805:de::43) by IA1PR12MB7496.namprd12.prod.outlook.com (2603:10b6:208:418::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Mon, 13 Jan 2025 08:46:10 +0000 Received: from SN1PEPF0002636C.namprd02.prod.outlook.com (2603:10b6:805:de:cafe::9d) by SN6PR05CA0030.outlook.office365.com (2603:10b6:805:de::43) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8356.10 via Frontend Transport; Mon, 13 Jan 2025 08:46:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF0002636C.mail.protection.outlook.com (10.167.241.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:46:09 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:54 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:45:51 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 09/10] platform: mellanox: nvsw-sn2200: Add support for new system flavour Date: Mon, 13 Jan 2025 10:43:31 +0200 Message-ID: <20250113084337.24763-10-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|IA1PR12MB7496:EE_ X-MS-Office365-Filtering-Correlation-Id: ad0e01fc-ef88-4595-d8b4-08dd33aeba5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: wKy3GHIth1uODKWm+Wim/ivLq9GW9dIj0j7wsjX4f0rA5V8zxvyK0DBiQv8kpZVDacFozI5+t9CLBPxUnwa0fApB6bCFSCKF0ZOzL4taMe2+NpaOy6pFLOrJHPNToZReds9vb20m0u4wojTKhpQ2qyXqfxuZoJtWXjhJ7J3pxJqM1NUdLF2aN0v1e8hRzpFpcS2E2DYMHfrgIGzGLE3oSr1TozeNgzmIpDvyFMkfrK3zuzGERFXwFxH4izETgPyso91lI4l6dDyWo/nIg8hmCrUaFAGFyxpQFQJOhlIBivRWEdevFjIMyv783+RY1Ejl/0xW3pWRXAeXDqna0oDxLt57Vk9cS2fhZ7R/yq/LJd/jZZXkcwDrjhkcBdt6ivEk3WnClzHqrfUNdQ+5JScVmc42smumUaCn/r7kA0gmusDYM89hW33TzhqdbDZq2OTlipKAzxIcCkMenfGNLgL/1tk0Z7DKIgTv8QtanKhNd9CxZ1YuinxlqDdDQYrw9ti5SXhgI5+ICJfqhwG8y2VvQWH/kf5+IaZywH4z43c+5FGaIMMh/SeUDIX//GTd1+SgABzgnWfwe2+wR1rbZEu2xdtu7550+0LUUqSGuEh7deG61H+1V+T89Gcbms8pJkXq/sC89ZxlfyfSiXACNrrp5kowpMRrWzrH9rfP4Lxn1ocibE5JJkIqAhHP1uorDUlogUCtk+uAF60GywDfNoJH0uD7V9bjKNgAzh5ymBKciHTWrWZYM/owlF8eN/i6LMIDaYXG4Kd5JGpG1qcWmrU3TRM8iQzdbrya021nZ0nQN8xv8mqcc2irCIJ7vyqAZvaXRxkAavVidyDG6o5+LxAd+TbhjTHvjf47d2Ap0de4cKL739Zms0WoybtTYxbwkRRvAkzsPiBOq9AUqU7di24pggxSY9DtNlrm9upBOC+IEIdOjVBIwO7ZENsmJyXHKdvQB54nO1Svqw1dEgwHPP1KpV7A69mckzQQSJElqk8fveaR/sUqoNYrguliSbhN+njh1/8BaMP568i9BzvQLJSobTIapHGJgXyVG9PorXvTCGN30B8a1xVdXroaCsF5BuJiEb/EWQrTICFuex67fFwVYzv3QRyxtB2UfIBeXAcc/8ul/SRDqpY7XJSNMhCCc3LTR1P3XeUMmdTJPUuhG0wxDbPXdbIcL6jRHxPd6H5vovDBRMucAtG6aSK5X6Mg/DYnJXBKG4WWU7WYDrPhmvCFi9ushBXnacZcp6VuJREuhC58+8mOW5/pn61bgDHgF+xDh0AJ25yALkDpvykr2lEpuM0zufgGGfshTRSuqXw4BzOhMle+vduvcp0ZhTmA0G4ZT2NEYQjybvSUoYmt6NRTULtx+TtEAOWLVBXXVj440DdpKwSTsUqBvB9UVgDpUuqVVwYPNbK0C6+SVBYohpq7JMO5EGO/Bz9pdUm5844K6sddEY9iTp9Y7PGws36u41Ov7ww58hlwL5psrA0GEMFJTBRdZUvtum//B2HX2X/+e7s= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:46:09.9045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad0e01fc-ef88-4595-d8b4-08dd33aeba5c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7496 Add support for SN2201 system flavour, which is fitting OCP rack form-factor and feeded from external power source through the rack standard busbar interface. Validate system type through DMI decode. For new system flavour: - Skip internal power supply configuration. - Attach power hotswap device. Reviewed-by: Michael Shych Signed-off-by: Vadim Pasternak --- drivers/platform/mellanox/nvsw-sn2201.c | 110 +++++++++++++++++++++++- 1 file changed, 107 insertions(+), 3 deletions(-) diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c index abe7be602f84..a6f982a8e874 100644 --- a/drivers/platform/mellanox/nvsw-sn2201.c +++ b/drivers/platform/mellanox/nvsw-sn2201.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -104,6 +105,9 @@ | NVSW_SN2201_CPLD_AGGR_PSU_MASK_DEF \ | NVSW_SN2201_CPLD_AGGR_PWR_MASK_DEF \ | NVSW_SN2201_CPLD_AGGR_FAN_MASK_DEF) +#define NVSW_SN2201_CPLD_AGGR_BUSBAR_MASK_DEF \ + (NVSW_SN2201_CPLD_AGGR_ASIC_MASK_DEF \ + | NVSW_SN2201_CPLD_AGGR_FAN_MASK_DEF) #define NVSW_SN2201_CPLD_ASIC_MASK GENMASK(3, 1) #define NVSW_SN2201_CPLD_PSU_MASK GENMASK(1, 0) @@ -132,6 +136,7 @@ * @cpld_devs: I2C devices for cpld; * @cpld_devs_num: number of I2C devices for cpld; * @main_mux_deferred_nr: I2C adapter number must be exist prior creating devices execution; + * @ext_pwr_source: 1 if system powered by external power supply; 0 - by internal; */ struct nvsw_sn2201 { struct device *dev; @@ -152,6 +157,7 @@ struct nvsw_sn2201 { struct mlxreg_hotplug_device *cpld_devs; int cpld_devs_num; int main_mux_deferred_nr; + u8 ext_pwr_source; }; static bool nvsw_sn2201_writeable_reg(struct device *dev, unsigned int reg) @@ -522,6 +528,35 @@ struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { .mask = NVSW_SN2201_CPLD_AGGR_MASK_DEF, }; +static struct mlxreg_core_item nvsw_sn2201_busbar_items[] = { + { + .data = nvsw_sn2201_fan_items_data, + .aggr_mask = NVSW_SN2201_CPLD_AGGR_FAN_MASK_DEF, + .reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_FAN_MASK, + .count = ARRAY_SIZE(nvsw_sn2201_fan_items_data), + .inversed = 1, + .health = false, + }, + { + .data = nvsw_sn2201_sys_items_data, + .aggr_mask = NVSW_SN2201_CPLD_AGGR_ASIC_MASK_DEF, + .reg = NVSW_SN2201_ASIC_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_ASIC_MASK, + .count = ARRAY_SIZE(nvsw_sn2201_sys_items_data), + .inversed = 1, + .health = false, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data nvsw_sn2201_busbar_hotplug = { + .items = nvsw_sn2201_items, + .counter = ARRAY_SIZE(nvsw_sn2201_busbar_items), + .cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_AGGR_BUSBAR_MASK_DEF, +}; + /* SN2201 static devices. */ static struct i2c_board_info nvsw_sn2201_static_devices[] = { { @@ -557,6 +592,9 @@ static struct i2c_board_info nvsw_sn2201_static_devices[] = { { I2C_BOARD_INFO("pmbus", 0x40), }, + { + I2C_BOARD_INFO("lm5066i", 0x15), + }, }; /* SN2201 default static board info. */ @@ -607,6 +645,58 @@ static struct mlxreg_hotplug_device nvsw_sn2201_static_brdinfo[] = { }, }; +/* SN2201 default basbar static board info. */ +static struct mlxreg_hotplug_device nvsw_sn2201_busbar_static_brdinfo[] = { + { + .brdinfo = &nvsw_sn2201_static_devices[0], + .nr = NVSW_SN2201_MAIN_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[1], + .nr = NVSW_SN2201_MAIN_MUX_CH0_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[2], + .nr = NVSW_SN2201_MAIN_MUX_CH0_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[3], + .nr = NVSW_SN2201_MAIN_MUX_CH0_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[4], + .nr = NVSW_SN2201_MAIN_MUX_CH3_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[5], + .nr = NVSW_SN2201_MAIN_MUX_CH5_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[6], + .nr = NVSW_SN2201_MAIN_MUX_CH5_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[7], + .nr = NVSW_SN2201_MAIN_MUX_CH5_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[8], + .nr = NVSW_SN2201_MAIN_MUX_CH6_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[9], + .nr = NVSW_SN2201_MAIN_MUX_CH6_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[10], + .nr = NVSW_SN2201_MAIN_MUX_CH7_NR, + }, + { + .brdinfo = &nvsw_sn2201_static_devices[11], + .nr = NVSW_SN2201_MAIN_MUX_CH1_NR, + }, +}; + /* LED default data. */ static struct mlxreg_core_data nvsw_sn2201_led_data[] = { { @@ -981,7 +1071,10 @@ static int nvsw_sn2201_config_init(struct nvsw_sn2201 *nvsw_sn2201, void *regmap nvsw_sn2201->io_data = &nvsw_sn2201_regs_io; nvsw_sn2201->led_data = &nvsw_sn2201_led; nvsw_sn2201->wd_data = &nvsw_sn2201_wd; - nvsw_sn2201->hotplug_data = &nvsw_sn2201_hotplug; + if (nvsw_sn2201->ext_pwr_source) + nvsw_sn2201->hotplug_data = &nvsw_sn2201_busbar_hotplug; + else + nvsw_sn2201->hotplug_data = &nvsw_sn2201_hotplug; /* Register IO access driver. */ if (nvsw_sn2201->io_data) { @@ -1198,12 +1291,18 @@ static int nvsw_sn2201_config_pre_init(struct nvsw_sn2201 *nvsw_sn2201) static int nvsw_sn2201_probe(struct platform_device *pdev) { struct nvsw_sn2201 *nvsw_sn2201; + const char *sku; int ret; nvsw_sn2201 = devm_kzalloc(&pdev->dev, sizeof(*nvsw_sn2201), GFP_KERNEL); if (!nvsw_sn2201) return -ENOMEM; + /* Validate system powering type. */ + sku = dmi_get_system_info(DMI_PRODUCT_SKU); + if (!strcmp(sku, "HI168")) + nvsw_sn2201->ext_pwr_source = 1; + nvsw_sn2201->dev = &pdev->dev; platform_set_drvdata(pdev, nvsw_sn2201); ret = platform_device_add_resources(pdev, nvsw_sn2201_lpc_io_resources, @@ -1214,8 +1313,13 @@ static int nvsw_sn2201_probe(struct platform_device *pdev) nvsw_sn2201->main_mux_deferred_nr = NVSW_SN2201_MAIN_MUX_DEFER_NR; nvsw_sn2201->main_mux_devs = nvsw_sn2201_main_mux_brdinfo; nvsw_sn2201->cpld_devs = nvsw_sn2201_cpld_brdinfo; - nvsw_sn2201->sn2201_devs = nvsw_sn2201_static_brdinfo; - nvsw_sn2201->sn2201_devs_num = ARRAY_SIZE(nvsw_sn2201_static_brdinfo); + if (nvsw_sn2201->ext_pwr_source) { + nvsw_sn2201->sn2201_devs = nvsw_sn2201_busbar_static_brdinfo; + nvsw_sn2201->sn2201_devs_num = ARRAY_SIZE(nvsw_sn2201_busbar_static_brdinfo); + } else { + nvsw_sn2201->sn2201_devs = nvsw_sn2201_static_brdinfo; + nvsw_sn2201->sn2201_devs_num = ARRAY_SIZE(nvsw_sn2201_static_brdinfo); + } return nvsw_sn2201_config_pre_init(nvsw_sn2201); } From patchwork Mon Jan 13 08:43:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936925 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2066.outbound.protection.outlook.com [40.107.237.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE5B5249F9 for ; Mon, 13 Jan 2025 08:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736758051; cv=fail; b=NPVDQBEbm6EwGntypM0d13BfuTrNIWblCKnkHxxTaoO8WBzZc/R1m1S4m1/0Ejr1oc/QywhZz4P0XmMk4808xUk1r5FBxswVjKFaKeLxu1FpsKX3ZiLbjJg0OY4VK2yjQVUJFuucO9JZ4aRc0bvT5HnQF1dtr//AjIc5NvaACvY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736758051; c=relaxed/simple; bh=29E62jaDXqCKIB0V/AFpPgsc2C+LlZ3Oe3hOmXkDBJM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mXspLwAMWD12hzg87LT4eTK49HD6Xr5OfwoqmSZED/X5X5MEDiy/v77KV6p0gbG9DT6nCctisMnBqK+VXRndmsMqDXpX/7mm7U7aDRxEp2jLLNmGvkQ9nUpQMon7K6ts/rKoc8DZzB2XOnIe1+BBoubzQsfQWsYzkhhLnVEPkFA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=V9zuUJlv; arc=fail smtp.client-ip=40.107.237.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="V9zuUJlv" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=H34L9y7YsUwAcso4kGG0CQCWnmuydYLxE/yTDcg88/9qSCP1DmdWAN4owEsGGzQjOxwepna1LNS3zMz17JUcgH7xUfHTIevHRamWml6BO82zKDgApqJczGUbvR2oZQ4nI8ASR80AfSaeogaTb4mLCgiCOOMq6cVKUieErfEQpbV2YFO/2iDhX9kzbaOn/jiLFGJPfPLyvicLolYHW0jpn/H9GUJfafbk0XuMN5oSzWm1tUXuMQdjEH6w0O/QUt+DdOTK8DZZUB/CSHqkX3plCKkhuTuYvTTZh4/L7KObz0EoVpKUmkJ68m076zrq7CQeOsPSyARM8GV78ZVDAD13gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=p6S2fwU+ji8u6GbAPz/hXm4Hcdcs6F56f7Dpiog+3EE=; b=vVuQWk/cPyXJHeq8ZV6l4Jeu97i8DWVCQpIz1t75KdQDezfcGVFccmbZWNQpSVmqAXd4gRczwOVNTSlDf4ouwovOl32YgFgi0NlzjTGZDFshN3h9npDmpM3yvSjFfzKy8ho5k57aPuOCTc5Q5KZJCxnZtJfbxpKrw/TqgQuML0IG/LG90qxmrGcISwQlYuAtULSkywQXXq2LuVEEx0+f50bZcPOm2wgC6zvi5sUUjMtHSLdCzutJH+4jwdUYKxMMtFyAFOFAm6QdDYAk/OTAOPrZassNEamsmlmOvlh4RaivnXP9nzL6nbnkRkGWZpl2XJUFSJY+4YBfPBrwA/xbsA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p6S2fwU+ji8u6GbAPz/hXm4Hcdcs6F56f7Dpiog+3EE=; b=V9zuUJlvy0g7FhrI3z6PocjjCFw+Yt1+sFFTAJHizTnFZIe7CjnQpzPuWG05O9IPB5UUfNwKtAAuLQ+fYc6F+ZPftI2DzSYnW0zIqjIYstKiI3jGBRZQYzuAcBnJb91d59dtk9fFuRl9sZHHA0qCBthx37cvIf7EGKko7rei+rotX+/W488kyYV9f1Rk/6nsV9oKY3JOHK19eYiMtTcPweN6+mRbrN990ZvaSXy5h2Ahoft93KvjO4OWEq+pX7UL1JaQtqpMGQG8ILL0QNiBAPmzwv/LMV3XvMDu3TGLPA6GckZXbBGKuoesUYLtusdN7yfF+Z7xobBp3Csj+ExFcg== Received: from CH2PR02CA0016.namprd02.prod.outlook.com (2603:10b6:610:4e::26) by MW6PR12MB8835.namprd12.prod.outlook.com (2603:10b6:303:240::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Mon, 13 Jan 2025 08:47:25 +0000 Received: from CH2PEPF000000A0.namprd02.prod.outlook.com (2603:10b6:610:4e:cafe::9c) by CH2PR02CA0016.outlook.office365.com (2603:10b6:610:4e::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8335.18 via Frontend Transport; Mon, 13 Jan 2025 08:47:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF000000A0.mail.protection.outlook.com (10.167.244.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:47:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:47:15 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:47:13 -0800 From: Vadim Pasternak To: CC: , , , , , "Vadim Pasternak" Subject: [PATCH platform-next v2 10/10] Documentation/ABI: Add new attribute for mlxreg-io sysfs interfaces Date: Mon, 13 Jan 2025 10:43:32 +0200 Message-ID: <20250113084337.24763-11-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084337.24763-1-vadimp@nvidia.com> References: <20250113084337.24763-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|MW6PR12MB8835:EE_ X-MS-Office365-Filtering-Correlation-Id: ccd0765e-8f4d-4d21-36de-08dd33aee75f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: acCDZ8ksNWblNo/aNR7+cozDZGIFUrx59rbY7cZqP6EJhVnsYT1g9A4jmqUVaNR0Q0EGbLQAIOQEwXgASl/aP0RtIlNXb1tJuZygzp7dmn4MGHueBL7c3K19EkOwXaGrawXYt8XewSDS0IZIgEG9HiLKl/GJ+EEShkj3JfI02p42G3ZNwq3ERzqLnCALQ/QvR5G2bez0y/f7oom8WG/bRB2XlCq3tFcgIpIo2AtkjL7W6rZ5YQo+ha+r97DEn8N5Hxat1Xu7FrMU4Gb0Q8Ne6ezKJW4sbX+21RVCil4fAZnYwein2Us8LI6BJOS78Y6h3EKke5NOKy5dalAaCscz31Wlzl5HNAni0dkqqFq+u0wn0klMAAWVQ7ZWBWgmS1jdzbwBkYO+p4KQJY2aZ+wpO8flT8aLJyFTqUFi0gu26QHrCmTjQNmjdr4/PuQDGIL8Un/8KvGdaxe9gYEJs1XVxxj7SD2Ll0x/HOzUw4oXPTQy062ZjzN89HDH5RzPqFe9eNgIXIxnztWQpg7UaUp/92Nidqwc74o8LL6q6m6Og14Bc+0Npe4jaPWSCpx8sA2Mxj3rwNe6aduznqB1iojDhPUztkGiBF1SsMSAr2tTV2ThIReLDvSOa0706N0tMOC9nlOeCtsng0mXUaQ4i6U8VsoPAxH41dQLM/MaFKAabaUl+IGze0mgHASY4v0R33Ei8iM+Pr2F3cTspZf1p0M5HAQ/sm9HIFooFlAb5ONz969ky07olE0Ygo5kE2t9/cLruQXq1J4Pa71mLWxD3QtDXtzoNTDca0+HlWzeu0nGyvZVfT4NexlcSLsVUqEZsLek1eXVQ7rdVNwvA0mmGcqb8+iLaqoa8gwyFSMHI+sP3c/pFGSemFM0si6oYvUzkb6vbUihFolWpmpI+Gxe97IwP8JLcknUgeGxQcRanX2gNUlRS45aDpqSo+T7z9Yn2RqKby03RmkLM7i37MY0STFCAIqnCxUQVDfNVhE/Rj7L1bbFxub0CrNmUoHf+g3NAB1UwHjuFQ+u4P3zHyE8GpHYO5Bg92CvrsTqCT3oDBYlGGQGvH6kqKAGpLcJK1qilyEaZ39P+loiMyxxJxfza1g1a/wA6YAOCCzvLEvTQ7p57tU15m9ccdo17mTTIvDTEw7Sro55MgcOrxefaw3wu2Sa9sqi3y0jBKeE3AvMPEFFkZBKwEL1m6sOBSd+3ztczJgx8ZjKUfxnHuf5FHMMTxJz5jwZjUS14h+Wf/rbE1rgmm+GIyWaTQR+eMnA3pXMqpufbZz7bhaV67WaUMDruqb5MHspuVQOVvLd8MkmF8Pkr4Fuq3pQNQeWE5D+U/ktqnwWRp1IHt5k43Zlj63AQlQlYpmcjbGN06FzWMoOk3hCkdS/U6gwDZ8n/h1cFMKLNfVx66cMw9U8+3x3T/XBoF5HKF0qa/6P8fg2saVVAY4jAckVtbL9fGivXL6/ez3uMT2jy8+cehmt4NblV6MydMdu+LWXO/hAfM8KTEXzH+wW3ck= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:47:25.3862 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccd0765e-8f4d-4d21-36de-08dd33aee75f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8835 Add documentation for the new attributes: - Request and response for access to protetced flashes: "global_wp_request", "global_wp_response". Only for systems equipped with BMC - grant can be provided only by BMC in case its security policy allows to grant access. - Request to unlock ASICs, which has been shutdown due-to ASIC thermal event: "shutdown_unlock". - Data processor Units (DPU) boot progress: "boot_progress". - DPU reset causes: "reset_aux_pwr_or_reload", "reset_dpu_thermal", "reset_from_main_board". - Reset control for DPU components: "perst_rst", "phy_rst", "tpm_rst", "usbphy_rst". - DPU Unified Fabric Manager upgrade - "ufm_upgrade". - Hardware Id of Data Process Unit board - "dpu_id". Reviewed-by: Michael Shych Signed-off-by: Vadim Pasternak --- .../ABI/stable/sysfs-driver-mlxreg-io | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io index 2cdfd09123da..ef6526a6de55 100644 --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io @@ -715,3 +715,99 @@ Description: This file shows 1 in case the system reset happened due to the switch board. The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_request +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: This file when written 1 activates request to allow access to + the write protected flashes. Such request can be performed only + for system equipped with BMC (Board Management Controller), + which can grant access to protected flashes. In case BMC allows + access - it will respond with "global_wp_response". BMC decides + regarding time window of granted access. After granted window is + expired, BMC will change value back to 0. + Default value is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_response +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: This file, when set 1, indicates that access to protected + flashes have been granted to host CPU by BMC. + Default value is 0. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak vadimp@nvidia.com +Description: When ASICs are getting overheated, system protection + hardware mechanism enforces system reboot. After system + reboot ASICs come up in locked state. To unlock ASICs, + this file should be written 1 + Default value is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/boot_progress +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: These files show the Data Process Unit board boot progress + state. Valid states are: + - 4 : OS starting. + - 5 : OS running. + - 6 : Low-Power Standby. + + The file is read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/dpu_id +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: This file shows hardware Id of Data Process Unit board. + + The file is read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_reload +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_dpu_thermal +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_from_main_board +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: These files show the Data Process Unit board reset cause, as + following: reset due to power auxiliary outage or power reload, reset + due to thermal shutdown, reset due to request from main board. + Value 1 in file means this is reset cause, 0 - otherwise. Only one of + the above causes could be 1 at the same time, representing only last + reset cause. + + The files are read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/perst_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/phy_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/tpm_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/usbphy_rst +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: These files allow to reset hardware components of Data Process + Unit board. Respectively PCI, Ethernet PHY, TPM and USB PHY + resets. + Default values for all the attributes is 1. Writing 0 will + cause reset of the related component. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/ufm_upgrade +Date: January 2025 +KernelVersion: 6.14 +Contact: Vadim Pasternak +Description: These files show status of Unified Fabric Manager upgrade. + state. 0 - means upgrade is done, 1 - otherwise. + + The file is read only.