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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF0001AB55.mail.protection.outlook.com (10.167.241.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.11 via Frontend Transport; Mon, 13 Jan 2025 08:49:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:49:27 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:49:25 -0800 From: Vadim Pasternak To: CC: , Vadim Pasternak Subject: [PATCH hwmon 1/2] hwmon: (mlxreg-fan) Separate methods of fan setting coming from different subsystems Date: Mon, 13 Jan 2025 10:48:58 +0200 Message-ID: <20250113084859.27064-2-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084859.27064-1-vadimp@nvidia.com> References: <20250113084859.27064-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB55:EE_|SA1PR12MB6751:EE_ X-MS-Office365-Filtering-Correlation-Id: da620b46-e105-40ed-e896-08dd33af36e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: XxipraXePoiyiXIUuc4ISU8QCJn+T+vNERBOa77FWHnpEDfn+6Uoz+POHfmkwDlplL96Est4X+OpQ2z2Mu2lgeZouhWbNwEsrXDjn0zXf2tTGWhmBRsbfyfFHDHZEzRLQN3TnmxzLyJmottk/cDvh3tBX8NtzPnwvrJBQGE9cqcf3cniLsbicKlHVUclBfRjb+HRKwaw2W+l3WGfQuV7YTvCV9rvsVtuzyBc8Y1Vn3D5y6tTpEn876AJmMcuXY4vFSoAHV9FmMh95Fh5G7eSvs8k4aW9H3x7F02xZUGiEPmMbGPt0kaFbP3B3Ru41acR+//SRdCdzuaTJkBejgt7VYqY4aJBw+9WT5L+hJ/c8rLqV9fPXOqTQJKIc9bommXwIme+WucE57OP7NN/gI7nM4unPPhFHrqu4AEj2AWJtNw9Zpt0/3fGYGOU4t/3QRzQcmLD0nN4+qfDa14IePm/AxUSJksQBG4P06t7jf/ml6LeEdtm7h9pGyy4eCM8+J9k0lNFait4KADSXOJ1EkR3mIH4hTkgbrGs5/5zLA9PT5JBYePpB+/ncjhAu81eJfLxxWmmFs63XybdViL0PIdqGqKj2uEgfX/cb4EneruYcsqt1CUh+i3qTlyxmovvNhfh6Ft+KhkJVPhdDRhqEOEg6hLxUrouDWsLYXPIksdPvMYJcuD6T7oF5/DON0Yb/L5/a+w6gbPF0adYJxZUjosBWVzzBS44KB4uReTseN/m6s6SezE2rd36e1EHvkgUIMglL26IexYemOzYzxanMf5eW77eG++7IrKctx84T+CFpK9J1cpR1IwFPLOFHxXArbZqYJqSE+NK1y2CNZhvKjrHiFwcjhemwiqXO4VVgZiP1S1tPTsWU1P2HBYKPrf6VAcN3Ho0tfUEzcCOD0R8ZmYCG2K//yG3tFZucMzyDHPblhsrmEfwcnHnykkcKO4M08rb63zkjQ8kDk8IJ1z+HWKr6NrnYFiLkK4JP7Z0jAa23zKvYnXky++IXPLqOPNkKehglNMzWg5GtYkmLrTGNbVSkUk1GlTiE7Hud4HNpR0HwXoxI3hkjo7SDH1+drSxKDACmKO1vNzreRsANeyD42gxbGFDbkKQ/LgmPiBT0fnRAx0zMPCpjFpXKJePqZwzLn2P/iyqcMPmJM19OFTmVuaMEEbtuBAcxqX0feyV14qEIQ8cNL3Fk2EPRVbxeDgRsLmFD1mJkELwyfcQe773ZSGCO9NfvpU8RX6A83viWfULJP5gaf88YCArMPiIgrzk+9FGTDlG5q3bpMsrhXesAHhB+iz1M8MWAAPl10j9mobxuWCE2eftwky0AQiNTmdBrbZE4WAIQVt3W+0S1fe22qnhosf3g9cLCKp2CFVCLrGxay7PVgFVwUIWpCXWOS2UdBj2NDM1ASbtwCylOoIMsGeyEz9prjYPmW9dLakRmlq6qmCC0FyIIs73hZUYEzt8AMXGwknzA8rVGmQxFQ7Smb4FYhr3ClRhtcXNqX5MZ/gjIls= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:49:38.7777 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da620b46-e105-40ed-e896-08dd33af36e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB55.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6751 Distinct between fan speed setting request coming for hwmon and thermal subsystems. There are fields 'last_hwmon_state' and 'last_thermal_state' in the structure 'mlxreg_fan_pwm', which respectively store the cooling state set by the 'hwmon' and 'thermal' subsystem. The purpose is to make arbitration of fan speed setting. For example, if fan speed required to be not lower than some limit, such setting is to be performed through 'hwmon' subsystem, thus 'thermal' subsystem will not set fan below this limit. Currently, the 'last_thermal_state' is also be updated by 'hwmon' causing cooling state to never be set to a lower value. Eliminate update of 'last_thermal_state', when request is coming from 'hwmon' subsystem. Fixes: da74944d3a46 ("hwmon: (mlxreg-fan) Use pwm attribute for setting fan speed low limit") Signed-off-by: Vadim Pasternak --- drivers/hwmon/mlxreg-fan.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c index a5f89aab3fb4..f848232c2c00 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -113,8 +113,8 @@ struct mlxreg_fan { int divider; }; -static int mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, - unsigned long state); +static int _mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state, bool thermal); static int mlxreg_fan_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, @@ -224,8 +224,9 @@ mlxreg_fan_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, * last thermal state. */ if (pwm->last_hwmon_state >= pwm->last_thermal_state) - return mlxreg_fan_set_cur_state(pwm->cdev, - pwm->last_hwmon_state); + return _mlxreg_fan_set_cur_state(pwm->cdev, + pwm->last_hwmon_state, + false); return 0; } return regmap_write(fan->regmap, pwm->reg, val); @@ -357,9 +358,8 @@ static int mlxreg_fan_get_cur_state(struct thermal_cooling_device *cdev, return 0; } -static int mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, - unsigned long state) - +static int _mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state, bool thermal) { struct mlxreg_fan_pwm *pwm = cdev->devdata; struct mlxreg_fan *fan = pwm->fan; @@ -369,7 +369,8 @@ static int mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, return -EINVAL; /* Save thermal state. */ - pwm->last_thermal_state = state; + if (thermal) + pwm->last_thermal_state = state; state = max_t(unsigned long, state, pwm->last_hwmon_state); err = regmap_write(fan->regmap, pwm->reg, @@ -381,6 +382,13 @@ static int mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, return 0; } +static int mlxreg_fan_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state) + +{ + return _mlxreg_fan_set_cur_state(cdev, state, true); +} + static const struct thermal_cooling_device_ops mlxreg_fan_cooling_ops = { .get_max_state = mlxreg_fan_get_max_state, .get_cur_state = mlxreg_fan_get_cur_state, From patchwork Mon Jan 13 08:48:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadim Pasternak X-Patchwork-Id: 13936944 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2054.outbound.protection.outlook.com [40.107.96.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8476233D8F for ; Mon, 13 Jan 2025 08:49:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736758188; cv=fail; b=Sr4FKZReHJO4RYzsFFushej7FdQZb9IaGt2lDnatshSPd4ab7Cb9o2SGuwPUAjwFrd+yii/hz34WLX+ZxlT0A4CrAj5sV3T4AJ0iEj7j6T6BGSjB1V/uCzBOhNu3wTVGZKuEDVE1sDqXA13gBJOsaadlhGFOOJnwIbqiC+gs3h8= ARC-Message-Signature: i=2; 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Mon, 13 Jan 2025 00:49:30 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 13 Jan 2025 00:49:29 -0800 From: Vadim Pasternak To: CC: , Vadim Pasternak Subject: [PATCH hwmon 2/2] hwmon: (mlxreg-fan) Add support for new flavour of capability register Date: Mon, 13 Jan 2025 10:48:59 +0200 Message-ID: <20250113084859.27064-3-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250113084859.27064-1-vadimp@nvidia.com> References: <20250113084859.27064-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB57:EE_|DS0PR12MB7606:EE_ X-MS-Office365-Filtering-Correlation-Id: 54dab9a2-a9b6-4375-938a-08dd33af393b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 08:49:42.6790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54dab9a2-a9b6-4375-938a-08dd33af393b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7606 FAN platform data is common across the various systems, while fan driver should be able to apply only the fan instances relevant to specific system. For example, platform data might contain descriptions for fan1, fan2, ..., fan{n}, while some systems equipped with all 'n' fans, others with less. Also, on some systems fan drawer can be equipped with several tachometers and on others only with one. For detection of the real number of equipped drawers and tachometers special capability registers are used. These registers used to indicate presence of drawers and tachometers through the bitmap. For some new big modular systems this register will provide presence data by counter. Use slot parameter to distinct whether capability register contains bitmask or counter. Signed-off-by: Vadim Pasternak --- drivers/hwmon/mlxreg-fan.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c index f848232c2c00..01faf1a8f55a 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -63,12 +63,14 @@ struct mlxreg_fan; * @reg: register offset; * @mask: fault mask; * @prsnt: present register offset; + * @shift: tacho presence bit shift; */ struct mlxreg_fan_tacho { bool connected; u32 reg; u32 mask; u32 prsnt; + u32 shift; }; /* @@ -143,8 +145,10 @@ mlxreg_fan_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, /* * Map channel to presence bit - drawer can be equipped with * one or few FANs, while presence is indicated per drawer. + * Shift channel value if necessary to align with register value. */ - if (BIT(channel / fan->tachos_per_drwr) & regval) { + if (BIT(rol32(channel, tacho->shift) / fan->tachos_per_drwr) & + regval) { /* FAN is not connected - return zero for FAN speed. */ *val = 0; return 0; @@ -408,7 +412,7 @@ static int mlxreg_fan_connect_verify(struct mlxreg_fan *fan, return err; } - return !!(regval & data->bit); + return data->slot ? (data->slot <= regval ? 1 : 0) : !!(regval & data->bit); } static int mlxreg_pwm_connect_verify(struct mlxreg_fan *fan, @@ -545,7 +549,15 @@ static int mlxreg_fan_config(struct mlxreg_fan *fan, return err; } - drwr_avail = hweight32(regval); + /* + * The number of drawers could be specified in registers by counters for newer + * systems, or by bitmasks for older systems. In case the data is provided by + * counter, it is indicated through 'version' field. + */ + if (pdata->version) + drwr_avail = regval; + else + drwr_avail = hweight32(regval); if (!tacho_avail || !drwr_avail || tacho_avail < drwr_avail) { dev_err(fan->dev, "Configuration is invalid: drawers num %d tachos num %d\n", drwr_avail, tacho_avail);