From patchwork Mon Jan 13 10:27:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13937129 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88B6187554 for ; Mon, 13 Jan 2025 10:27:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764075; cv=none; b=XPralEFydqlGk0/lM6zcNwscn1Uzxi/1h5YDKsbh+LFtn2IaTdV1w4on5YEm5ms9c86Sivew/NAOUZ+XrXTGiHzoz/NbLQEEJDYdjBeOge5XbHgE9p2kQb6rTt1++MVX9zAA0/GZ5dERbN/tfsBzBqo0yMnWNg2o/obCywTP7c8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764075; c=relaxed/simple; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aNi5NVhSnxPpePFdy2rR/IyKWxcJM6FGfhKPG362BqkL05jy8f/IYNkDNgjA71DDXDvjmlHBv6TiPvPhPy2baZ0JGFm8RI1YqpYmD7ozC+AAMwDb1i6Qu4b5cm2sQ3ag1acFJeYOeIDwejkDHVyL3CVNrNmzZ2nvr9L98oy90e0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qX07L0kL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qX07L0kL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99078C4CEDD; Mon, 13 Jan 2025 10:27:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736764075; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qX07L0kLNbx9MiVO0V20mPBkr60gkHzUkookBaYblJlv4KaqBsafpSIEI4fuRPPWG HRreGanF2eUI4kSnpyv9oDFoiAO83XNXnxmHLN9AlVJZahEgkVEaKD4I9Xd+wSSZi8 hcs/yKmT6T1A1uCRMAFX2LBEqmCuGZweFVv80niptuIBZO5+IwLQhT/GT8/CQJQb6B b22GnC8dH+f1Z3LrQgrkGedaqBIMFtRcQX9Ljd7Zd84WFm+H0kdCZV88zH7UlfldbO w+FjRLJOf2/rnwZXpBePIbKdevZTUQM9HUvbMJ0atztZikAxxEUm+0wbFxBNFQnEyL 58TMLtmdF7/6w== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v3 1/6] PCI: endpoint: Add BAR type BAR_RESIZABLE Date: Mon, 13 Jan 2025 11:27:32 +0100 Message-ID: <20250113102730.1700963-9-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113102730.1700963-8-cassel@kernel.org> References: <20250113102730.1700963-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3008; i=cassel@kernel.org; h=from:subject; bh=fH/+PtW6Al/BgLEY0tVX9tkQABLvNtrARmIww7kOrA0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJbXk3fMifhZ7BqcrzDIr130y5+K3f0mdtyuuuo9qPZa 81eVDVO6ShlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEPN0Z/ikWvlHJsdtZUXJg E4eIFdeSg6ymV06pnfO0yJV5HF7xzozhD3+O2b4JhQenpTCFC4qFPzr3OOe92Px+VsW6bfwH9r/ 3YQIA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A resizable BAR is different from a normal BAR in a few ways: -The minimum size of a resizable BAR is 1 MB. -Each BAR that is resizable has a Capability and Control register in the Resizable BAR Capability structure. These registers contain the supported sizes and the currently selected size of a resizable BAR. The supported sizes is a bitmap of the supported sizes. The selected size is a single value that is equal to one of the supported sizes. A resizable BAR thus has to be configured differently than a BAR_PROGRAMMABLE BAR, which usually sets the BAR size/mask in a vendor specific way. The PCI endpoint framework currently does not support resizable BARs. Add a BAR type BAR_RESIZABLE, so that an EPC driver can support resizable BARs properly. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, an EPC driver will be able to support resizable BARs (we intentionally only support a single supported resizable BAR size). Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epf-core.c | 4 ++++ include/linux/pci-epc.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 50bc2892a36c..394395c7f8de 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -274,6 +274,10 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, if (size < 128) size = 128; + /* According to PCIe base spec, min size for a resizable BAR is 1 MB. */ + if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M) + size = SZ_1M; + if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) { if (size > bar_fixed_size) { dev_err(&epf->dev, diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index e818e3fdcded..e9d5ed23914f 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -188,11 +188,14 @@ struct pci_epc { * enum pci_epc_bar_type - configurability of endpoint BAR * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC. * @BAR_FIXED: The BAR mask is fixed by the hardware. + * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability. + * An EPC driver can currently only set a single supported size. * @BAR_RESERVED: The BAR should not be touched by an EPF driver. */ enum pci_epc_bar_type { BAR_PROGRAMMABLE = 0, BAR_FIXED, + BAR_RESIZABLE, BAR_RESERVED, }; From patchwork Mon Jan 13 10:27:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13937130 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 153A2BA49 for ; Mon, 13 Jan 2025 10:27:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764079; cv=none; b=r2xtv64EAN1OgLCPDLGB5kA2ggKQo37cR6sw6OwPVOKoYbwYYi0fqxW0K4ze0JimjFwmDDyCCE2fSeVlS6aoiMztSpnd1idj5xXT+9ufApCvYYeS0mBaJE2IcQQo//tMi/WaOzj0ExO7tyWs2r4L+zbqHMEdIbDy6Q/Aufa4dQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764079; c=relaxed/simple; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aoW/yfls2J0D2U/WpnjbI6+TEy93ffe5uYkkuIA8sCixk4BpeumqWMrdlwiBy71H9cyXmX1FmghXhj9J8Y8PWb9tG/thyEPYd7I4niWtAmrBMIf4Q3HCi8Yh2tuPYWFBu+CWBaLdbZ/WZgO4uFSxLz+g1YyHvvFmCqlL1KwLHLQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oCn5FVWp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oCn5FVWp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 68354C4CED6; Mon, 13 Jan 2025 10:27:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736764078; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oCn5FVWp23YzeIG6OAGd37m2TzRoPpZsBFJdF8kBPbc4EsxnsXEiMfFbxgv8oUtx/ 5FCZmnUE2bq9VP9hV23yqNrtiCH6PIsI8/qt22xcRZOs1owOljXPtaxY+MM6raPORY kkosueF+ZZFYdq3KnpBetAAGl/PPyETXifYGIpKUsP1MoNoBVX8SHT6v1b+uw5Ty6N nQUjoqR/kiPulnIQLalyjCTresusMNn39ePATaPLELDlZHkxqz6l6gcYk3wrGwswtE 2DRxuabAF+bPPef4eK3FUQHkXdHvws/1wwiZ+LOaUhNfjzzWJIe4clUH/fkeByxmHw l86Au07nog57w== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v3 2/6] PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability() Date: Mon, 13 Jan 2025 11:27:33 +0100 Message-ID: <20250113102730.1700963-10-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113102730.1700963-8-cassel@kernel.org> References: <20250113102730.1700963-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1884; i=cassel@kernel.org; h=from:subject; bh=Yp1kSs17kW6mzImsCQDNvZePX3qc9b5BoCNjhBaDlP0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJbXs0QWm/5cImE5d8lL+fNrG8OiTj6dprc8tZNNh+vS LKcYNIq6ShlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBE7tsw/M/eNrf0+ip9UwfW 1ebt90/9r+Z4tfObt0rqoZhQh+6NH74wMszJ6/gy//JHPQFbAcHT84QcQ8IrGCaYyM46t054zil NZmYA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Move dw_pcie_ep_find_ext_capability() so that it is located next to dw_pcie_ep_find_capability(). Additionally, a follow-up commit requires this to be defined earlier in order to avoid a forward declaration. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- .../pci/controller/dwc/pcie-designware-ep.c | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8e07d432e74f..6b494781da42 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -102,6 +102,24 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap) return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_header *hdr) { @@ -690,24 +708,6 @@ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); -static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) -{ - u32 header; - int pos = PCI_CFG_SPACE_SIZE; - - while (pos) { - header = dw_pcie_readl_dbi(pci, pos); - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (!pos) - break; - } - - return 0; -} - static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { unsigned int offset; From patchwork Mon Jan 13 10:27:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13937131 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A04E7235C07 for ; Mon, 13 Jan 2025 10:28:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 13 Jan 2025 10:27:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736764082; bh=cQ7WBPPklmp7uBYyIoiOFzUCNA70aPbQK89Wd3riicA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Oozyp28/ER5vFNuS/GxLULVJSzvlwy8D6w3czjhWI7DH6cv5uRlUYc/ueem1ke9wy bniDdk0Y0S+44wySfM0x3gWOVPO06isvkpM7TBLxlWjTxHbpt7aZE2HmKRR+5HMwWw mGKm8LH/qTidoBhe/6QxVt2BAMfvSBWHuc+0+AiCaAZXE2x+dWdOAJHn2khp7ADFcN A9i1pwlF7O5rbEdUqn3HC3/tDqXWoswIeI+pToL4Nd2YXc87LC7y5c6FmS5Y56ck4d BvPeesEGXicsyQwM2C8jwKe1+YkfLaLagTFWOhK6JrA+nTgDlHeIGK4pcgzz/Er56d AgxTP656tQ7MQ== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v3 3/6] PCI: dwc: endpoint: Add support for BAR type BAR_RESIZABLE Date: Mon, 13 Jan 2025 11:27:34 +0100 Message-ID: <20250113102730.1700963-11-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113102730.1700963-8-cassel@kernel.org> References: <20250113102730.1700963-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9829; i=cassel@kernel.org; h=from:subject; bh=cQ7WBPPklmp7uBYyIoiOFzUCNA70aPbQK89Wd3riicA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJbXs2QlHl75O3jD7KX8/gEWyvL3zcX8Ht/N4yO5S2Xj bVR+3mzo5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABOx3MTwv2ifUziv3rEygW/W /t8Cjz+t0K9yW+L1YX5mIkOTxu7DJowM/aZsrGJfGnrXLbrvd7Lr/6fLljfdrs92kF4naXOe+cU 2fgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC databook specifies three different BARn_SIZING_SCHEME_N - Fixed Mask (0) - Programmable Mask (1) - Resizable BAR (2) Each of these sizing schemes have different instructions for how to initialize the BAR. The DWC driver currently does not support resizable BARs. Instead, in order to somewhat support resizable BARs, the DWC EP driver currently has an ugly hack that force sets a resizable BAR to 1 MB, if such a BAR is detected. Additionally, this hack only works if the DWC glue driver also has lied in their EPC features, and claimed that the resizable BAR is a 1 MB fixed size BAR. This is unintuitive (as you somehow need to know that you need to lie in your EPC features), but other than that it is overly restrictive, since a resizable BAR is capable of supporting sizes different than 1 MB. Add proper support for resizable BARs in the DWC EP driver. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, the DWC EP driver will be able to support resizable BARs (we intentionally only support a single supported resizable BAR size). This means that an EPC driver does not need to lie in EPC features, and an EPF driver will be able to set an arbitrary size (not be forced to a 1 MB size), just like BAR_PROGRAMMABLE. Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 195 ++++++++++++++++-- 1 file changed, 180 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 6b494781da42..34c3ae7219f4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -223,6 +223,138 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, ep->bar_to_atu[bar] = 0; } +static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, + enum pci_barno bar) +{ + u32 reg, bar_index; + unsigned int offset, nbars; + int i; + + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (!offset) + return offset; + + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + bar_index = reg & PCI_REBAR_CTRL_BAR_IDX; + if (bar_index == bar) + return offset; + } + + return 0; +} + +static u32 dw_pcie_ep_bar_size_to_rebar_cap(size_t size) +{ + u32 val; + + /* + * According to PCIe base spec, min size for a resizable BAR is 1 MB, + * thus disallow a requested BAR size smaller than 1 MB. + * Disallow a requested BAR size larger than 128 TB. + */ + if (size < SZ_1M || (u64)size > (SZ_128G * 1024)) + return 0; + + val = ilog2(size); + val -= 20; + + /* Sizes in REBAR_CAP start at BIT(4). */ + return BIT(val + 4); +} + +static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + unsigned int rebar_offset; + u32 rebar_cap, rebar_ctrl; + + rebar_offset = dw_pcie_ep_get_rebar_offset(pci, bar); + if (!rebar_offset) + return -EINVAL; + + rebar_cap = dw_pcie_ep_bar_size_to_rebar_cap(size); + if (!rebar_cap) + return -EINVAL; + + dw_pcie_dbi_ro_wr_en(pci); + + /* + * You should not write a BAR mask for a resizable BAR. The BAR mask + * is automatically derived by the controller every time the "selected + * size" bits are updated, see "Figure 3-26 Resizable BAR Example for + * 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write + * BIT(0) to set the BAR enable bit. + */ + dw_pcie_ep_writel_dbi2(ep, func_no, reg, BIT(0)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + /* + * Bits 31:0 in PCI_REBAR_CAP define "supported sizes" bits for sizes + * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" + * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. + */ + rebar_ctrl = dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); + rebar_ctrl &= ~GENMASK(31, 16); + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + + /* + * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically + * updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR + * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a. + */ + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap); + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static int dw_pcie_ep_set_bar_programmable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + + dw_pcie_dbi_ro_wr_en(pci); + + dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(struct dw_pcie_ep *ep, + enum pci_barno bar) +{ + const struct pci_epc_features *epc_features = ep->ops->get_features(ep); + + return epc_features->bar[bar].type; +} + static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { @@ -230,9 +362,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar = epf_bar->barno; size_t size = epf_bar->size; + enum pci_epc_bar_type bar_type; int flags = epf_bar->flags; int ret, type; - u32 reg; /* * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs @@ -264,19 +396,30 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, goto config_atu; } - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - dw_pcie_dbi_ro_wr_en(pci); - - dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); - - if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { - dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + bar_type = dw_pcie_ep_get_bar_type(ep, bar); + switch (bar_type) { + case BAR_FIXED: + /* + * There is no need to write a BAR mask for a fixed BAR (except + * to write 1 to the LSB of the BAR mask register, to enable the + * BAR). Write the BAR mask regardless. (The fixed bits in the + * BAR mask register will be read-only anyway.) + */ + fallthrough; + case BAR_PROGRAMMABLE: + ret = dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar); + break; + case BAR_RESIZABLE: + ret = dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar); + break; + default: + ret = -EINVAL; + dev_err(pci->dev, "Invalid BAR type\n"); + break; } - dw_pcie_dbi_ro_wr_dis(pci); + if (ret) + return ret; config_atu: if (!(flags & PCI_BASE_ADDRESS_SPACE)) @@ -710,9 +853,11 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { + struct dw_pcie_ep *ep = &pci->ep; unsigned int offset; unsigned int nbars; - u32 reg, i; + enum pci_barno bar; + u32 reg, i, val; offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); @@ -727,9 +872,29 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) * PCIe r6.0, sec 7.8.6.2 require us to support at least one * size in the range from 1 MB to 512 GB. Advertise support * for 1 MB BAR size only. + * + * For a BAR that has been configured via dw_pcie_ep_set_bar(), + * advertise support for only that size instead. */ - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4)); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + /* + * While the RESBAR_CAP_REG_* fields are sticky, the + * RESBAR_CTRL_REG_BAR_SIZE field is non-sticky (it is + * sticky in certain versions of DWC PCIe, but not all). + * + * RESBAR_CTRL_REG_BAR_SIZE is updated automatically by + * the controller when RESBAR_CAP_REG is written, which + * is why RESBAR_CAP_REG is written here. + */ + val = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + bar = val & PCI_REBAR_CTRL_BAR_IDX; + if (ep->epf_bar[bar]) + val = dw_pcie_ep_bar_size_to_rebar_cap(ep->epf_bar[bar]->size); + else + val = BIT(4); + + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val); + } } dw_pcie_setup(pci); From patchwork Mon Jan 13 10:27:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13937132 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35D06235C07 for ; Mon, 13 Jan 2025 10:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764085; cv=none; b=UA5sE4etk6ejBQvBPScHkYA7Eew+iD17SXOiFpXrsMhQpSEgeQI5atkcTCorltGRUBEUsMyXvkmq8/UOT3CyGNRbRCmR9fJuN/69IB91n25DGQXUhOuIeR8t8FCnYaVQRbpkFbkhM9m7TZMezTpqqIXdRWT8CHvlNeOxWQiWoR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764085; c=relaxed/simple; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sp9NDOLbAzKsHsW9aYBkCu0nHF5Bl9hFMGMqQbny0ro9z8nZD1TsR3J5qNvggG00gm0SJWgdccKMFQBp9iYl5LS4O2/m7nVzRS40M6dO45y+i/BFU7yn8GqmMDE/k8fMlZ+SwL+AZX9KPZflVOlYVOVV2jW9ars9MXkM3AvtPXM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XdZonzD3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XdZonzD3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1B7CC4CED6; Mon, 13 Jan 2025 10:28:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736764085; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XdZonzD3weGG/HfPVTUzGr16dRN/IN8wONxB/UrdJpoLSCbEce3IOtuOEAbJ8SUR+ rYCsiEyGMlSZJ/jogSVy8hKpOCr5NGRbAHKvL2iMIlAcPEURnrhdlkXWxxJe20EnGX KGpQHF4s+Fwz+Ku1BuLn02nxxqSQR8ZVfqyztpLSItR3JuZbnGLLnTkiJFyrbKqfRJ oReFxtc79aHvFQGqW6etYVH1KZXY1pLy8F3U13sOhUWiHO6IQOr8aZW8XWNas9C+yY D8ifhNUA86R2Idwanxz3ICnEv5hfufT7fNdUVWV5d4/p3KwqhDEqY3+u1fI3ia9v59 Eb4nBDdqBw7MA== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v3 4/6] PCI: keystone: Describe resizable BARs as resizable BARs Date: Mon, 13 Jan 2025 11:27:35 +0100 Message-ID: <20250113102730.1700963-12-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113102730.1700963-8-cassel@kernel.org> References: <20250113102730.1700963-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1286; i=cassel@kernel.org; h=from:subject; bh=dsOF55gCBp2ClK+Wep4E7OIkJHnlYk6Yk3WYdTKco9M=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJbXs188+TkMpljEbNvz44466Vl/KLw8oqb9oK3JPxPH tS9Yqh3oaOUhUGMi0FWTJHF94fL/uJu9ynHFe/YwMxhZQIZwsDFKQATuZvAyDA1XfB+VfyS3bF7 3H57Rup/+D/p267c+V/VkoKPPPsk3f2D4X/IxVvT++4c/voqT+HRootTH27o2X7PVPaFsqbAEfZ 88e2sAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "12.2.2.4.15 PCIe Subsystem BAR Configuration" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf We can see that BAR2 and BAR5 are not Fixed BARs, but actually Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 63bd5003da45..fdc610ec7e5e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -966,10 +966,10 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .msix_capable = true, .bar[BAR_0] = { .type = BAR_RESERVED, }, .bar[BAR_1] = { .type = BAR_RESERVED, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, .align = SZ_1M, }; From patchwork Mon Jan 13 10:27:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13937133 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78314235C07 for ; Mon, 13 Jan 2025 10:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764088; cv=none; b=XYZZgMpP5q9bq6vSzBauaVMfIjJRPkRKb7XQnu211r5GOyrT4cvUB0UmVQaXAjrYcutfxLHx6Uhns5gY1pfT8tu9SJn4omszo4TmpuVj5B9phc3IJowA1p5aiJH6ThOmFK6wNxNYg9daOqLXmKed5vqPBOkYLHCdBj0lqgB2qCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764088; c=relaxed/simple; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A9LLgsnNMdoNUbPvNld6KnWkZKS2g2gis826+mVF1GbTGe5aa4dvKR6RyUXNgNGb7Ry/IQ+pzQQkJCb6G1LlDl3kDvvBuQ+KnRR+AZ0E+E6IiAgKz6/P1/pBBhYclruiqxGpQLJzzBMkRvQEs6OjzdE4B3B1WC5gJ40c0Ec7cqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eKze5RCg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eKze5RCg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6D04C4CEE2; Mon, 13 Jan 2025 10:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736764088; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eKze5RCgbzv8dcfTltJK+m1k4CNZG9GWYrTjuoyVrMzaBEIp1ZCwlW7fBl625nSl5 eamfezyBTn7aqy4vgWMqAFIITmlXqUXTV5oL8tVUDe2PUjubEa//39dJE1XU5HxaSi seWMT7hnCRukri4nPeJBMORy+IyvzqWNqcX+hEUX4+t0+ytesBk/AOTlA/CYF/Cq4k cyUJK+Av20Zx7GUtkCbQJX+r1Xem86fiSsH1fc3mIvmcC2avbhiwDSDlNGjvu121P0 xZCj+qsICu0dtjkAUQC51ffKc6xmH0DWSc7hoviT4bh2KdGm9W1C1/4DYDpxkNVehU O3DUBpewH6D2g== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v3 5/6] PCI: keystone: Specify correct alignment requirement Date: Mon, 13 Jan 2025 11:27:36 +0100 Message-ID: <20250113102730.1700963-13-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113102730.1700963-8-cassel@kernel.org> References: <20250113102730.1700963-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1604; i=cassel@kernel.org; h=from:subject; bh=9O4nRSIfQmKcND2iuEtQIlbKli8kf9nI8aNTK97IxIc=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJbXs2UXXq6dQdPg06id9yM3e1LV8r1X+fOlarRtb+e9 PlgzFKLjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAExENIORYXXRdLatfAq/dySx nnNl4z5ipmESL6uQcSlM5ATHmpCe5wz/A0Sa74k9SK39e0cgwGFf5cmiFT8PLa8323eog7VDcd0 PdgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The support for a specific iATU alignment was added in commit 2a9a801620ef ("PCI: endpoint: Add support to specify alignment for buffers allocated to BARs"). This commit specifically mentions both that the alignment by each DWC based EP driver should match CX_ATU_MIN_REGION_SIZE, and that AM65x specifically has a 64 KB alignment. This also matches the CX_ATU_MIN_REGION_SIZE value specified by "12.2.2.4.7 PCIe Subsystem Address Translation" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf This higher value, 1 MB, was obviously an ugly hack used to be able to handle Resizable BARs which have a minimum size of 1 MB. Now when we actually have support for Resizable BARs, let's configure the iATU alignment requirement to the actual requirement. (BARs described as Resizable will still get aligned to 1 MB.) Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-keystone.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fdc610ec7e5e..76a37368ae4f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -970,7 +970,7 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, .bar[BAR_5] = { .type = BAR_RESIZABLE, }, - .align = SZ_1M, + .align = SZ_64K, }; static const struct pci_epc_features* From patchwork Mon Jan 13 10:27:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13937134 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 064BD235C07 for ; Mon, 13 Jan 2025 10:28:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764092; cv=none; b=i1BcpRB8+caDhDx/PO5kyGmxL+YJAGtz2RPRKKcJEg2mHrU16JzJ+V2i9sT8t3PCk7obicwFKXDTH1LOv78D0UJDxibADJXRtT1PY4MkAE2cdzG/Mrep57oi0DbeDOq5XaUusSP3viJl//ITeOC5EvPqAtn7llbes8c5GdFB/Jk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736764092; c=relaxed/simple; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N+UqxDSfW6rGRPVn9ouiKYp2NMfaY/VcuO012VZULTx0oI4qnvo4erBHyeXl9wi8rdlQfu08N2EyfPgopheW6eTwXRRG5EHscNDjwSL3Wy9i1V1kphv4nK0j3aWBE18BgXYNrKX9NMtas85VNNcLx7MedyD6q+vNgoq7AKIcZzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k46+ZMIP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k46+ZMIP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AEADDC4CED6; Mon, 13 Jan 2025 10:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736764091; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k46+ZMIP6SHUP2Fkk1BFOsyeCxNX7n2Tbjur95ZFq5q2DbYzf7Sq7EDdqsA8gxEw5 570kJOPmVAKjtq8E9Y0dQK+N6RUIYBoAPh1pf8BclgS2AoQSKlvcj6V+7UmQC7mIvC d5tqvfmtzqkpnwC1+bmRQXvrRUAgd99KDExOArPK3jp+uz2O4kmquwgbeLJQpflqNN lAaxMVXiDX/VqfFItKZm0K1OR1kNR9F6xwBYmpfQKxM9JI+JctSA9RMh/y5e2JNAqS g/K7zuvMLn60B2XgLZ2+GjAoNBJ7fDdNtAb9EFajN/cChTAQ2P4+8MBXv3SsExmI/6 VH9T+9u0N03Cg== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 6/6] PCI: dw-rockchip: Describe resizable BARs as resizable BARs Date: Mon, 13 Jan 2025 11:27:37 +0100 Message-ID: <20250113102730.1700963-14-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113102730.1700963-8-cassel@kernel.org> References: <20250113102730.1700963-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2520; i=cassel@kernel.org; h=from:subject; bh=YjPRYyKxFWfwBGyFIc8FXbd9BDk5/XxDt0/Kay6MfyM=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJbXs08/n9iHc+0po1bBV95XOt7xmsjf82T498kUZ67P 91vNnQs7ihlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBE7GMY/kpNM51z/fnWH8tX b7Xh0/42q2HXBuZbPxdmfDMJZlx2vlGE4X9Z2e8H766k1KS8PhzEVXg+4ctaAwNWl2L7hMSNJ9o X/eEBAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM, we can see that none of the BARs are Fixed BARs, but actually Resizable BARs. I couldn't find any reference in the rk3568 TRM, but looking at the downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same, so the BARs on rk3568 must also be Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index ce4b511bff9b..6a307a961756 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, + .bar[BAR_4] = { .type = BAR_RESIZABLE, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; /* @@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, .bar[BAR_4] = { .type = BAR_RESERVED, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; static const struct pci_epc_features *