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Mon, 13 Jan 2025 03:23:59 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:23:58 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 1/6] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block Date: Mon, 13 Jan 2025 11:23:44 +0000 Message-ID: <20250113112349.801875-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. For example, specific bits in these registers indicate resets caused by events such as underflow or overflow of the watchdog timer. This functionality allows the watchdog driver to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Add the syscon-compatible property to the RZ/V2H(P) and RZ/G3E CPG block, allowing drivers to interact with the CPG_ERROR_RSTm registers as required. Signed-off-by: Lad Prabhakar --- Note, there is no ABI breakage as, this series adds the first `syscon` user and also note the driver doesnt fail if the `syscon` property isnt present in the cpg node to handle backward compatibility. --- v2->v3 - No change v1->v2 - No change --- .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f42d79e73e70 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -17,9 +17,11 @@ description: properties: compatible: - enum: - - renesas,r9a09g047-cpg # RZ/G3E - - renesas,r9a09g057-cpg # RZ/V2H + items: + - enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H + - const: syscon reg: maxItems: 1 @@ -73,7 +75,7 @@ additionalProperties: false examples: - | clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; 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Mon, 13 Jan 2025 03:24:00 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:23:59 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 2/6] arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node Date: Mon, 13 Jan 2025 11:23:45 +0000 Message-ID: <20250113112349.801875-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `syscon` compatible for CPG node to allow the IP blocks to interact with the CPG registers as needed. Signed-off-by: Lad Prabhakar --- v2->v3 - No change v1->v2 - No change --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 200e9ea89193..57fbe92e794e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -145,7 +145,7 @@ pinctrl: pinctrl@10410000 { }; cpg: clock-controller@10420000 { - compatible = "renesas,r9a09g047-cpg"; + compatible = "renesas,r9a09g047-cpg", "syscon"; reg = <0 0x10420000 0 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; From patchwork Mon Jan 13 11:23:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13937170 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CB072451C0; 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Mon, 13 Jan 2025 03:24:01 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:24:00 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 3/6] arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node Date: Mon, 13 Jan 2025 11:23:46 +0000 Message-ID: <20250113112349.801875-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `syscon` compatible for CPG node to allow the IP blocks to interact with the CPG registers as needed. Signed-off-by: Lad Prabhakar --- v2->v3 - No change v1->v2 - No change --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 3938b9740959..e7428b80bda2 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -243,7 +243,7 @@ pinctrl: pinctrl@10410000 { }; cpg: clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0 0x10420000 0 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal"; From patchwork Mon Jan 13 11:23:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13937171 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D5B32451E0; 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Mon, 13 Jan 2025 03:24:02 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:24:01 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 4/6] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property Date: Mon, 13 Jan 2025 11:23:47 +0000 Message-ID: <20250113112349.801875-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The RZ/V2H(P) CPG block includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. In the event of a watchdog overflow or underflow, a system reset is issued, and the CPG_ERROR_RST2[0/1/2/3] bits are set depending on the watchdog in use: CM33 = 0, CA55 = 1, CR8_0 = 2, CR8_1 = 3. For the watchdog driver to determine and report the current boot status, it needs to read the CPG_ERROR_RST2[0/1/2/3]bits and provide this information to the user upon request. To facilitate this operation, add `renesas,syscon-cpg-error-rst` property to the WDT node, which maps to the `syscon` CPG node, enabling retrieval of the necessary information. Additionally, the property is marked as required for the RZ/V2H(P) SoC to ensure future compatibility (e.g., where the same IP block is present on the RZ/G3E SoC) and explicitly disallowed for other SoCs. Signed-off-by: Lad Prabhakar --- Note, this change doesnt break any ABI, as the subsequent driver patch handles the case elegantly if the `syscon` node is missing to handle backward compatibility. v2->v3 - No change v1->v2 - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst` - Updated commit message --- .../bindings/watchdog/renesas,wdt.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 29ada89fdcdc..ca62ae8b1b0c 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -112,6 +112,19 @@ properties: timeout-sec: true + renesas,syscon-cpg-error-rst: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The first cell is a phandle to the SYSCON entry required to obtain + the current boot status. The second cell specifies the CPG_ERROR_RSTm + register offset within the SYSCON, and the third cell indicates the + bit within the CPG_ERROR_RSTm register. + items: + - items: + - description: Phandle to the CPG node + - description: The CPG_ERROR_RSTm register offset + - description: The bit within CPG_ERROR_RSTm register of interest + required: - compatible - reg @@ -182,7 +195,11 @@ allOf: properties: interrupts: false interrupt-names: false + required: + - renesas,syscon-cpg-error-rst else: + properties: + renesas,syscon-cpg-error-rst: false required: - interrupts From patchwork Mon Jan 13 11:23:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13937172 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49913246332; 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Mon, 13 Jan 2025 03:24:03 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:24:02 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information Date: Mon, 13 Jan 2025 11:23:48 +0000 Message-ID: <20250113112349.801875-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar On the RZ/V2H(P) SoC we can determine if the current boot is due to `Power-on-Reset` or due to the `Watchdog`. The information used to determine this is present on the CPG block. The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an reset. CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an underflow/overflow on WDT1 causing an error interrupt. To fetch this information from CPG block `syscon` is used and bootstatus field in the watchdog device is updated based on the CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it. Signed-off-by: Lad Prabhakar --- Note, this change doesnt break any ABI, if the `syscon` node is missing the driver probe continues further to handle backward compatibility. v2->v3 - No change v1->v2 - Returned ret in error path instead of -EINVAL - Dropped unnecessar regmap_read --- drivers/watchdog/rzv2h_wdt.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index 8defd0241213..ab7e35928190 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -4,14 +4,17 @@ * * Copyright (C) 2024 Renesas Electronics Corporation. */ +#include #include #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -40,6 +43,9 @@ #define WDT_DEFAULT_TIMEOUT 60U +#define CPG_ERROR_RST2(x) BIT(x) +#define CPG_ERROR_RST2_WEN(x) BIT((x) + 16) + static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" @@ -206,9 +212,37 @@ static const struct watchdog_ops rzv2h_wdt_ops = { static int rzv2h_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct rzv2h_wdt_priv *priv; + unsigned int bootstatus = 0; + struct regmap *syscon; int ret; + /* Do not error out to maintain old DT compatibility */ + syscon = syscon_regmap_lookup_by_phandle(np, "renesas,syscon-cpg-error-rst"); + if (!IS_ERR(syscon)) { + struct of_phandle_args args; + u32 reg; + + ret = of_parse_phandle_with_fixed_args(np, "renesas,syscon-cpg-error-rst", + 2, 0, &args); + if (ret) + return ret; + + ret = regmap_read(syscon, args.args[0], ®); + if (ret) + return ret; + + if (reg & CPG_ERROR_RST2(args.args[1])) { + ret = regmap_write(syscon, args.args[0], + CPG_ERROR_RST2(args.args[1]) | + CPG_ERROR_RST2_WEN(args.args[1])); + if (ret) + return ret; + } + bootstatus = reg & CPG_ERROR_RST2(args.args[1]) ? WDIOF_CARDRESET : 0; + } + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -243,6 +277,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev) priv->wdev.info = &rzv2h_wdt_ident; priv->wdev.ops = &rzv2h_wdt_ops; priv->wdev.parent = dev; + priv->wdev.bootstatus = bootstatus; watchdog_set_drvdata(&priv->wdev, priv); watchdog_set_nowayout(&priv->wdev, nowayout); watchdog_stop_on_unregister(&priv->wdev); From patchwork Mon Jan 13 11:23:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13937204 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A705C2500B3; Mon, 13 Jan 2025 11:24:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 13 Jan 2025 03:24:04 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.24.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:24:04 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 6/6] arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst` property to WDT node Date: Mon, 13 Jan 2025 11:23:49 +0000 Message-ID: <20250113112349.801875-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add `renesas,syscon-cpg-error-rst` property to WDT node, to determine whether the current boot resulted from a `Power-on Reset` or a `Watchdog Reset`. Signed-off-by: Lad Prabhakar --- v2->v3 - No change v1->v2 - No change --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index e7428b80bda2..01b4b4184e5c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -445,6 +445,7 @@ wdt0: watchdog@11c00400 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x75>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 0>; status = "disabled"; }; @@ -455,6 +456,7 @@ wdt1: watchdog@14400000 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x76>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>; status = "disabled"; }; @@ -465,6 +467,7 @@ wdt2: watchdog@13000000 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x77>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 2>; status = "disabled"; }; @@ -475,6 +478,7 @@ wdt3: watchdog@13000400 { clock-names = "pclk", "oscclk"; resets = <&cpg 0x78>; power-domains = <&cpg>; + renesas,syscon-cpg-error-rst = <&cpg 0xb40 3>; status = "disabled"; };