From patchwork Mon Jan 13 17:27:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13937831 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709661B6CE3; Mon, 13 Jan 2025 17:27:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736789242; cv=none; b=gdb0QP596thWHu2RMsHWDi7KKwefPjALZdnB38qxNCuvJmUPOjkxQGFEXeiawk7iJnNddq3fyGQZaNqP2KLz07GijipNODEdKp7VS0CQ4sqNfybvMT9dwyi5x3pim0mTZoQiS/V+vwEJIKrckovbBjYfybX+6SJEtJd3sC9tqcg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736789242; c=relaxed/simple; bh=2rFQ5V+qiVNqzWe99MRI9waBj3AoywN2TQFZDho1GG8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=UKx4A0nSkBEwYGyp9JeFFHVVuNzqzLms9ph240qBO8N794eo6IEm8Ls9aE4cKMssoDjcHXTnknqb+1y/U8XA7TJPkh31rQbHwxWORHItHT2LdC7m+dvcAB//fI50Vq9LurU3F3L+xg3LXS7YFiY5qUC/zF+wx6yNgGHTzz6Yclk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=hypVi124; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hypVi124" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50DEm4wI024305; Mon, 13 Jan 2025 17:27:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zQZ4mpJGOb5W8SabxO7F1NHae0Oa6byLQQNJ2o4fWZo=; b=hypVi124z9rAchAn GN3Y+CL6YzPzi3Ctw706Cs344j9uWrXE3OarGcNvk6TzH8R00hS6FSrp4j+09FYQ dzaM9PN8tYZHXAnqgx35hBpecyFAq4Wu07Od+clo7HPT2BmyAOJPT8aAaobSwZcf AQeR/r3swHcFt5u3Bghw1GSapNkbv+lV/0a95DU4HGDO491tudoADULZLb+WpfeD zMwzUqxAytyP9glfqlcx+DPKq/91bauu5SjQhkg+WavYouOBRFoIiwJaZ0yjefSL WOsjYHdQBDNaQbUuMAkQjYQzw+l8TtWfrclHwLbe16P0Ay5UAzrJXT4WUXrM5cXn J5VFcw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 444wt4stq8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jan 2025 17:27:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50DHRFJA018932 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jan 2025 17:27:15 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 13 Jan 2025 09:27:12 -0800 From: Taniya Das Date: Mon, 13 Jan 2025 22:57:04 +0530 Subject: [PATCH 1/3] clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250113-support-pll-reconfigure-v1-1-1fae6bc1062d@quicinc.com> References: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> In-Reply-To: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 5Y6EfRsFZIiWYi9G6lPgEeDaIfIRYe0A X-Proofpoint-GUID: 5Y6EfRsFZIiWYi9G6lPgEeDaIfIRYe0A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501130141 Integrate the PLL configuration into clk_alpha_pll to facilitate future reuse as needed. This is particularly useful when the PLL requires reconfiguration. Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 79aca8525262211ae5295245427d4540abf1e09a..943320cdcd10a6c07fcd74dccb88be847dc086c2 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -81,6 +81,7 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @regs: alpha pll register map (see @clk_alpha_pll_regs) + * @config: array of pll settings * @vco_table: array of VCO settings * @num_vco: number of VCO settings in @vco_table * @flags: bitmask to indicate features supported by the hardware @@ -90,6 +91,7 @@ struct clk_alpha_pll { u32 offset; const u8 *regs; + const struct alpha_pll_config *config; const struct pll_vco *vco_table; size_t num_vco; #define SUPPORTS_OFFLINE_REQ BIT(0) From patchwork Mon Jan 13 17:27:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13937832 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 678BB1BC9FB; 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Mon, 13 Jan 2025 17:27:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50DHRJjl018947 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jan 2025 17:27:19 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 13 Jan 2025 09:27:15 -0800 From: Taniya Das Date: Mon, 13 Jan 2025 22:57:05 +0530 Subject: [PATCH 2/3] clk: qcom: clk-alpha-pll: Add support to reconfigure PLL Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250113-support-pll-reconfigure-v1-2-1fae6bc1062d@quicinc.com> References: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> In-Reply-To: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AK7x0Ji31-pGgO4-TpMEk6st-AGn9Lxm X-Proofpoint-GUID: AK7x0Ji31-pGgO4-TpMEk6st-AGn9Lxm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501130140 During boot-up, there is a possibility that the PLL configuration might be missed even after invoking pll_configure() from the clock controller probe. This is often due to the PLL being connected to rail or rails that are in an OFF state and current clock controller also cannot vote on multiple rails. As a result, the PLL may be enabled with suboptimal settings, leading to functional issues. The PLL configuration, now part of clk_alpha_pll, can be reused to reconfigure the PLL to a known good state before scaling for frequency. The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs in future. Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 9a65d14acf71c97912664be4f6f78891cab4afa3..eb27c0992c7f9281dac4f2fc792084292c21a6c1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1750,6 +1750,26 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); } +#define GET_PLL_TYPE(pll) ((pll->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) +static void clk_alpha_pll_reconfigure(struct clk_alpha_pll *pll) +{ + if (!pll->config || !pll->regs) + return; + + pr_debug("configuring the PLL again!\n"); + + switch (GET_PLL_TYPE(pll)) { + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: + clk_lucid_ole_pll_configure(pll, pll->clkr.regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: + clk_lucid_evo_pll_configure(pll, pll->clkr.regmap, pll->config); + break; + default: + break; + } +} + static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, u32 latch_bit, u32 latch_ack) { @@ -1765,6 +1785,11 @@ static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, if (ret < 0) return ret; + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &val); + /* Check if the PLL is in good state to accept set rate requests. */ + if (!(val & LUCID_EVO_PLL_L_VAL_MASK)) + clk_alpha_pll_reconfigure(pll); + regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); @@ -2372,6 +2397,11 @@ static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) if (trion_pll_is_enabled(pll, regmap)) return 0; + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &val); + /* Check if the PLL is in good state to accept enable requests */ + if (!(val & LUCID_EVO_PLL_L_VAL_MASK)) + clk_alpha_pll_reconfigure(pll); + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 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Mon, 13 Jan 2025 17:27:22 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 13 Jan 2025 09:27:19 -0800 From: Taniya Das Date: Mon, 13 Jan 2025 22:57:06 +0530 Subject: [PATCH 3/3] clk: qcom: videocc-sm8550: Update the pll config for Video PLLs Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250113-support-pll-reconfigure-v1-3-1fae6bc1062d@quicinc.com> References: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> In-Reply-To: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7rGEfOkiBJvdV63JySzYrpTY7f5ULLB4 X-Proofpoint-GUID: 7rGEfOkiBJvdV63JySzYrpTY7f5ULLB4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxlogscore=708 malwarescore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501130141 The video plls are on MxC rail and needs to be configured before being used for functional use case, so update the pll configs as part of the pll structure. Signed-off-by: Taniya Das --- drivers/clk/qcom/videocc-sm8550.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index 7c25a50cfa970dff55d701cb24bc3aa5924ca12d..ed94a72d6c1b064fd767df0c691d0273ef106e84 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -51,6 +51,7 @@ static struct alpha_pll_config video_cc_pll0_config = { static struct clk_alpha_pll video_cc_pll0 = { .offset = 0x0, + .config = &video_cc_pll0_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -82,6 +83,7 @@ static struct alpha_pll_config video_cc_pll1_config = { static struct clk_alpha_pll video_cc_pll1 = { .offset = 0x1000, + .config = &video_cc_pll1_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],