From patchwork Tue Jul 24 14:17:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 10542227 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DBC214BC for ; Tue, 24 Jul 2018 14:18:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6AB2228ADE for ; Tue, 24 Jul 2018 14:18:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E37F28AF4; Tue, 24 Jul 2018 14:18:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6077128ADE for ; Tue, 24 Jul 2018 14:18:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=G5Ef+ThTzOkK7LneCGvyxImUD1I41eJo2Zzy7MtHFek=; b=nSEcU6bxJvM1jz 2xVZkQt0LYvro0hyQcZ3temUQvUNlNRQBoAUKAbNReFkQqquHl3kX7yFcaIVC5sI6u/wtYO0EP1Yd rtAI/QR7j5h91X8lsdldU+i88Ml/U2EypxtzbMTWjkHpnR8qGYBpglyxlKRaZrY04llCpWSsCb/L8 +T+V4ZmV6IlScImO4z5gM2q4BoU+b+tbM7wegq3OS3RizsPw0oAmCaUwWdapWbpxyMq8fr9HpqYTz TIlMPJ+1StOY7jzoDPk5AiKQgrvly9T3QostYywRPhP5h/O66Cy34YhCWyYKCYjf8cbptT4Ir7OeW P6B0An/9H/xJHNfkGqDw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fhy8m-0006FE-26; Tue, 24 Jul 2018 14:18:16 +0000 Received: from mail-co1nam05on0600.outbound.protection.outlook.com ([2a01:111:f400:fe50::600] helo=NAM05-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fhy8i-0006CW-Va for linux-arm-kernel@lists.infradead.org; Tue, 24 Jul 2018 14:18:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ANTBhagBtqHzmgOzh01sQhYySbQD4UUaqWElqp/WsDU=; b=F4jebwijQTcx+mjmLIuPATrU832vzgZO1sA+uoI3XevTZPvo7tMwivqdzVCZ1fb0l6IdxzAM937O/iAv014ahBnzqlb7PiKSeYYKhSvGcQutvD1gk6EYZ04A3DE/vioxU6ZwaZshHoG9Y7O4L3/FVQEjJKxmwhHhNioF0/kdemE= Received: from MWHPR0201CA0052.namprd02.prod.outlook.com (2603:10b6:301:73::29) by CY1PR02MB1625.namprd02.prod.outlook.com (2a01:111:e400:5299::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.973.21; Tue, 24 Jul 2018 14:17:59 +0000 Received: from CY1NAM02FT060.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e45::209) by MWHPR0201CA0052.outlook.office365.com (2603:10b6:301:73::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.973.16 via Frontend Transport; Tue, 24 Jul 2018 14:17:59 +0000 Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by CY1NAM02FT060.mail.protection.outlook.com (10.152.74.252) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.995.12 via Frontend Transport; Tue, 24 Jul 2018 14:17:58 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:53984 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1fhy8T-0000Xc-UH; Tue, 24 Jul 2018 07:17:57 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fhy8O-0004O5-UP; Tue, 24 Jul 2018 07:17:52 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w6OEHi16004201; Tue, 24 Jul 2018 07:17:44 -0700 Received: from [172.23.37.94] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fhy8G-0004NT-3H; Tue, 24 Jul 2018 07:17:44 -0700 From: Appana Durga Kedareswara rao To: , , , Subject: [PATCH v3 1/2] fpga: fpga-mgr: Add readback support Date: Tue, 24 Jul 2018 19:47:37 +0530 Message-ID: <1532441858-13507-1-git-send-email-appana.durga.rao@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(396003)(39860400002)(136003)(346002)(376002)(2980300002)(438002)(199004)(189003)(186003)(356003)(6346003)(7696005)(106002)(8676002)(26005)(336012)(6666003)(51416003)(478600001)(81166006)(81156014)(47776003)(2906002)(8936002)(54906003)(36386004)(77096007)(110136005)(316002)(486006)(476003)(2616005)(16586007)(6636002)(2201001)(426003)(126002)(14444005)(305945005)(63266004)(50226002)(48376002)(106466001)(5660300001)(36756003)(50466002)(9786002)(4326008)(107886003)(107986001)(5001870100001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR02MB1625; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; LANG:en; PTR:xapps1.xilinx.com,unknown-60-100.xilinx.com; A:1; MX:1; X-Microsoft-Exchange-Diagnostics: 1; CY1NAM02FT060; 1:n2+6du54LkCPJdPHiDhEgFZ0B9x80tUNY9GHw83vRLyqa8RSVjV1sUIzvVyhEH0GBeGIj5eUILRydoCVrFgqKpjVmEFq1zAEtDUbKIOABZtAIi7e9e0kRfRKaKYMctXI MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 41cd3443-aab8-44d0-270f-08d5f17041fe X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600073)(711020)(4608076)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060); SRVR:CY1PR02MB1625; X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 3:5s8fWJqOjQKm75dR+QddYcB4MDdZ6mB5ROCAW8puUHL0bisCwEGdUgKgMNZnnNQ8/V2WJQI3tal4zN+VtrfgLCxVBWgdtZnWLJ/oTzxJa9Mvo76QtGNiZt5U5qQpiV7SYMGGgoFU607o1chAQUo7or5yWLI2kosHGFPDAsvpMu4v+Yl3mSnKk4a3vWRjSwGafkBI8tQt/ejkP17TF2lyUmBQiIrth7Inu8CZep4iZyOZFlGa4IejemB5OeLKZa9HoLQmqqTlcFUTAjxJJWU3X92e/FU4JZJLSqlWcisIYjxRSygnT6BfE1C2LULSsdypInultLxEpTUFmOf3G7BSnGAhbhWaD4KYNR2UF9OV7zY=; 25:6f6dyxexi6Nc2jNiAJU6m9U2mlxLfDriEkTwU+t11JS2MwbxykVomoV1fe/1cxOm0h9KzHuD5hj4yNexyTWeBtDXSSWxVKEQY9SGuZYGliuzROtqEWsfBje0fHI7+JaAGhc4x0LEf54mFBSo3z+j5PnW40WvpTPcSnIzfICBm2adwJv4kAvM+2MB4g+s+OA4xsiPDxQKQ8J9feWsIOSjMuSSyRFP4okFVaW6BYqnDaUDHeEGSAH/8vr4ig+fCQIbxCEhtBYsPEhI/kNDeC4ahJrAshC2rmnnfOTRXBJH/ddo/0AXoq27Apkf4VEu15SoYLmwkYSAOOVPDasuL/j2ww== X-MS-TrafficTypeDiagnostic: CY1PR02MB1625: X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 31:OQ7cuHvqhKalaFJDgL0e+WMx54s60EzlNyDsmS192B2cRl7MOLJH1OiBreg+X6qDKDukt23bebvUwmZPP2ilBBTtOD45NrB6dQm2wPwubXtUMo1Jy62Mo9wf393JxlxGqjI47jpcXoktyiB4kK+D/KXPvsmfEJUvCl3yUrRP0ku0dY+dk+0QPMU3BRI1IXcZgHWpvKbCnhFQ7WTUJNPs0m3lcf330Grb06e4XU00jxg=; 20:hdpDHNmIma3MyKzl7Cq5xjS4IsAq79hmhKjslo8FWtqYIjfwQ1JvFubpI4MimD59f+t4utefVsjI+O40ekhipN4TMNMm0FaerL/0WhTDW+XodjhqGZaSYstQMjT301k12Cbyk6wCSN4TjuixYnVmkYhS/8y/NhnoRgK7eLsFxepBaVfo+douCQbpquiy/S43kPJd97RoUs0+ehiXm6qPVboGzO6oZQ4ksu6iSSdGQ8gaQN0V4NsEsBOHa4YbhgBKgdpoB9OCQLyUzyPVRyBnaxhRTS/kp8ZUNFeyJnIAt2mnyDoUc0IZxxsMbT3jZM4q+BrTrfAtmpiSIe7pwqix6Q8FLQIg5dvkJ30hfQBhm9j3OGGfAYbO86G4yWJiAurhhlHFsaDCWVmaPCBn6btGEgyxnC9utqyhsTMVLBXLnVnXy+0+WdUKtamSTknCdsgWixZRIG6eDAZ8mL0kyh83T34UAmStbatOnZ5TD4SLv2i2bArFEeKUhI+9Ar4ZCImU X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231311)(944501410)(52105095)(93006095)(93004095)(10201501046)(3002001)(6055026)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(6072148)(201708071742011)(7699016); SRVR:CY1PR02MB1625; BCL:0; PCL:0; RULEID:; SRVR:CY1PR02MB1625; X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 4:VO6hrf2SV3JCmlgrKyrDS6Ki17kk+UqqLiO844tEm80ufhY1j0XTG4tBzAElpqKaS1dUB7i9181qUoV2agDXid30a9lTllavbjvJH5xnxPTk5wy93bQdTJltAlxmQmCkwB952uWI+t5ZCLQCRCb3W0OoxFa3cCc3LROCdBxUKOlzfL8vqgZ/szsv94iKbI/udSoWFymffs8d6IRbpumB9ZTuR6YFIPeNcegqx9XiSBEJeDKfz/r31T2v+EpCCCmMlidlc1iu+w1z1xCZzTfPcaMLsDCZmP4OL7UJzgBnsybUt0lSqABV5/P9YsSTrsHs X-Forefront-PRVS: 0743E8D0A6 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR02MB1625; 23:3aDIKyEPkbOqg/arMvNNkpLiL/KrUpc+6zGWr97gj?= 4EZjCTpwWVqM7wKB52/8TdlCFzgQdYqyscwDCIhmV9/filyVOMA7CZQg7/KKstZcHwaxrv7Yeqq3eUkJ4y/WUT+zgqMtgGn87ufx0l8ZYqDHO0fIDDEB9QrNDTlQrU1lZLh6qaoEFMx6ebjTqxsUIF1vKZrXJw3hb6GnEpN6kWnRou24J67ED5Cy93uuWDq9V2azfJsIIrVWqGvumBlKRBr/Hklyq0iDg2lde7KXKGgxcEND0dxmkQ4RBVnSKNi1hVgCmYyx7V8okos/yRInzkez6UHhgNzkrzDRpufaAv457x4PzqF1C9mMjv+uRdkAaEV/tHaSqxLD/jpXlzhFL4D9NxJvxcJEfSjDPADo+NwodpntbfCEBJekBY+ZRFexMQHyXhvFMnM7UqV8USfftuornhSZcit1tVe2mumPzUvpfdEejKdx/QTzvhERlxz2+m01mBqFJnhtld2gYhZ3UtFsuDk1R1IHC8NgzyiAHpfnocpfAxr2UdiOasjQVFLbyO/EI6aXWmNutDqeobGZDBjEitVadiZE+bdDtZLpn5S1TON6yQT8b+eFvr6KC3KCyJJ+Gcx/KsB/CBIC2i+hDKR5DwWL56DlsCzqKBtt5hpMIJbfuQM++WYEwRCmA4aQXYP8XVydGOnx4ObnIOAfntn1HEDrQMAl0Rw+1YlsUJkEDhORZ3dzKqRI+gn50Yhi+ktJ1I+x/cSj7qST6y3Qup+VFtV84N3cp515yy9zQocPH4/vxNNfd0cydQDDW7a2vm6W753CybOZwpH+HrGsH34cko6f7zmTvBmEVdmnDCQad29nAf63Rtjn3ohq8lXy7lbI6/p39QotfWXWcHMFp3rdgyXTnFJa3/8LMG530cl7DlcyVeA6/gx5IpMAlM+iPj1HQp94vyf43bTttvyZWMkH07xWK9XsOEy2lYf7uviycjQAagBW5C58L6kvKg+8Gr0YZK6G06yGDnlZemJox9m9Kk2M0q72wzQsJvvvfN8Mbgag+2W+h24dCQCkf29IOoqAB0eW5vEPrf3mwMLHpiqIhu8lbPk4Q5R91ii5hHWvzo0V6QmTXeciZ4JD64Ma7vYssSgN2a/VR6hrmL3Io3YM/O0D7BihhPpCneuY3A0FA== X-Microsoft-Antispam-Message-Info: 8M7tiFgS3BrOYdiS6sv3hFEHT6ZzHGbAV2JVatJW4j8WUQhPwxqWqfgZ7R02UqWoI+pbDKplB7H93i7TWulD/tBSu7DdFxfnR5w43p6lVLxJ3y5c2r41xeCpb1BERSTRSAXU5KygbhZSyZBWIxmgmAxhCBKTf34OMA0hFfeRO7bGr4Eiu1UfigqEogpFVA0xS727SHa8PdRWj3Em3OEEh1Io1O2PFWcSpypUrstMW/RZwFe4dKS2mTeKr1XYDh2pnWmg2Hp4ytFAnhMLJuz7BcRXSDEsj11m054VtVQwW7iiOZtGb1RBCtSTp5MwkBMyAUoOXRYf+2hBVnKntjbJlzEjd94V51XCxcOjDBl2ySA= X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 6:cE619fjASlonVUDWVqfymC3L/rLoCt8vGWK5FcbTxqE/5LTM3L9xz6zgiZExPPAm1BWnHFFl9FbEgGXIk/+AdkWf3w9g8KQjA/lJEaObcfFFsVzGNIAG4jikZX+KQn+Lg0t+Pb8kHrRBrNzekpsO+PHKmz5uXsRUq4sG99yFs4QAljNSqEIUK5pvQSa3rPB2oCmTlswoZLqsXxjaxszKKSjsFWa2QZaVJGFeV1SuHLGWrAiTn8Tf/mh6LJK/8YiWzrjPSBWtRE4m2RbWuw+mZIWg6kHrESMIMi81+QpWC08iHCPmgto17/R6+IZOIRVSFSO473Mv4MFKAvM7RPwoKW7LfCm3UmnFwQcMHrnGP288M6yhAP4/EPKkdN9/x+iSCf1jpPjcPL0ZHVCLZE9S8by9JjKY5Yre4ocnPuYBm1Z+0WGXy2wScU/EDjwd7UFQsYH6maZg0aInINlNKfVfGA==; 5:8moIZxN79pvdT43xL56sZ7Os9RUTveLQg59yUVWPhIB62jC98gS3y5omnj2E4Pcrk3OkrAr4H5F7dUp1jlqLRhKC2wnWPDNTljsdxs5uhmuTSjL3Bef0WQgCjTUeoxDEk5tyuw8TDYJosQywZuIy/QOqJCJk4VIDnJRrNaw+x/s=; 7:tnUd/baNnKTGuH2Fga7/9mnyRIi7sTUuQj6aztU2Erl2awvH/nWJVKVwop2qDdXPElvJnh4TIn9ydsygLLxIOGTSYqPfErp+kxSEZlSi0Be0sTX1VmWIb9sUpARYmKnGMblR07oRAyw39n3ZCVQy7cEMN5HQgqkGGgAv+4J6hCHveDkfJ93Ue3lobZgdVJ+ensGBwtx1DXqZFgMWcTJ84/ETaccNkVvtamzfl6UcpLbNTrEKAUXbP9NZc+TmPKRh SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2018 14:17:58.4849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41cd3443-aab8-44d0-270f-08d5f17041fe X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1625 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180724_071813_177140_697A68FB X-CRM114-Status: GOOD ( 15.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-fpga@vger.kernel.org, Appana Durga Kedareswara rao , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Inorder to debug issues with fpga's users would like to read the fpga configuration information. This patch adds readback support for fpga configuration data in the framework through debugfs interface. Usage: cat /sys/kernel/debug/fpga/fpga0/image Signed-off-by: Appana Durga Kedareswara rao --- Changes for v3: --> None. Changes for v2: --> Fixed debug attribute path and name as suggested by Alan --> Add config entry for DEBUG as suggested by Alan --> Fixed trival coding style issues. drivers/fpga/Kconfig | 7 +++++ drivers/fpga/fpga-mgr.c | 68 +++++++++++++++++++++++++++++++++++++++++++ include/linux/fpga/fpga-mgr.h | 5 ++++ 3 files changed, 80 insertions(+) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 53d3f55..838ad4e 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -11,6 +11,13 @@ menuconfig FPGA if FPGA +config FPGA_MGR_DEBUG_FS + tristate "FPGA Debug fs" + select DEBUG_FS + help + FPGA manager debug provides support for reading fpga configuration + information. + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA || COMPILE_TEST diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 9939d2c..4bea860 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -484,6 +484,48 @@ void fpga_mgr_put(struct fpga_manager *mgr) } EXPORT_SYMBOL_GPL(fpga_mgr_put); +#ifdef CONFIG_FPGA_MGR_DEBUG_FS +#include + +static int fpga_mgr_read(struct seq_file *s, void *data) +{ + struct fpga_manager *mgr = (struct fpga_manager *)s->private; + int ret = 0; + + if (!mgr->mops->read) + return -ENOENT; + + if (!mutex_trylock(&mgr->ref_mutex)) + return -EBUSY; + + if (mgr->state != FPGA_MGR_STATE_OPERATING) { + ret = -EPERM; + goto err_unlock; + } + + /* Read the FPGA configuration data from the fabric */ + ret = mgr->mops->read(mgr, s); + if (ret) + dev_err(&mgr->dev, "Error while reading configuration data from FPGA\n"); + +err_unlock: + mutex_unlock(&mgr->ref_mutex); + + return ret; +} + +static int fpga_mgr_read_open(struct inode *inode, struct file *file) +{ + return single_open(file, fpga_mgr_read, inode->i_private); +} + +static const struct file_operations fpga_mgr_ops_image = { + .owner = THIS_MODULE, + .open = fpga_mgr_read_open, + .read = seq_read, +}; +#endif + /** * fpga_mgr_lock - Lock FPGA manager for exclusive use * @mgr: fpga manager @@ -581,6 +623,29 @@ int fpga_mgr_register(struct device *dev, const char *name, if (ret) goto error_device; +#ifdef CONFIG_FPGA_MGR_DEBUG_FS + struct dentry *d, *parent; + + mgr->dir = debugfs_create_dir("fpga", NULL); + if (!mgr->dir) + goto error_device; + + parent = mgr->dir; + d = debugfs_create_dir(mgr->dev.kobj.name, parent); + if (!d) { + debugfs_remove_recursive(parent); + goto error_device; + } + + parent = d; + d = debugfs_create_file("image", 0644, parent, mgr, + &fpga_mgr_ops_image); + if (!d) { + debugfs_remove_recursive(mgr->dir); + goto error_device; + } +#endif + dev_info(&mgr->dev, "%s registered\n", mgr->name); return 0; @@ -604,6 +669,9 @@ void fpga_mgr_unregister(struct device *dev) dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name); +#ifdef CONFIG_FPGA_MGR_DEBUG_FS + debugfs_remove_recursive(mgr->dir); +#endif /* * If the low level driver provides a method for putting fpga into * a desired state upon unregister, do it. diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 3c6de23..e9e17a9 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -114,6 +114,7 @@ struct fpga_image_info { * @write: write count bytes of configuration data to the FPGA * @write_sg: write the scatter list of configuration data to the FPGA * @write_complete: set FPGA to operating state after writing is done + * @read: optional: read FPGA configuration information * @fpga_remove: optional: Set FPGA into a specific state during driver remove * @groups: optional attribute groups. * @@ -131,6 +132,7 @@ struct fpga_manager_ops { int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); + int (*read)(struct fpga_manager *mgr, struct seq_file *s); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; }; @@ -151,6 +153,9 @@ struct fpga_manager { enum fpga_mgr_states state; const struct fpga_manager_ops *mops; void *priv; +#ifdef CONFIG_FPGA_MGR_DEBUG_FS + struct dentry *dir; +#endif }; #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) From patchwork Tue Jul 24 14:17:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 10542229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A02A14BC for ; Tue, 24 Jul 2018 14:18:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 051EA28B1E for ; Tue, 24 Jul 2018 14:18:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 02ECE28B1D; Tue, 24 Jul 2018 14:18:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 17D2C28AF3 for ; Tue, 24 Jul 2018 14:18:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5i4FCb9B/FJkx1wIfPPkOl8Zbx8cPEjOHo8aG2PFQAA=; b=k5kcE2kkIPPZ7v T+YJW60XPXl6R2u7nv0hwz3tojud9w3gEi9QF6zI69qKKin0B7Jx2IQk2SNORA/rWVdCRIdCgjcBZ 2or3B/vicLLs9pM2GbilykHPFnwoOWFJrf6CtPfKU5cxD7s4XJ3FOyFkcoIZugi4tg+I37W87cHmT FcWazMRnbUZU2OkjRfIlS3wHr5+PCWgLzEmidfBcoDYCJQS2gtyIAoMXUY75ZHeqWtkIDs+Cr6k3S bTGMiNCHo9VozAiPTQORLFjGuzG8DbOQJGpPNFth4FG7KjtYv5tSPLa14XPT0vzdciHn0K8oPN0Wl Msq7xJL0ex0KqUU4rAMQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fhy8y-0006Sv-I6; Tue, 24 Jul 2018 14:18:28 +0000 Received: from mail-co1nam05on0600.outbound.protection.outlook.com ([2a01:111:f400:fe50::600] helo=NAM05-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fhy8l-0006CW-69 for linux-arm-kernel@lists.infradead.org; Tue, 24 Jul 2018 14:18:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=87XOzAnQQ35a0u3igUcrN7WUGDyliaz6GnBVqOhBesQ=; b=Xch0YCdEjYywBz2LLw7+Ai/krlk93896mGVHYb7r3LvuUvmWTvEgPDFkB6zQA40+KxZaqC0ip6fR9aYBNIYgaVlvdY1Yf3IeA4ZOdOOOwtxMy1lJU4/F75VO0vLXIm2E5AWgffz9P3MC6qBWvpD8smISY6ITFwEHAKVbdo7EYRw= Received: from BLUPR0201CA0023.namprd02.prod.outlook.com (2a01:111:e400:52e7::33) by CY1PR02MB1625.namprd02.prod.outlook.com (2a01:111:e400:5299::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.973.21; Tue, 24 Jul 2018 14:17:59 +0000 Received: from SN1NAM02FT033.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::207) by BLUPR0201CA0023.outlook.office365.com (2a01:111:e400:52e7::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.973.16 via Frontend Transport; Tue, 24 Jul 2018 14:17:58 +0000 Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT033.mail.protection.outlook.com (10.152.72.133) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.995.12 via Frontend Transport; Tue, 24 Jul 2018 14:17:58 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1fhy8U-00022i-0Q; Tue, 24 Jul 2018 07:17:58 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fhy8O-0004O5-Vu; Tue, 24 Jul 2018 07:17:53 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w6OEHldc004205; Tue, 24 Jul 2018 07:17:47 -0700 Received: from [172.23.37.94] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fhy8I-0004NT-QQ; Tue, 24 Jul 2018 07:17:47 -0700 From: Appana Durga Kedareswara rao To: , , , Subject: [PATCH v3 2/2] fpga: zynq-fpga: Add support for readback Date: Tue, 24 Jul 2018 19:47:38 +0530 Message-ID: <1532441858-13507-2-git-send-email-appana.durga.rao@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532441858-13507-1-git-send-email-appana.durga.rao@xilinx.com> References: <1532441858-13507-1-git-send-email-appana.durga.rao@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(396003)(39860400002)(136003)(346002)(376002)(2980300002)(438002)(199004)(189003)(186003)(356003)(446003)(11346002)(6346003)(7696005)(106002)(8676002)(26005)(336012)(6666003)(51416003)(478600001)(81166006)(81156014)(47776003)(2906002)(8936002)(76176011)(54906003)(36386004)(77096007)(110136005)(316002)(486006)(476003)(2616005)(16586007)(6636002)(2201001)(426003)(126002)(14444005)(305945005)(63266004)(50226002)(48376002)(106466001)(5660300001)(36756003)(50466002)(9786002)(4326008)(107886003)(107986001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR02MB1625; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; X-Microsoft-Exchange-Diagnostics: 1; SN1NAM02FT033; 1:EuRl/WZg7PqOj3NbfOIg8qgFbwOHJlshTU8XDkp70ET5W0i4bWMtFKMiGJG99nrmx8781nzeSOc5843Avn3lcd7z0R01mbr0WTUSxLZeoTgKMY6dxAQ6Qz5iaDTMYi2G MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 696e7795-9e2e-49eb-a05e-08d5f17041fb X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600073)(711020)(4608076)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060); SRVR:CY1PR02MB1625; X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 3:Fp3R8mVv5aH3xaXdn3FzhlRjo51oYHtEwqT6IIQ1tsy2nVoAyZkcmPBBVY2vAGP2Aqk2/ynRibC1PQRzNdsbdx7Yw8KRWSK81YEn7m39dJnXlIswq9UZ4i2DIKN0pvz6CoM1tDVKQghAuUvMh2nWCkI/RmkUeD8T4yTj4mreoH63nPdrRN1PdF23vNKq3K2NZcGCdYgBxaFBoqmKomuW8BBvqaRM4TOdQ39Suf6udrKrPblF62DIq3ZAWp1LCyJuFxlHnGnisn8q1W87+UGRWTgLTlt73bu13AesBhWJ1OJM2/zRwELLmIYMGbUUk/t/ia9Y9Z1h4eu9NMmySW8ObcBgECEkBLDu1GC25mXfWYA=; 25:PNtR1nsvgj9dXHdWBp1Pvo/erK7Kpdk474ejdB08TOLIyU5DQu2WLC0rycgkLBc/5kmb0sohlYTVKkUj02kVJz3JL07PYc76AQbJ6PRnxG0S8A2gEs7JlUUEd5xqk9iPUryb+eyvVxr2uxe8Onb7PcTjhszWXsfVFFbdi88Gw6138bISv1XFvI1VhH8Ml9/t6YzPSfMY/K2rp/RXAcfIxu/WXBaN33dhyy1E/v2toFL2u0fpGgsbwBvkRnFWp+GldkgHAtK7zyRkk1EJkZGBEYbIHQQDdgjhk2dnU3WHdJZteyPIfLQ/STI/ysEqUe1Oi9ofmOx8lcv/QJETNmq6FA== X-MS-TrafficTypeDiagnostic: CY1PR02MB1625: X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 31:L1RKEWuJM3xvPCWh6+ac+uj09RqzzXABv6gUtYE76FWQu8kZI7XCjdAFSC0CBroQ0BdTROAv24xnMRlkVtYG7P9eqLXR+mvuQiYdjReUD40/vlXxAP5sz2PJyXjBFaNEgu4NJqk+KC0Z5JvO5Zuc61h1IhssPnyhEqQVlS2oRzhBn6Xx3yyr9gBKQfq3v+B+9jF0FPjy8MF19Fg0Ns6H4X1FTBU6fKClYUK/hHMnCYc=; 20:xBAlotMhbJSkOFNra0gWWrBTVNz16+jzx27ZmbediLEhKy60yswQ7a60o7jfjv02eBE7QKbERm4/Uv6eckb7HC2rsFtrKl4OWh8VIbUD9b7/yNiDK7mVufzyzYFxUfPCrxekDRNESjH6ymEtcLpvzWfsxuTCK6un4CAqyHMtRXy/vslTf09neO+mrl0pfIY/12Hq5ltfsy3Y2g0epzf4ZAIWoFQr18D6jjIeW85XvMw0o/FmTH2aUQovL0TwOVwo41N/tbqK48wH11wtzbkyNy3wciGRdyyEZIG3hgJFJ/kuK8XmJq/cUd9vyGMKkJi+8LnrS2A+p9mYS6VyIaWt3a6maZYjXvLTa2g6822+L0jjQ+if1QfCxcWS33qy1v6VG3iyNUqmjDbbZ/sBsT2O7D5hcMISTGcay9GRh9LDsCD0aMOMQynVdHaB3tRNZz4SczrgnZqMmZ98zVmPafK1gwIUBrP959AQ6qxbvyXwzszOnZeJOQgU413uTWYqXwvJ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231311)(944501410)(52105095)(93006095)(93004095)(10201501046)(3002001)(6055026)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(6072148)(201708071742011)(7699016); SRVR:CY1PR02MB1625; BCL:0; PCL:0; RULEID:; SRVR:CY1PR02MB1625; X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 4:Ga/jd1T/iZCkOyBEbkwFubuZHwrysG7B6FvS8uOTlytCNOmazksznFpr+ko+W8Veam9qpl+ABd0YZNLSDKrZItO7JH5d2HVZvSef+F9knEjXbu14kXxSNiE5f6MZru+9xmhFBp+T3ls5/Szqw5vLKYwD3G5f4qjdfENURMqzZcd/5IhpODD93DYr3sFmjodxt2QBux7xoLTRTJ8WfLzB/0U2c+AEhSV172/Bv/9CJ4hReyyfBMx13dcbTi7Rm8WPY1VRoDUjzHdRcFJzuH9fdAhc37PQptJ2JvUeZWGFMvWbnsgLpIw3cnfQjr4EoVfB X-Forefront-PRVS: 0743E8D0A6 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR02MB1625; 23:2TyM82PZWDt4asx9RFFKqEIQC7F6otCaCB+cgSX8R?= IRVly4ePrs38ws1cVVmkNfu0AjZhPlbPhySyLapKpN4RGergiZXsczUUpTxi7mnMtMiPefTNwAUEC6dWfZy3FkUbyS0WsKmvTZmCtaPWkUFewN/QMzV3/N4HXW52Z5bdbgDkLlzPxhBs+N+0onnlQdIr9SGhLD46KQ4Vg9iaPCnSrRTmy1X45OP75YTajKC37Ttt0Za5Wr1/KqpbB2qDKja4YkRUbxhbKLu2rIOMr9HgAEtmhlLUXi5pgKRq93xGuODWZUhso7ot1Z69sn6vPot25wOY0724JF5QoOYqwsCShs4HGuCp67Yj33KiVsX7mq7uWPQDfmRvP+T1b8r/5xE9FJYGsHo03EhmsBqt9STqvowHETYQKTrvruEQeZcB7029oaC7uPYfrszLsLzQQvTuSgXhvB99PKfm7FmVjshDfwsYZ6xB86NbPFSDDupqRnpoBW+6Qj/3kZGMd1jbP9hmrVcZ5d28gW+IKOhOkAb01WJZNFoSlu0hyKL/f7123tYlitCRPKF/4wbJAA93UJBzYjjGSX+wAcKAbXLMPLZ5Y5XDnaqX8W+6B2POoVvrWQuC0Ff1DZkY3bWYtNbonzsaTBnHxjGn7E7qdiBy+RPVkD6sfLC3Vf4WlqfvMSi2GtEaC298pqQ7L/fAaga/asvXaQ6RQZJnG9tgpVmmgIUA1rUv6/02UfW2kR0U6y0lQ+1dUfHCIrYsRsALG1G4szLOT1Qozctnmif4REWDohIgd0b68uaMB52aZ056yORMuudLQ+2PSczZ8EgRzWzxVNX+bye+XEbJ/0Q1MD87o3E4A7DVfmnJEvcPn8HyTvUdN/pqVHxP3Lh6QqURGHvaE3TjtrBFmSJ3tWllBXe949nR82n5KChXEOHyYBTd3XwUlq02h/KU5ULVpUxQ7QOC+uHh8uVI1ZrUddtao25AQr/Fb2vUxj8/WmczAsDWxpVQdX0vazEOlDeKrvqIv0zzxFRHC0QMC3hA5EfvHd1ik/LgoWqg4SZKPF+qdQJaaxonaw1kpHDli5UCIGts+5hv2EcVkN0L00a/l87H/rNIGGj9Oo/XgwJaqW81c+kalgRsLMKq+/3ZfmBkGxJnfpaHDkb2FW3PWjw+d7y2fBa9aq07jdTohNd1wv/z6QeCECdnxE= X-Microsoft-Antispam-Message-Info: V4A5WnAfgqmCUCwZqHWD7g4xNoJPq2iH2/XeJXL8dkchHkpxvSZS0xWWDXkDzgfGgw38Xq5pB56ugkpEksm0dks8Mkzj/FC8cM1z6TMC8SVS6+L9NdwPEI1NzHSUT8QG/jF8YupiNi0Xv8p37kw3dOU/aLkguNlp+OQFYmTtSHt3vqXoEi9mtRZt+ItMeNLGYRR8QmaKt3fGxjXYykctYKn+qwuM4YPKKo9ulqwg3Nl9wOYpEO7MJcTqpcb3ptqYWMnSa8mftoJibvZgeFhMZ/Ja3rGerD8vs9wzd8ugCVUJOHGVmEOvqVJL+ocuqPTWwORCQD3M/GLdvxBe/WA+Pxcg8T68qOLJQpsQF9y+AAU= X-Microsoft-Exchange-Diagnostics: 1; CY1PR02MB1625; 6:ESJzKnXseV/7H5td6Q1NGoTt2cOVM9scl7mxm6BUsM1LWHJR49dcgn39sBtKv9XesCc+x2PC812ObryczXwZ5id3Z82C8urGu5kIkY67DPkYDPB5xWrGgVnL/Po+MfwanEyElFZPtwCqSmfM4qTZ4SapwHxCFLS1SjCV3grCXSscHzACB2sueSzhCHIZkvVknafTD+8DDpG7jW7IK8YnqkrK/+8wHQFpDQ1JA9qcfiSC31hsG3XMU4Fno7Vbex7GrsBpyPu+gEw68Bp1WGTGqr35suD5jOBPgwFPnBn/zMmc/sr4jtH35fQmJNmLprpCz6+4+ZC+L24+vqmnuCnwpEfFGxV0Wlfkx1P//UVNkPnguerZ/8vuJ10Cm1VGUz3Udm+Xm5DPjhCXztT6Fh08aB3Zg6QTBGzseVSFqLnJzg7+w2GMgeP54xm4awWMmyvDwz0WwTrUZY/j2aAol0+vIg==; 5:jB+Jp2G++MtV9qieJsvcYRyzV5OswDIO1WQDHxxFnyn+YIoEwHj3q3foC/6bjwK9qZlfPsqK8SsBmdzXQ2Ycn6g/cPjeRH1VYpAG7XS19gW72ebqs1T2aPxpzbB5LXGD+MKz43sPWMlNfrZNX8Jix5YeokRAdLcIEx1xhgscFmU=; 7:XodnHNAXPsBvSbvIviwIgXLqlyvjYHXOaABfG2EHvA6Fto5IkSeMfiKS45DjBW95IU6o0A271ZgBRSf2iuKOWWCNoKCYXsEojWJED5NFs6EqeeIp1+sW8oz94Zbd9SJI+tSVaVqaYbxrqNzQy5MUOCECubz31Vs9w/c/ulurP4knYXgbVrreyzui+OFm+E5i9I2157pLf1cqVjFQaC1NDCML+RYlK6X/fDs0yJd+BV3ChWqW5T0BnngNzmVKFMqH SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2018 14:17:58.5621 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 696e7795-9e2e-49eb-a05e-08d5f17041fb X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1625 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180724_071815_388556_44126C70 X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-fpga@vger.kernel.org, Appana Durga Kedareswara rao , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch does the below --> Adds support for readback of pl configuration data --> Adds support for readback of pl configuration registers Usage: Readback of PL configuration registers cat /sys/kernel/debug/fpga/fpga0/image Readback of PL configuration data echo 1 > /sys/module/zynqmp_fpga/parameters/readback_type cat /sys/kernel/debug/fpga/fpga0/image Signed-off-by: Appana Durga Kedareswara rao --- Changes for v3: --> Added support for pl configuration data readback --> Improved the pl configuration register readback logic. Changes for v2: --> Removed locks from the read_ops as lock handling is done in the framework. drivers/fpga/zynq-fpga.c | 400 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 400 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 70b15b3..5f1a1aa 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -31,6 +31,7 @@ #include #include #include +#include /* Offsets into SLCR regmap */ @@ -127,6 +128,72 @@ /* Disable global resets */ #define FPGA_RST_NONE_MASK 0x0 +static bool readback_type; +module_param(readback_type, bool, 0644); +MODULE_PARM_DESC(readback_type, + "readback_type 0-configuration register read " + "1- configuration data read (default: 0)"); + +/** + * struct zynq_configreg - Configuration register offsets + * @reg: Name of the configuration register. + * @offset: Register offset. + */ +struct zynq_configreg { + char *reg; + u32 offset; +}; + +static struct zynq_configreg cfgreg[] = { + {.reg = "CRC", .offset = 0}, + {.reg = "FAR", .offset = 1}, + {.reg = "FDRI", .offset = 2}, + {.reg = "FDRO", .offset = 3}, + {.reg = "CMD", .offset = 4}, + {.reg = "CTRL0", .offset = 5}, + {.reg = "MASK", .offset = 6}, + {.reg = "STAT", .offset = 7}, + {.reg = "LOUT", .offset = 8}, + {.reg = "COR0", .offset = 9}, + {.reg = "MFWR", .offset = 10}, + {.reg = "CBC", .offset = 11}, + {.reg = "IDCODE", .offset = 12}, + {.reg = "AXSS", .offset = 13}, + {.reg = "COR1", .offset = 14}, + {.reg = "WBSTR", .offset = 16}, + {.reg = "TIMER", .offset = 17}, + {.reg = "BOOTSTS", .offset = 22}, + {.reg = "CTRL1", .offset = 24}, + {} +}; + +/* Masks for Configuration registers */ +#define FAR_ADDR_MASK 0x00000000 +#define RCFG_CMD_MASK 0x00000004 +#define START_CMD_MASK 0x00000005 +#define RCRC_CMD_MASK 0x00000007 +#define SHUTDOWN_CMD_MASK 0x0000000B +#define DESYNC_WORD_MASK 0x0000000D +#define BUSWIDTH_SYNCWORD_MASK 0x000000BB +#define NOOP_WORD_MASK 0x20000000 +#define BUSWIDTH_DETECT_MASK 0x11220044 +#define SYNC_WORD_MASK 0xAA995566 +#define DUMMY_WORD_MASK 0xFFFFFFFF + +#define TYPE_HDR_SHIFT 29 +#define TYPE_REG_SHIFT 13 +#define TYPE_OP_SHIFT 27 +#define TYPE_OPCODE_NOOP 0 +#define TYPE_OPCODE_READ 1 +#define TYPE_OPCODE_WRITE 2 +#define TYPE_FAR_OFFSET 1 +#define TYPE_FDRO_OFFSET 3 +#define TYPE_CMD_OFFSET 4 + +#define READ_DMA_SIZE 0x200 +#define DUMMY_FRAMES_SIZE 0x28 +#define SLCR_PCAP_FREQ 10000000 + struct zynq_fpga_priv { int irq; struct clk *clk; @@ -140,6 +207,7 @@ struct zynq_fpga_priv { struct scatterlist *cur_sg; struct completion dma_done; + u32 size; }; static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset, @@ -164,6 +232,27 @@ static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable) zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable); } +static void zynq_fpga_dma_xfer(struct zynq_fpga_priv *priv, u32 srcaddr, + u32 srclen, u32 dstaddr, u32 dstlen) +{ + zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, srcaddr); + zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, dstaddr); + zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, srclen); + zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, dstlen); +} + +static int zynq_fpga_wait_fordone(struct zynq_fpga_priv *priv) +{ + u32 status; + int ret; + + ret = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, status, + status & IXR_D_P_DONE_MASK, + INIT_POLL_DELAY, + INIT_POLL_TIMEOUT); + return ret; +} + /* Must be called with dma_lock held */ static void zynq_step_dma(struct zynq_fpga_priv *priv) { @@ -192,6 +281,7 @@ static void zynq_step_dma(struct zynq_fpga_priv *priv) priv->dma_elm++; } + priv->size += len; zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, addr); zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, DMA_INVALID_ADDRESS); zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, len / 4); @@ -401,6 +491,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt) int i; priv = mgr->priv; + priv->size = 0; /* The hardware can only DMA multiples of 4 bytes, and it requires the * starting addresses to be aligned to 64 bits (UG585 pg 212). @@ -546,12 +637,321 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) return FPGA_MGR_STATE_UNKNOWN; } +static int zynq_type1_pkt(u8 reg, u8 opcode, u16 size) +{ + /* + * Type 1 Packet Header Format + * The header section is always a 32-bit word. + * + * HeaderType | Opcode | Register Address | Reserved | Word Count + * [31:29] [28:27] [26:13] [12:11] [10:0] + * -------------------------------------------------------------- + * 001 xx RRRRRRRRRxxxxx RR xxxxxxxxxxx + * + * @R: means the bit is not used and reserved for future use. + * The reserved bits should be written as 0s. + * + * Generating the Type 1 packet header which involves sifting of Type1 + * Header Mask, Register value and the OpCode which is 01 in this case + * as only read operation is to be carried out and then performing OR + * operation with the Word Length. + */ + return (((1 << TYPE_HDR_SHIFT) | + (reg << TYPE_REG_SHIFT) | + (opcode << TYPE_OP_SHIFT)) | size); + +} + +/****************************************************************************/ +/** + * + * Generates a Type 2 packet header that reads back the requested Configuration + * register. + * + * @param OpCode is the read/write operation code. + * @param Size is the size of the word to be read. + * + * @return Type 2 packet header to read the specified register + * + * @note None. + * + *****************************************************************************/ +static int zynq_type2_pkt(u8 OpCode, u32 Size) +{ + /* + * Type 2 Packet Header Format + * The header section is always a 32-bit word. + * + * HeaderType | Opcode | Word Count + * [31:29] [28:27] [26:0] + * -------------------------------------------------------------- + * 010 xx xxxxxxxxxxxxx + * + * @R: means the bit is not used and reserved for future use. + * The reserved bits should be written as 0s. + * + * Generating the Type 2 packet header which involves sifting of Type 2 + * Header Mask, OpCode and then performing OR + * operation with the Word Length. + */ + return (((2 << TYPE_HDR_SHIFT) | + (OpCode << TYPE_OP_SHIFT)) | Size); +} + +static int zynq_fpga_read_cfgdata(struct fpga_manager *mgr, + struct seq_file *s) +{ + struct zynq_fpga_priv *priv; + int ret = 0, i, cmdindex, clk_rate; + unsigned int *buf; + dma_addr_t dma_addr; + u32 intr_status, status; + size_t size; + + priv = mgr->priv; + size = priv->size + READ_DMA_SIZE + DUMMY_FRAMES_SIZE; + buf = dma_zalloc_coherent(mgr->dev.parent, size, + &dma_addr, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + seq_puts(s, "zynq FPGA Configuration data contents are\n"); + + /* + * There is no h/w flow control for pcap read + * to prevent the FIFO from over flowing, reduce + * the PCAP operating frequency. + */ + clk_rate = clk_get_rate(priv->clk); + ret = clk_set_rate(priv->clk, SLCR_PCAP_FREQ); + if (ret) { + dev_err(&mgr->dev, "Unable to reduce the PCAP freq\n"); + goto free_dmabuf; + } + + ret = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status, + status & STATUS_PCFG_INIT_MASK, + INIT_POLL_DELAY, + INIT_POLL_TIMEOUT); + if (ret) { + dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n"); + goto restore_pcap_clk; + } + + cmdindex = 0; + buf[cmdindex++] = DUMMY_WORD_MASK; + buf[cmdindex++] = BUSWIDTH_SYNCWORD_MASK; + buf[cmdindex++] = BUSWIDTH_DETECT_MASK; + buf[cmdindex++] = DUMMY_WORD_MASK; + buf[cmdindex++] = SYNC_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, TYPE_OPCODE_WRITE, + 1); + buf[cmdindex++] = SHUTDOWN_CMD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, TYPE_OPCODE_WRITE, + 1); + buf[cmdindex++] = RCRC_CMD_MASK; + for (i = 0; i < 6; i++) + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, TYPE_OPCODE_WRITE, + 1); + buf[cmdindex++] = RCFG_CMD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_FAR_OFFSET, TYPE_OPCODE_WRITE, + 1); + buf[cmdindex++] = FAR_ADDR_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_FDRO_OFFSET, TYPE_OPCODE_READ, + 0); + buf[cmdindex++] = zynq_type2_pkt(TYPE_OPCODE_READ, priv->size/4); + for (i = 0; i < 32; i++) + buf[cmdindex++] = NOOP_WORD_MASK; + + intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); + zynq_fpga_write(priv, INT_STS_OFFSET, intr_status); + + /* Write to PCAP */ + zynq_fpga_dma_xfer(priv, dma_addr, cmdindex, + DMA_INVALID_ADDRESS, 0); + ret = zynq_fpga_wait_fordone(priv); + if (ret) { + dev_err(&mgr->dev, "SRCDMA: Timeout waiting for D_P_DONE\n"); + goto restore_pcap_clk; + } + intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); + zynq_fpga_write(priv, INT_STS_OFFSET, intr_status); + + /* READ From PACP */ + zynq_fpga_dma_xfer(priv, DMA_INVALID_ADDRESS, 0, + dma_addr + READ_DMA_SIZE, priv->size/4); + ret = zynq_fpga_wait_fordone(priv); + if (ret) { + dev_err(&mgr->dev, "DSTDMA: Timeout waiting for D_P_DONE\n"); + goto restore_pcap_clk; + } + intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); + zynq_fpga_write(priv, INT_STS_OFFSET, intr_status); + + /* Write to PCAP */ + cmdindex = 0; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, + TYPE_OPCODE_WRITE, 1); + buf[cmdindex++] = START_CMD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, + TYPE_OPCODE_WRITE, 1); + buf[cmdindex++] = RCRC_CMD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, + TYPE_OPCODE_WRITE, 1); + buf[cmdindex++] = DESYNC_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + + zynq_fpga_dma_xfer(priv, dma_addr, cmdindex, + DMA_INVALID_ADDRESS, 0); + ret = zynq_fpga_wait_fordone(priv); + if (ret) { + dev_err(&mgr->dev, "SRCDMA1: Timeout waiting for D_P_DONE\n"); + goto restore_pcap_clk; + } + + seq_write(s, &buf[READ_DMA_SIZE/4], priv->size); + +restore_pcap_clk: + clk_set_rate(priv->clk, clk_rate); +free_dmabuf: + dma_free_coherent(mgr->dev.parent, size, buf, + dma_addr); + return ret; +} + +static int zynq_fpga_getconfigreg(struct fpga_manager *mgr, u8 reg, + dma_addr_t dma_addr, int *buf) +{ + struct zynq_fpga_priv *priv; + int ret = 0, cmdindex, src_dmaoffset; + u32 intr_status, status; + + priv = mgr->priv; + + src_dmaoffset = 0x8; + cmdindex = 2; + buf[cmdindex++] = DUMMY_WORD_MASK; + buf[cmdindex++] = BUSWIDTH_SYNCWORD_MASK; + buf[cmdindex++] = BUSWIDTH_DETECT_MASK; + buf[cmdindex++] = DUMMY_WORD_MASK; + buf[cmdindex++] = SYNC_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = zynq_type1_pkt(reg, TYPE_OPCODE_READ, 1); + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + + ret = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status, + status & STATUS_PCFG_INIT_MASK, + INIT_POLL_DELAY, + INIT_POLL_TIMEOUT); + if (ret) { + dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n"); + goto out; + } + + /* Write to PCAP */ + intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); + zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK); + + zynq_fpga_dma_xfer(priv, dma_addr + src_dmaoffset, cmdindex, + DMA_INVALID_ADDRESS, 0); + ret = zynq_fpga_wait_fordone(priv); + if (ret) { + dev_err(&mgr->dev, "SRCDMA: Timeout waiting for D_P_DONE\n"); + goto out; + } + zynq_fpga_set_irq(priv, intr_status); + + /* READ From PACP */ + zynq_fpga_dma_xfer(priv, DMA_INVALID_ADDRESS, 0, dma_addr, 1); + ret = zynq_fpga_wait_fordone(priv); + if (ret) { + dev_err(&mgr->dev, "DSTDMA: Timeout waiting for D_P_DONE\n"); + goto out; + } + + /* Write to PCAP */ + cmdindex = 2; + buf[cmdindex++] = zynq_type1_pkt(TYPE_CMD_OFFSET, + TYPE_OPCODE_WRITE, 1); + buf[cmdindex++] = DESYNC_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + buf[cmdindex++] = NOOP_WORD_MASK; + zynq_fpga_dma_xfer(priv, dma_addr + src_dmaoffset, cmdindex, + DMA_INVALID_ADDRESS, 0); + ret = zynq_fpga_wait_fordone(priv); + if (ret) + dev_err(&mgr->dev, "SRCDMA1: Timeout waiting for D_P_DONE\n"); +out: + return ret; +} + +static int zynq_fpga_read_cfgreg(struct fpga_manager *mgr, + struct seq_file *s) +{ + int ret = 0; + unsigned int *buf; + dma_addr_t dma_addr; + struct zynq_configreg *p = cfgreg; + + buf = dma_zalloc_coherent(mgr->dev.parent, READ_DMA_SIZE, + &dma_addr, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + seq_puts(s, "zynq FPGA Configuration register contents are\n"); + + while (p->reg) { + ret = zynq_fpga_getconfigreg(mgr, p->offset, dma_addr, buf); + if (ret) + goto free_dmabuf; + seq_printf(s, "%s --> \t %x \t\r\n", p->reg, buf[0]); + p++; + } + +free_dmabuf: + dma_free_coherent(mgr->dev.parent, READ_DMA_SIZE, buf, + dma_addr); + return ret; +} + +static int zynq_fpga_ops_read(struct fpga_manager *mgr, struct seq_file *s) +{ + struct zynq_fpga_priv *priv; + int ret; + + priv = mgr->priv; + + ret = clk_enable(priv->clk); + if (ret) + return ret; + + if (readback_type) + ret = zynq_fpga_read_cfgdata(mgr, s); + else + ret = zynq_fpga_read_cfgreg(mgr, s); + + clk_disable(priv->clk); + + return ret; +} + static const struct fpga_manager_ops zynq_fpga_ops = { .initial_header_size = 128, .state = zynq_fpga_ops_state, .write_init = zynq_fpga_ops_write_init, .write_sg = zynq_fpga_ops_write, .write_complete = zynq_fpga_ops_write_complete, + .read = zynq_fpga_ops_read, }; static int zynq_fpga_probe(struct platform_device *pdev)