From patchwork Wed Jan 15 00:13:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 13939698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88894C02183 for ; Wed, 15 Jan 2025 00:13:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 291B610E3BA; Wed, 15 Jan 2025 00:13:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m7BMgD8R"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id C7CAE10E3BA for ; Wed, 15 Jan 2025 00:13:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736900026; x=1768436026; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=XELd0H26p70FWGslkgds25MVjN+qHMsjNGPtdEnT2sU=; b=m7BMgD8RRMgpzc4WRNeMqrsGd//D/m8aWXgvPpDkBKsY/TfpIAQJSG9H hd+v7S8AfvaU51PuZ6y2VovjZ6ouEuxph3mmH+iOGRjSSsi2aLtOrVUve Sr7NCTFfO5XV+3OX/23ZMUrug1sx5wjQhJUjnIOmCS7GnXYy/Y3elAcJl 3ip5GJtYHZswAoN6Vqbh7vD7v2kBO00l6nY+ylG6HzjBVBpz6ZKclPzMd t6hGVMOGqP55ML2kYwPC06m/id1e0K9jyIRI1wK9kf3l3eFMNmQlfTQ2P mtjH/jBdD2zrCEuoX9HEAbZuft4QF9YAsviwqGjLBdImC/Eb1c4FZMVUh w==; X-CSE-ConnectionGUID: 8ROd5XDcS16pXodNZYbY/w== X-CSE-MsgGUID: vUA7TY6xRgK6t0t9dcqGug== X-IronPort-AV: E=McAfee;i="6700,10204,11315"; a="36430741" X-IronPort-AV: E=Sophos;i="6.12,315,1728975600"; d="scan'208";a="36430741" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2025 16:13:45 -0800 X-CSE-ConnectionGUID: iV1pwWIvSIu0IiWxb9pgbw== X-CSE-MsgGUID: CnRo+vn/S5m2do6Fjx9H+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="105831897" Received: from valcore-skull-1.fm.intel.com ([10.1.39.17]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2025 16:13:45 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Cc: Daniele Ceraolo Spurio , John Harrison , Matthew Brost , stable@vger.kernel.org Subject: [PATCH v2] drm/i915/guc: Debug print LRC state entries only if the context is pinned Date: Tue, 14 Jan 2025 16:13:34 -0800 Message-ID: <20250115001334.3875347-1-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After the context is unpinned the backing memory can also be unpinned, so any accesses via the lrc_reg_state pointer can end up in unmapped memory. To avoid that, make sure to only access that memory if the context is pinned when printing its info. v2: fix newline alignment Fixes: 28ff6520a34d ("drm/i915/guc: Update GuC debugfs to support new GuC") Signed-off-by: Daniele Ceraolo Spurio Cc: John Harrison Cc: Matthew Brost Cc: # v5.15+ Reviewed-by: John Harrison --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 20 +++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 12f1ba7ca9c1..158f78a0941f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -5519,12 +5519,20 @@ static inline void guc_log_context(struct drm_printer *p, { drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id); drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca); - drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", - ce->ring->head, - ce->lrc_reg_state[CTX_RING_HEAD]); - drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", - ce->ring->tail, - ce->lrc_reg_state[CTX_RING_TAIL]); + if (intel_context_pin_if_active(ce)) { + drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", + ce->ring->head, + ce->lrc_reg_state[CTX_RING_HEAD]); + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", + ce->ring->tail, + ce->lrc_reg_state[CTX_RING_TAIL]); + intel_context_unpin(ce); + } else { + drm_printf(p, "\t\tLRC Head: Internal %u, Memory not pinned\n", + ce->ring->head); + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory not pinned\n", + ce->ring->tail); + } drm_printf(p, "\t\tContext Pin Count: %u\n", atomic_read(&ce->pin_count)); drm_printf(p, "\t\tGuC ID Ref Count: %u\n",