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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-437c7499932sm13313065e9.7.2025.01.14.23.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 23:30:52 -0800 (PST) From: Christian Marangi To: Chaotian Jing , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Wenbin Mei , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, upstream@airoha.com Cc: Christian Marangi Subject: [PATCH 1/2] dt-bindings: mmc: mtk-sd: Add eMMC for AN7581 Date: Wed, 15 Jan 2025 08:29:50 +0100 Message-ID: <20250115073026.31552-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250115_073056_341477_3DFD1064 X-CRM114-Status: GOOD ( 12.90 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Document eMMC compatible for AN7581. This eMMC controller doesn't have regulator exposed to the system and have a single clock only for source clock and only default pintctrl. Rework the schema to permit these new requirements and make supply optional only for airoha,an7581-mmc compatible. Also provide an example for airoha,an7581-mmc. Signed-off-by: Christian Marangi --- This depends on patch merged in clk-next bfe257f9780d8f77045a7da6ec959ee0659d2f98 .../devicetree/bindings/mmc/mtk-sd.yaml | 64 +++++++++++++++++-- 1 file changed, 58 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index f86ebd81f5a5..6dad5455b369 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8183-mmc - mediatek,mt8196-mmc - mediatek,mt8516-mmc + - airoha,an7581-mmc - items: - const: mediatek,mt7623-mmc - const: mediatek,mt2701-mmc @@ -48,11 +49,11 @@ properties: clocks: description: Should contain phandle for the clock feeding the MMC controller. - minItems: 2 + minItems: 1 maxItems: 7 clock-names: - minItems: 2 + minItems: 1 maxItems: 7 interrupts: @@ -72,7 +73,7 @@ properties: Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this scenario. - minItems: 2 + minItems: 1 items: - const: default - const: state_uhs @@ -170,9 +171,6 @@ required: - clock-names - pinctrl-names - pinctrl-0 - - pinctrl-1 - - vmmc-supply - - vqmmc-supply allOf: - $ref: mmc-controller.yaml# @@ -335,6 +333,40 @@ allOf: - const: axi_cg - const: ahb_cg + - if: + properties: + compatible: + contains: + const: airoha,an7581-mmc + then: + properties: + clocks: + items: + - description: source clock + + clock-names: + items: + - const: source + + pinctrl-names: + items: + - const: default + else: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + pinctrl-names: + minItems: 2 + + required: + - pinctrl-1 + - vmmc-supply + - vqmmc-supply + unevaluatedProperties: false examples: @@ -389,5 +421,25 @@ examples: vqmmc-supply = <&mt6397_vgp3_reg>; mmc-pwrseq = <&wifi_pwrseq>; }; + - | + #include + #include + #include + mmc@1fa0e000 { + compatible = "airoha,an7581-mmc"; + reg = <0x1fa0e000 0x1000>, + <0x1fa0c000 0x60>; + clocks = <&scuclk EN7581_CLK_EMMC>; + clock-names = "source"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + bus-width = <4>; + max-frequency = <52000000>; + disable-wp; + cap-mmc-highspeed; + non-removable; + + }; ... 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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-437c7499932sm13313065e9.7.2025.01.14.23.30.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 23:30:53 -0800 (PST) From: Christian Marangi To: Chaotian Jing , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Wenbin Mei , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, upstream@airoha.com Cc: Christian Marangi Subject: [PATCH 2/2] mmc: mtk-sd: add support for AN7581 MMC Host Date: Wed, 15 Jan 2025 08:29:51 +0100 Message-ID: <20250115073026.31552-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250115073026.31552-1-ansuelsmth@gmail.com> References: <20250115073026.31552-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250114_233056_467539_6AFC6FB6 X-CRM114-Status: GOOD ( 19.55 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add support for AN7581 MMC Host. The MMC Host controller is based on mt7622 with the difference of not having regulator supply and state_uhs pins and hclk clock. Some minor fixes are applied to check if the state_uhs pins are defined and make hclk optional for the new airoha compatible. Signed-off-by: Christian Marangi --- drivers/mmc/host/mtk-sd.c | 55 ++++++++++++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index efb0d2d5716b..9d6868883c91 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -666,6 +666,20 @@ static const struct mtk_mmc_compatible mt8196_compat = { .support_new_rx = true, }; +static const struct mtk_mmc_compatible an7581_compat = { + .clk_div_bits = 12, + .recheck_sdio_irq = true, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .stop_dly_sel = 3, + .enhance_rx = true, + .support_64g = false, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, @@ -680,7 +694,7 @@ static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, - + { .compatible = "airoha,an7581-mmc", .data = &an7581_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -1600,6 +1614,10 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) struct msdc_host *host = mmc_priv(mmc); int ret; + /* Skip setting supply if not supported */ + if (!mmc->supply.vqmmc) + return 0; + if (!IS_ERR(mmc->supply.vqmmc)) { if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { @@ -1699,7 +1717,9 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); } - pinctrl_select_state(host->pinctrl, host->pins_uhs); + /* Skip setting uhs pins if not supported */ + if (host->pins_uhs) + pinctrl_select_state(host->pinctrl, host->pins_uhs); } else { dev_pm_clear_wake_irq(host->dev); } @@ -2036,6 +2056,10 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) msdc_set_buswidth(host, ios->bus_width); + /* Skip regulator if not supported */ + if (!mmc->supply.vmmc) + goto skip_regulator; + /* Suspend/Resume will do power off/on */ switch (ios->power_mode) { case MMC_POWER_UP: @@ -2071,6 +2095,7 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } +skip_regulator: if (host->mclk != ios->clock || host->timing != ios->timing) msdc_set_mclk(host, ios->timing, ios->clock); } @@ -2816,9 +2841,12 @@ static int msdc_of_clock_parse(struct platform_device *pdev, if (IS_ERR(host->src_clk)) return PTR_ERR(host->src_clk); - host->h_clk = devm_clk_get(&pdev->dev, "hclk"); - if (IS_ERR(host->h_clk)) - return PTR_ERR(host->h_clk); + /* AN7581 SoC doesn't have hclk */ + if (!device_is_compatible(&pdev->dev, "airoha,an7581-mmc")) { + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(host->h_clk)) + return PTR_ERR(host->h_clk); + } host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); if (IS_ERR(host->bus_clk)) @@ -2926,10 +2954,13 @@ static int msdc_drv_probe(struct platform_device *pdev) return PTR_ERR(host->pins_default); } - host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); - if (IS_ERR(host->pins_uhs)) { - dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); - return PTR_ERR(host->pins_uhs); + /* AN7581 doesn't have state_uhs pins */ + if (!device_is_compatible(&pdev->dev, "airoha,an7581-mmc")) { + host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); + if (IS_ERR(host->pins_uhs)) { + dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); + return PTR_ERR(host->pins_uhs); + } } /* Support for SDIO eint irq ? */ @@ -3010,6 +3041,12 @@ static int msdc_drv_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Cannot ungate clocks!\n"); goto release_clk; } + + /* AN7581 without regulator require tune to OCR values */ + if (device_is_compatible(&pdev->dev, "airoha,an7581-mmc") && + !mmc->ocr_avail) + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + msdc_init_hw(host); if (mmc->caps2 & MMC_CAP2_CQE) {