From patchwork Wed Jan 15 17:32:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13940689 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D76141AB50C; Wed, 15 Jan 2025 17:33:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736962413; cv=none; b=lsACKZLYwAwBJzNwC9Bu82rALsc3RlVrUTViTqhHMVCL7RCh+JExQsw9lGbt4fM+2YYOmzhX0vmnnqG76yy6m4zopAYVNOajuhLA7009ComoEjG1L+CXMIrD99sqTYtcRGYVrWKM/Z3ZBxnkJoUujb/K0zQvkiN09owqqcX/rvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736962413; c=relaxed/simple; bh=ARIk+9NqKhtoui7VcoODdebFlMlXwR30ub418qR58tU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RO4IMFWjjxThAQNv+cMPtKlWX+c4hosX6CsE4E0iqRiZU1yeH9IkpSVEfmUtGntNN4MBfd+7a56YGXEEmhhQsOKGguQ54Ua7rmjy73XjyTSvoCoNrX6n71iyZCAqozbzJSRrZEp+90mYHbEXVJMVZ+Qtqfm7DlCzUb2jN3h6ahQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TlSy8LDz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TlSy8LDz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2BD4C4CED1; Wed, 15 Jan 2025 17:33:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736962413; bh=ARIk+9NqKhtoui7VcoODdebFlMlXwR30ub418qR58tU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TlSy8LDzXzOpjtwdPVFvEoFYT5N4F0Ihzwa6yNDZcOwznO6ZdICydVjtcR5R7K0rV uDKvTGYd8ZabNxiBnJVuRmUtzg1WukP5y48WbmZXSRbeMhAqQmTj4jDJHfl2NNmFvq VuLIOKm/3Ged7F72b4oM23o6MYD/K0oZ4r7/Y1W7HaWAJ8hREhayGbOeZmlM2KFYVw WYu8IJxt7mtbXxDy60i523oY75EPjXOmA+hjWHtp5tZwG/v/GoIsnI0QJbKffWOFTl +zMnA2SiScgNhSs86S+uP9/VzdVhgwL4hCNsno3PWeLhTBhz4yCOSffOE19tT/9/Mk qOIt2wgF3GZJg== From: Lorenzo Bianconi Date: Wed, 15 Jan 2025 18:32:30 +0100 Subject: [PATCH 1/2] dt-bindings: arm: airoha: Add the pbus-csr node for EN7581 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250115-en7581-pcie-pbus-csr-v1-1-40d8fcb9360f@kernel.org> References: <20250115-en7581-pcie-pbus-csr-v1-0-40d8fcb9360f@kernel.org> In-Reply-To: <20250115-en7581-pcie-pbus-csr-v1-0-40d8fcb9360f@kernel.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 This patch adds the pbus-csr document bindings for EN7581 SoC. The airoha pbus-csr block provides a configuration interface for the PBUS controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. Signed-off-by: Lorenzo Bianconi --- .../bindings/arm/airoha,en7581-pbus-csr.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml new file mode 100644 index 0000000000000000000000000000000000000000..80b237e195cd3607645efe3fda1eb6152134481c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-pbus-csr.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha,en7581-pbus-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Pbus CSR Controller for EN7581 SoC + +maintainers: + - Lorenzo Bianconi + +description: + The airoha pbus-csr block provides a configuration interface for the PBUS + controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. + +properties: + compatible: + items: + - enum: + - airoha,en7581-pbus-csr + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + syscon@1fbe3400 { + compatible = "airoha,en7581-pbus-csr", "syscon"; + reg = <0x0 0x1fbe3400 0x0 0xff>; + }; + }; From patchwork Wed Jan 15 17:32:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13940690 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47D3B1AB6CB; Wed, 15 Jan 2025 17:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736962416; cv=none; b=O38wGy+R4xUf0Q7iaJbbdFaYDpnhwAyVSb7p9jYw1fQnC8kkGP2Mr41ttlFXSkL/cRvUqUrebQzkx8RXUUaUlvHNq5lEgbaBJmcrPHgXu5ysouJcQWdWadbM6v16BuEnJULQqrk54zLjAQedfwOFFLjtt71BoWX8bfSNdXDESmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736962416; c=relaxed/simple; bh=X1iUr4Z3xOp2+2SXrinRazhxNTDYDO8wPhrfSPaaZSo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fNbkV5tUSyViWNcmLx9a82CpOHMm1Y/52ieulW/nXnqvwcXp5D/O4piJY8gyBYgZGvWfUCZSsqERWWb+xySxOJxnluKeFy/qfNQ9AmElsuf0Y68mjwIY0sT0fJEkHei8jasdio5ZkO3ZDPkDDLY3THRG4pjWCfTAjC3XSqIDBY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZeqyiJwQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZeqyiJwQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5FE2C4CED1; Wed, 15 Jan 2025 17:33:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736962416; bh=X1iUr4Z3xOp2+2SXrinRazhxNTDYDO8wPhrfSPaaZSo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZeqyiJwQ9iZpAtxKr6wN9eWfGdHiYrJgQL5e7HznK240KZxasrQt6U6xrrjw5YbeB KL8uk4SpYvjRObFhZbtlabjwjceDWuzBI/6sVKgRxReM7ddari+RbEHrr4rVsRaZml +9j5GSHQlAARPemjSdclwryAtAJ743Ql6dNyiYy7MwZaH2exoCf5V/fBsRmHtMJfpS 27lCE+0/Di4H6Wr6ej36NGPwHlkZPX7JGTcbb+dx3KH0u36EIE9u1HYWvlQ0KDbUMe GcOIEYVAe+TEAXcOjRFlxfUeXndppK0g8ArtOSBBvUYFN7hqPIj580FA/QGhJHKWF3 jcmomyEPWN2tQ== From: Lorenzo Bianconi Date: Wed, 15 Jan 2025 18:32:31 +0100 Subject: [PATCH 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250115-en7581-pcie-pbus-csr-v1-2-40d8fcb9360f@kernel.org> References: <20250115-en7581-pcie-pbus-csr-v1-0-40d8fcb9360f@kernel.org> In-Reply-To: <20250115-en7581-pcie-pbus-csr-v1-0-40d8fcb9360f@kernel.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Configure PBus base address and address mask in order to allow the hw detecting if a given address is on PCIE0, PCIE1 or PCIE2. Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index aa24ac9aaecc749b53cfc4faf6399913d20cdbf2..b172a46cf95a9c728291c5b7a88457d3b725681a 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -127,6 +129,13 @@ #define PCIE_MTK_RESET_TIME_US 10 +#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3)) +#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3)) +#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \ + ((_n) == 2 ? 0x28000000 : \ + (_n) == 1 ? 0x24000000 : 0x20000000) +#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26) + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -931,7 +940,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; - int err; + struct regmap *map; + int err, slot; u32 val; /* @@ -945,6 +955,23 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) /* Wait for the time needed to complete the reset lines assert. */ msleep(PCIE_EN7581_RESET_TIME_MS); + map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* + * Configure PBus base address and address mask in order to allow the + * hw detecting if a given address is on PCIE0, PCIE1 or PCIE2. + */ + slot = of_get_pci_domain_nr(dev->of_node); + if (slot < 0) + return slot; + + regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot), + PCIE_EN7581_PBUS_BASE_ADDR(slot)); + regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot), + PCIE_EN7581_PBUS_BASE_ADDR_MASK); + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert.