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Thu, 16 Jan 2025 07:52:55 -0800 From: Mohan Kumar D To: , , CC: , , , , Mohan Kumar D , kernel test robot Subject: [PATCH v2 1/2] dmaengine: tegra210-adma: Fix build error due to 64-by-32 division Date: Thu, 16 Jan 2025 21:22:19 +0530 Message-ID: <20250116155220.3896947-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116155220.3896947-1-mkumard@nvidia.com> References: <20250116155220.3896947-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006002:EE_|SJ2PR12MB8181:EE_ X-MS-Office365-Filtering-Correlation-Id: 1de803d3-cace-46e8-b8d7-08dd3645e26d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: S+jJ5NUxCkTv8eZIYP5O+r2Du2YPlc3hV1XqJ6TXTt6jks72aOkelC4Y6rMXeNHzK2/UFRRRp6lgTZ2qvOQAKDh/EuhTPkhWbZZgYrY+kJq7q0Oq933707fZtF+mlv3yNMZsObxV5WVBVdeP836SUn3ASRDaHhAcuDWdu1yf74WjGK3lelQaYnabGSuzqW/hqeA6vHgIBnquTdb6BFUmi3Fj/SP4wO2XlwPvi9ZbWwq90ujCh/wrb0YdzPgF2BuGs7/ueGP65VAlAsfUgM1pFFV/SdT04uVrZ31WkVitgijrWTUeIQK9PEiGSP33VkTJj3DYZIzCwKPGSJEaIh2UPVIi2WFxXlO48O27QPdGirQWxTPXI3zFV+nh+0jDdYL6cB/uv5KPZifTh+ojgekHRXKTnatWgg/rW9CSYDP4mR1vqbnyGPVBUZNdPWggQk9zG2Lj02hqiZ0Ls3d+eVarAtpqqEv/asu6pq4UiqyOKoEP2PEb4O+P/t8Bx8bNhZig4zg4pekfMCdU3oLGCHOMB4AoGPTYH9c4eJgXTXQoKtjLNx8dPpjIOdxFOZQ+VZs2THRqBzYRi3O92Mzg1QqfFMwwaUxaai7dp8+eXx3osRDbco2L4vtKFkjBpSYH2AMD4vGljGeO1+IXCq9rR3KK3+fl47OiFPTivf/4k+sn6c4jU/Sr6SG766TtfigK3TnfrF7aXcCaVDkz8Xl2Fzg+OMcNSpllgDWsgRUuNHC/pqY8zEPaLm/6A1JxdwBf8yOwC0GpYYjQVkyKLvFxsxOvIVmjhTP0bafguiFXkHtKKZSy8WuFGNMwLwCvcdNLpWCfWztMuNEzhECbL1XDLPq5alFfph1zamPJpMdzXhtnb4PXN1WrmqkfOXcxaMd0FHI34Elok/C7Cy5W5lk03MeED60Rcd7Ijxp4p9MBBxBXr9yx6ooEAfFkavG8zKaWBMC1e0t7/LOcnzo0XxLe9QLkBVtPPHxpGRwUNpTfjur3rLH/cj648Uan3x5XUdNGjJjPBaGLo1iYxOJk7dnPAASK1PnebMehe1955ZwY1iaMu5ozBlqfeg25hIumYTuRGAdyfvPnEFE0VaKIIKNKxm6rM2xiIWGbocVz2bEx/epkL5cExcaOZpWyUgwEZhnNztQFUgxOUla2VFp+hm+qdBUnGoRDtccBJ5Y/U/JHNnfbNuggUQ+m2XKF2J92hRaWi76WdoedaEBWAZ5OPoh+CF1QNI+Ythx30au5QZSYeExHV+aXwB5ms7xparSt6PrTE45MtrOPrBsrT0903QiITJ/oisiL3Uu7wVTv/aYFNXtg+GCGijBjP0u7zb5n/LYzXbPSxjI3ESikzCX2kShzvNel2V0o8pcWAOLhDrgJ8sRIjaNQZjNn8WW5SGHxukl0u+vyvGi6rnNULT8PBjDPOpFeby6f+KJbqsTcDpSueSe55DpLCD1wVNZWk6P6Q2JwXIF4bM0B14eNTkmLYmO0Zm1V9JP4j+GS+eRhFqXu0TgqdXs= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 15:53:13.3932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1de803d3-cace-46e8-b8d7-08dd3645e26d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006002.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8181 Kernel test robot reported the build errors on 32-bit platforms due to plain 64-by-32 division. Following build erros were reported. "ERROR: modpost: "__udivdi3" [drivers/dma/tegra210-adma.ko] undefined! ld: drivers/dma/tegra210-adma.o: in function `tegra_adma_probe': tegra210-adma.c:(.text+0x12cf): undefined reference to `__udivdi3'" This can be fixed by using lower_32_bits() for the adma address space as the offset is constrained to the lower 32 bits Fixes: 68811c928f88 ("dmaengine: tegra210-adma: Support channel page") Cc: stable@vger.kernel.org Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202412250204.GCQhdKe3-lkp@intel.com/ Signed-off-by: Mohan Kumar D --- drivers/dma/tegra210-adma.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 6896da8ac7ef..258220c9cb50 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -887,7 +887,8 @@ static int tegra_adma_probe(struct platform_device *pdev) const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; struct resource *res_page, *res_base; - int ret, i, page_no; + unsigned int page_no, page_offset; + int ret, i; cdata = of_device_get_match_data(&pdev->dev); if (!cdata) { @@ -914,9 +915,16 @@ static int tegra_adma_probe(struct platform_device *pdev) res_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global"); if (res_base) { - page_no = (res_page->start - res_base->start) / cdata->ch_base_offset; - if (page_no <= 0) + if (WARN_ON(lower_32_bits(res_page->start) <= + lower_32_bits(res_base->start))) + return -EINVAL; + + page_offset = lower_32_bits(res_page->start) - + lower_32_bits(res_base->start); + page_no = page_offset / cdata->ch_base_offset; + if (page_no == 0) return -EINVAL; + tdma->ch_page_no = page_no - 1; tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); if (IS_ERR(tdma->base_addr)) From patchwork Thu Jan 16 15:52:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar D X-Patchwork-Id: 13941853 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2082.outbound.protection.outlook.com [40.107.92.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C43D22CA19; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 15:53:16.3835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45c9aace-a1ae-45ab-a11b-08dd3645e433 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8472 Have additional check for max channel page during the probe to cover if any offset overshoot happens due to wrong DT configuration. Fixes: 68811c928f88 ("dmaengine: tegra210-adma: Support channel page") Cc: stable@vger.kernel.org Signed-off-by: Mohan Kumar D --- drivers/dma/tegra210-adma.c | 7 ++++++- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 258220c9cb50..393e8a8a5bc1 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -83,7 +83,9 @@ struct tegra_adma; * @nr_channels: Number of DMA channels available. * @ch_fifo_size_mask: Mask for FIFO size field. * @sreq_index_offset: Slave channel index offset. + * @max_page: Maximum ADMA Channel Page. * @has_outstanding_reqs: If DMA channel can have outstanding requests. + * @set_global_pg_config: Global page programming. */ struct tegra_adma_chip_data { unsigned int (*adma_get_burst_config)(unsigned int burst_size); @@ -99,6 +101,7 @@ struct tegra_adma_chip_data { unsigned int nr_channels; unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; + unsigned int max_page; bool has_outstanding_reqs; void (*set_global_pg_config)(struct tegra_adma *tdma); }; @@ -854,6 +857,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { .nr_channels = 22, .ch_fifo_size_mask = 0xf, .sreq_index_offset = 2, + .max_page = 0, .has_outstanding_reqs = false, .set_global_pg_config = NULL, }; @@ -871,6 +875,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { .nr_channels = 32, .ch_fifo_size_mask = 0x1f, .sreq_index_offset = 4, + .max_page = 4, .has_outstanding_reqs = true, .set_global_pg_config = tegra186_adma_global_page_config, }; @@ -922,7 +927,7 @@ static int tegra_adma_probe(struct platform_device *pdev) page_offset = lower_32_bits(res_page->start) - lower_32_bits(res_base->start); page_no = page_offset / cdata->ch_base_offset; - if (page_no == 0) + if (page_no == 0 || page_no > cdata->max_page) return -EINVAL; tdma->ch_page_no = page_no - 1; diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 45004f598e4d..2af939bab62b 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -466,7 +466,7 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + //fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));