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Thu, 16 Jan 2025 08:20:38 -0800 From: Mohan Kumar D To: , , CC: , , , , Mohan Kumar D , kernel test robot Subject: [PATCH v3 1/2] dmaengine: tegra210-adma: Fix build error due to 64-by-32 division Date: Thu, 16 Jan 2025 21:50:32 +0530 Message-ID: <20250116162033.3922252-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116162033.3922252-1-mkumard@nvidia.com> References: <20250116162033.3922252-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E2:EE_|CY5PR12MB6180:EE_ X-MS-Office365-Filtering-Correlation-Id: e2a17ade-8da6-4a29-1c71-08dd3649c6e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: n7N+Uf0d07qCExtweaj3OgbL0jGAb31+5msbP0nlwp7CwWC/aA25LDhAOxBcANh37WkP4fZTh3ehuEhE/IFJoFLJ8pgbfE7UNI8kRcOrCtcWes+Ma71IP1sku9iU/lKuwi/GmH+7JZ3lBIYWnPGWAgdlE4agtPO3RxEUKgmlgU8YgumFKpZbxu+m4W541C9UvsQnyR5nQng0Zp7Fp6uwxnRAKvcf2vXTD4xMFNC0pDb/yFsqxUI4ZYjEv53nghUnGFdFO+/4txzOTQwoAxfDoF4VlVCqFNMZR8/9yK99EB2O7zxzzp4W/OTHOWNPf2UYO5CBkLm8SIb8fhklBu+ueqfeyAkso69R/Hrbl6RlYgi5hBAQ92NZR48l9uXTJeecnX19dPC//KMgf7WEnndAsDtEsYFTpAX01lVn/R7FXHQZHYOCO6dMrnwZo43IFaXHiqzm7/VCEK4FKBsBKHIkwxddSIWeZZXJ/kSCcFtEQrAMogYGkYqdtNsTfVWWe1Y5bIamBg0QDRLolXQsIvqHcf4de3r+zBr6xn+yI7ImWQAhXkeA4Q/b2GgUPR01y0Ns9GRpPfiYFS+N247XP21sICNNIF58WoZEzwwOdzAIdKHLMnNdOV2H74vmochWOLT3VLKZ04eTvFkMxDWi0Y7Jr7DItVp/2IAptS5Tnzna6PFdm1fOW1DO38bDSH+EaU2OzxL+TmTXP2Y4W2jR+LvHa8UvaNwYP/GMWJlYQSiDjT1iVY/wN4VfkGcVTyNZoA9FIoeHz8+XQYiXce9WqFiP7jbfpq2FokRPo/T7rqeJ/1QDZTqjP0TsTwR7ZWpyxW7KXglSPAa1pvMRjbvqxGK6cgCPhEiBmPNzTcVZnpwJRMW++h7vYGBNNqUDznPfXaCIU5rH/DF9bR117/1MX+lsvGIL1tkN5sVHDOiSaPDP5hAI8FnG7u4SlEST4Drz3VCVPOuGxYyyM5SKHDvGwreJaVO2+VI03S/lZZRBkhVTOwP07eNDt26x1Qt5F0M1ABxzjTlmQEF843HJ1nJxS2avenWlKlm8wzvVEV9EZdo/W5TdxbcT9ZZMMv47T6oAEAvg38MkKbVzUTAiwDnplHrBztJETKtSXRGHL1oIrtMbd8/4tD5QuKItrz5ABesmH3NKlBRS4ptpky+bEUUZjv1Nbty9QRx0dI9F+XylgwrGOyhPKyqCLNbKC2hsq8N18bpU0GeM033tygTvUiTOh/+0x6ztKLhLSgETA9cVuloiAovcuRLdgzQEJgh4LAbD61SV0cbrTrvr6wtSO+3sG78M2M2P+AuDHt5MJfDI6LWSaJl5h2CByZYBvQYKroc8PWoqQIX3EDcp56errXNc0QcP+qkWWl3wBeJ3+qHHiLL7IesqCsmE20h/LiRYgsztXsmaAI9gGNIQXNSXuXoTB5Wz2Wv2Zl72PEdmev2XEksU3X+RphcKmWwpJhnvVJ8OvwcdkxWvJpWi16JSAKHWxhGAeR+KEZeKqLQG5kr0dBdYUyg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 16:21:05.2085 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2a17ade-8da6-4a29-1c71-08dd3649c6e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6180 Kernel test robot reported the build errors on 32-bit platforms due to plain 64-by-32 division. Following build erros were reported. "ERROR: modpost: "__udivdi3" [drivers/dma/tegra210-adma.ko] undefined! ld: drivers/dma/tegra210-adma.o: in function `tegra_adma_probe': tegra210-adma.c:(.text+0x12cf): undefined reference to `__udivdi3'" This can be fixed by using lower_32_bits() for the adma address space as the offset is constrained to the lower 32 bits Fixes: 68811c928f88 ("dmaengine: tegra210-adma: Support channel page") Cc: stable@vger.kernel.org Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202412250204.GCQhdKe3-lkp@intel.com/ Signed-off-by: Mohan Kumar D Reviewed-by: Jon Hunter --- drivers/dma/tegra210-adma.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 6896da8ac7ef..258220c9cb50 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -887,7 +887,8 @@ static int tegra_adma_probe(struct platform_device *pdev) const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; struct resource *res_page, *res_base; - int ret, i, page_no; + unsigned int page_no, page_offset; + int ret, i; cdata = of_device_get_match_data(&pdev->dev); if (!cdata) { @@ -914,9 +915,16 @@ static int tegra_adma_probe(struct platform_device *pdev) res_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global"); if (res_base) { - page_no = (res_page->start - res_base->start) / cdata->ch_base_offset; - if (page_no <= 0) + if (WARN_ON(lower_32_bits(res_page->start) <= + lower_32_bits(res_base->start))) + return -EINVAL; + + page_offset = lower_32_bits(res_page->start) - + lower_32_bits(res_base->start); + page_no = page_offset / cdata->ch_base_offset; + if (page_no == 0) return -EINVAL; + tdma->ch_page_no = page_no - 1; tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); if (IS_ERR(tdma->base_addr)) From patchwork Thu Jan 16 16:20:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar D X-Patchwork-Id: 13941919 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2077.outbound.protection.outlook.com [40.107.223.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF05F1D86F6; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2025 16:21:07.1173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 307e1fad-3191-4f8b-c073-08dd3649c80b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8923 Have additional check for max channel page during the probe to cover if any offset overshoot happens due to wrong DT configuration. Fixes: 68811c928f88 ("dmaengine: tegra210-adma: Support channel page") Cc: stable@vger.kernel.org Signed-off-by: Mohan Kumar D Reviewed-by: Jon Hunter --- drivers/dma/tegra210-adma.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 258220c9cb50..393e8a8a5bc1 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -83,7 +83,9 @@ struct tegra_adma; * @nr_channels: Number of DMA channels available. * @ch_fifo_size_mask: Mask for FIFO size field. * @sreq_index_offset: Slave channel index offset. + * @max_page: Maximum ADMA Channel Page. * @has_outstanding_reqs: If DMA channel can have outstanding requests. + * @set_global_pg_config: Global page programming. */ struct tegra_adma_chip_data { unsigned int (*adma_get_burst_config)(unsigned int burst_size); @@ -99,6 +101,7 @@ struct tegra_adma_chip_data { unsigned int nr_channels; unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; + unsigned int max_page; bool has_outstanding_reqs; void (*set_global_pg_config)(struct tegra_adma *tdma); }; @@ -854,6 +857,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { .nr_channels = 22, .ch_fifo_size_mask = 0xf, .sreq_index_offset = 2, + .max_page = 0, .has_outstanding_reqs = false, .set_global_pg_config = NULL, }; @@ -871,6 +875,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { .nr_channels = 32, .ch_fifo_size_mask = 0x1f, .sreq_index_offset = 4, + .max_page = 4, .has_outstanding_reqs = true, .set_global_pg_config = tegra186_adma_global_page_config, }; @@ -922,7 +927,7 @@ static int tegra_adma_probe(struct platform_device *pdev) page_offset = lower_32_bits(res_page->start) - lower_32_bits(res_base->start); page_no = page_offset / cdata->ch_base_offset; - if (page_no == 0) + if (page_no == 0 || page_no > cdata->max_page) return -EINVAL; tdma->ch_page_no = page_no - 1;